Lines Matching +full:hba +full:- +full:cap
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
49 u32 cap; member
99 return (i < timeout_msec) ? 0 : -1; in waiting_for_cmd_completed()
104 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_setup_oobr()
106 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); in ahci_setup_oobr()
107 writel(0x02060b14, &host_mmio->oobr); in ahci_setup_oobr()
117 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_host_init()
120 cap_save = readl(&host_mmio->cap); in ahci_host_init()
124 tmp = readl(&host_mmio->ghc); in ahci_host_init()
126 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc); in ahci_host_init()
128 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout) in ahci_host_init()
133 return -1; in ahci_host_init()
137 writel(clk / 1000, &host_mmio->timer1ms); in ahci_host_init()
141 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc); in ahci_host_init()
142 writel(cap_save, &host_mmio->cap); in ahci_host_init()
144 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi); in ahci_host_init()
152 uc_priv->cap = readl(&host_mmio->cap); in ahci_host_init()
153 uc_priv->port_map = readl(&host_mmio->pi); in ahci_host_init()
155 /* Determine how many command slots the HBA supports */ in ahci_host_init()
156 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1; in ahci_host_init()
158 debug("cap 0x%x port_map 0x%x n_ports %d\n", in ahci_host_init()
159 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); in ahci_host_init()
161 for (i = 0; i < uc_priv->n_ports; i++) { in ahci_host_init()
162 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); in ahci_host_init()
163 port_mmio = uc_priv->port[i].port_mmio; in ahci_host_init()
166 tmp = readl(&port_mmio->cmd); in ahci_host_init()
181 writel_with_flush(tmp, &port_mmio->cmd); in ahci_host_init()
190 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) in ahci_host_init()
191 && --timeout) in ahci_host_init()
196 return -1; in ahci_host_init()
200 /* Spin-up device */ in ahci_host_init()
201 tmp = readl(&port_mmio->cmd); in ahci_host_init()
202 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd); in ahci_host_init()
204 /* Wait for spin-up to finish */ in ahci_host_init()
206 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) in ahci_host_init()
207 && --timeout) in ahci_host_init()
210 debug("Spin-Up can't finish!\n"); in ahci_host_init()
211 return -1; in ahci_host_init()
216 tmp = readl(&port_mmio->ssts); in ahci_host_init()
224 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) in ahci_host_init()
225 && --timeout) in ahci_host_init()
229 return -1; in ahci_host_init()
237 tmp = readl(&port_mmio->serr); in ahci_host_init()
240 writel(tmp, &port_mmio->serr); in ahci_host_init()
243 tmp = readl(&host_mmio->is); in ahci_host_init()
246 writel(tmp, &host_mmio->is); in ahci_host_init()
248 writel(1 << i, &host_mmio->is); in ahci_host_init()
251 writel(DEF_PORT_IRQ, &port_mmio->ie); in ahci_host_init()
254 tmp = readl(&port_mmio->ssts); in ahci_host_init()
257 uc_priv->link_port_map |= (0x01 << i); in ahci_host_init()
260 tmp = readl(&host_mmio->ghc); in ahci_host_init()
262 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc); in ahci_host_init()
263 tmp = readl(&host_mmio->ghc); in ahci_host_init()
271 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_print_info()
272 u32 vers, cap, impl, speed; in ahci_print_info() local
276 vers = readl(&host_mmio->vs); in ahci_print_info()
277 cap = uc_priv->cap; in ahci_print_info()
278 impl = uc_priv->port_map; in ahci_print_info()
280 speed = (cap & SATA_HOST_CAP_ISS_MASK) in ahci_print_info()
297 ((cap >> 8) & 0x1f) + 1, in ahci_print_info()
298 (cap & 0x1f) + 1, in ahci_print_info()
306 cap & (1 << 31) ? "64bit " : "", in ahci_print_info()
307 cap & (1 << 30) ? "ncq " : "", in ahci_print_info()
308 cap & (1 << 28) ? "ilck " : "", in ahci_print_info()
309 cap & (1 << 27) ? "stag " : "", in ahci_print_info()
310 cap & (1 << 26) ? "pm " : "", in ahci_print_info()
311 cap & (1 << 25) ? "led " : "", in ahci_print_info()
312 cap & (1 << 24) ? "clo " : "", in ahci_print_info()
313 cap & (1 << 19) ? "nz " : "", in ahci_print_info()
314 cap & (1 << 18) ? "only " : "", in ahci_print_info()
315 cap & (1 << 17) ? "pmp " : "", in ahci_print_info()
316 cap & (1 << 15) ? "pio " : "", in ahci_print_info()
317 cap & (1 << 14) ? "slum " : "", in ahci_print_info()
318 cap & (1 << 13) ? "part " : ""); in ahci_print_info()
324 struct ahci_ioports *pp = &uc_priv->port[port]; in ahci_fill_sg()
325 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; in ahci_fill_sg()
330 sg_count = ((buf_len - 1) / max_bytes) + 1; in ahci_fill_sg()
333 return -1; in ahci_fill_sg()
337 ahci_sg->addr = in ahci_fill_sg()
339 ahci_sg->addr_hi = 0; in ahci_fill_sg()
340 ahci_sg->flags_size = cpu_to_le32(0x3fffff & in ahci_fill_sg()
342 ? (buf_len - 1) in ahci_fill_sg()
343 : (max_bytes - 1))); in ahci_fill_sg()
345 buf_len -= max_bytes; in ahci_fill_sg()
353 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + in ahci_fill_cmd_slot()
357 cmd_hdr->opts = cpu_to_le32(opts); in ahci_fill_cmd_slot()
358 cmd_hdr->status = 0; in ahci_fill_cmd_slot()
359 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); in ahci_fill_cmd_slot()
361 pp->cmd_slot->tbl_addr_hi = in ahci_fill_cmd_slot()
362 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); in ahci_fill_cmd_slot()
372 struct ahci_ioports *pp = &uc_priv->port[port]; in ahci_exec_ata_cmd()
373 struct sata_port_regs *port_mmio = pp->port_mmio; in ahci_exec_ata_cmd()
377 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci)); in ahci_exec_ata_cmd()
390 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); in ahci_exec_ata_cmd()
400 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); in ahci_exec_ata_cmd()
401 writel_with_flush(1 << cmd_slot, &port_mmio->ci); in ahci_exec_ata_cmd()
403 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, in ahci_exec_ata_cmd()
406 return -1; in ahci_exec_ata_cmd()
408 invalidate_dcache_range((int)(pp->cmd_slot), in ahci_exec_ata_cmd()
409 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); in ahci_exec_ata_cmd()
411 pp->cmd_slot->status); in ahci_exec_ata_cmd()
424 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; in ahci_set_feature()
425 cfis->pm_port_c = 1 << 7; in ahci_set_feature()
426 cfis->command = ATA_CMD_SET_FEATURES; in ahci_set_feature()
427 cfis->features = SETFEATURES_XFER; in ahci_set_feature()
428 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e; in ahci_set_feature()
435 struct ahci_ioports *pp = &uc_priv->port[port]; in ahci_port_start()
436 struct sata_port_regs *port_mmio = pp->port_mmio; in ahci_port_start()
442 port_status = readl(&port_mmio->ssts); in ahci_port_start()
446 return -1; in ahci_port_start()
453 return -ENOMEM; in ahci_port_start()
456 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ in ahci_port_start()
460 * First item in chunk of DMA memory: 32-slot command table, in ahci_port_start()
463 pp->cmd_slot = (struct ahci_cmd_hdr *)mem; in ahci_port_start()
464 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); in ahci_port_start()
468 * Second item: Received-FIS area, 256-Byte aligned in ahci_port_start()
470 pp->rx_fis = mem; in ahci_port_start()
475 * and its scatter-gather table in ahci_port_start()
477 pp->cmd_tbl = mem; in ahci_port_start()
478 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); in ahci_port_start()
482 writel_with_flush(0x00004444, &port_mmio->dmacr); in ahci_port_start()
483 pp->cmd_tbl_sg = (struct ahci_sg *)mem; in ahci_port_start()
484 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); in ahci_port_start()
485 writel_with_flush(pp->rx_fis, &port_mmio->fb); in ahci_port_start()
488 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), in ahci_port_start()
489 &port_mmio->cmd); in ahci_port_start()
492 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR | in ahci_port_start()
494 && --timeout) in ahci_port_start()
499 return -1; in ahci_port_start()
504 PORT_CMD_START, &port_mmio->cmd); in ahci_port_start()
517 pdev->product, pdev->vendor, pdev->revision, pdev->lba); in dwc_ahsata_print_info()
521 pdev->product, pdev->vendor, pdev->revision, pdev->lba); in dwc_ahsata_print_info()
529 u8 port = uc_priv->hard_port_no; in dwc_ahsata_identify()
533 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; in dwc_ahsata_identify()
534 cfis->pm_port_c = 0x80; /* is command */ in dwc_ahsata_identify()
535 cfis->command = ATA_CMD_ID_ATA; in dwc_ahsata_identify()
544 uc_priv->pio_mask = id[ATA_ID_PIO_MODES]; in dwc_ahsata_xfer_mode()
545 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES]; in dwc_ahsata_xfer_mode()
546 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask); in dwc_ahsata_xfer_mode()
554 u8 port = uc_priv->hard_port_no; in dwc_ahsata_rw_cmd()
561 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; in dwc_ahsata_rw_cmd()
562 cfis->pm_port_c = 0x80; /* is command */ in dwc_ahsata_rw_cmd()
563 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; in dwc_ahsata_rw_cmd()
564 cfis->device = ATA_LBA; in dwc_ahsata_rw_cmd()
566 cfis->device |= (block >> 24) & 0xf; in dwc_ahsata_rw_cmd()
567 cfis->lba_high = (block >> 16) & 0xff; in dwc_ahsata_rw_cmd()
568 cfis->lba_mid = (block >> 8) & 0xff; in dwc_ahsata_rw_cmd()
569 cfis->lba_low = block & 0xff; in dwc_ahsata_rw_cmd()
570 cfis->sector_count = (u8)(blkcnt & 0xff); in dwc_ahsata_rw_cmd()
583 u8 port = uc_priv->hard_port_no; in dwc_ahsata_flush_cache()
587 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; in dwc_ahsata_flush_cache()
588 cfis->pm_port_c = 0x80; /* is command */ in dwc_ahsata_flush_cache()
589 cfis->command = ATA_CMD_FLUSH; in dwc_ahsata_flush_cache()
599 u8 port = uc_priv->hard_port_no; in dwc_ahsata_rw_cmd_ext()
606 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; in dwc_ahsata_rw_cmd_ext()
607 cfis->pm_port_c = 0x80; /* is command */ in dwc_ahsata_rw_cmd_ext()
609 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT in dwc_ahsata_rw_cmd_ext()
612 cfis->lba_high_exp = (block >> 40) & 0xff; in dwc_ahsata_rw_cmd_ext()
613 cfis->lba_mid_exp = (block >> 32) & 0xff; in dwc_ahsata_rw_cmd_ext()
614 cfis->lba_low_exp = (block >> 24) & 0xff; in dwc_ahsata_rw_cmd_ext()
615 cfis->lba_high = (block >> 16) & 0xff; in dwc_ahsata_rw_cmd_ext()
616 cfis->lba_mid = (block >> 8) & 0xff; in dwc_ahsata_rw_cmd_ext()
617 cfis->lba_low = block & 0xff; in dwc_ahsata_rw_cmd_ext()
618 cfis->device = ATA_LBA; in dwc_ahsata_rw_cmd_ext()
619 cfis->sector_count_exp = (blkcnt >> 8) & 0xff; in dwc_ahsata_rw_cmd_ext()
620 cfis->sector_count = blkcnt & 0xff; in dwc_ahsata_rw_cmd_ext()
633 u8 port = uc_priv->hard_port_no; in dwc_ahsata_flush_cache_ext()
637 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; in dwc_ahsata_flush_cache_ext()
638 cfis->pm_port_c = 0x80; /* is command */ in dwc_ahsata_flush_cache_ext()
639 cfis->command = ATA_CMD_FLUSH_EXT; in dwc_ahsata_flush_cache_ext()
647 uc_priv->flags |= SATA_FLAG_WCACHE; in dwc_ahsata_init_wcache()
649 uc_priv->flags |= SATA_FLAG_FLUSH; in dwc_ahsata_init_wcache()
651 uc_priv->flags |= SATA_FLAG_FLUSH_EXT; in dwc_ahsata_init_wcache()
675 blks -= max_blks; in ata_low_level_rw_lba48()
710 blks -= max_blks; in ata_low_level_rw_lba28()
730 linkmap = uc_priv->link_port_map; in dwc_ahci_start_ports()
734 return -ENXIO; in dwc_ahci_start_ports()
737 for (i = 0; i < uc_priv->n_ports; i++) { in dwc_ahci_start_ports()
743 uc_priv->hard_port_no = i; in dwc_ahci_start_ports()
758 u8 port = uc_priv->hard_port_no; in dwc_ahsata_scan_common()
766 memcpy(pdev->product, serial, sizeof(serial)); in dwc_ahsata_scan_common()
770 memcpy(pdev->revision, firmware, sizeof(firmware)); in dwc_ahsata_scan_common()
774 memcpy(pdev->vendor, product, sizeof(product)); in dwc_ahsata_scan_common()
778 pdev->lba = (u32)n_sectors; in dwc_ahsata_scan_common()
780 pdev->type = DEV_TYPE_HARDDISK; in dwc_ahsata_scan_common()
781 pdev->blksz = ATA_SECT_SIZE; in dwc_ahsata_scan_common()
782 pdev->lun = 0; in dwc_ahsata_scan_common()
786 pdev->lba48 = 1; in dwc_ahsata_scan_common()
791 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK); in dwc_ahsata_scan_common()
792 uc_priv->flags |= ata_id_queue_depth(id); in dwc_ahsata_scan_common()
817 if (desc->lba48) in sata_read_common()
832 u32 flags = uc_priv->flags; in sata_write_common()
834 if (desc->lba48) { in sata_write_common()
857 uc_priv->dev = pdev; in ahci_init_one()
859 uc_priv->host_flags = ATA_FLAG_SATA in ahci_init_one()
865 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; in ahci_init_one()
891 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { in init_sata()
893 return -1; in init_sata()
908 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { in reset_sata()
910 return -1; in reset_sata()
918 host_mmio = uc_priv->mmio_base; in reset_sata()
919 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); in reset_sata()
920 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) in reset_sata()
931 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) in sata_port_status()
932 return -EINVAL; in sata_port_status()
935 return -ENODEV; in sata_port_status()
938 port_mmio = uc_priv->port[port].port_mmio; in sata_port_status()
940 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; in sata_port_status()
978 port_mmio = uc_priv->port[port].port_mmio; in dwc_ahsata_port_status()
979 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO; in dwc_ahsata_port_status()
985 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in dwc_ahsata_bus_reset()
987 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); in dwc_ahsata_bus_reset()
988 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) in dwc_ahsata_bus_reset()
1009 IF_TYPE_SATA, -1, 512, 0, &blk); in dwc_ahsata_scan()
1031 uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | in dwc_ahsata_probe()
1033 uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev); in dwc_ahsata_probe()