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/openbmc/linux/tools/perf/pmu-events/arch/riscv/
H A Driscv-sbi-firmware.json39 "PublicDescription": "Sent IPI to other HART event",
42 "BriefDescription": "Sent IPI to other HART event"
45 "PublicDescription": "Received IPI from other HART event",
48 "BriefDescription": "Received IPI from other HART event"
51 "PublicDescription": "Sent FENCE.I request to other HART event",
54 "BriefDescription": "Sent FENCE.I request to other HART event"
57 "PublicDescription": "Received FENCE.I request from other HART event",
60 "BriefDescription": "Received FENCE.I request from other HART event"
63 "PublicDescription": "Sent SFENCE.VMA request to other HART event",
66 "BriefDescription": "Sent SFENCE.VMA request to other HART event"
[all …]
/openbmc/linux/arch/riscv/kernel/
H A Dcpu.c26 * Returns the hart ID of the given device tree node, or -ENODEV if the node
27 * isn't an enabled and valid RISC-V hart node.
29 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
33 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
34 if (*hart == ~0UL) { in riscv_of_processor_hartid()
35 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
39 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
49 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_early_of_processor_hartid() argument
58 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_early_of_processor_hartid()
59 if (*hart == ~0UL) { in riscv_early_of_processor_hartid()
[all …]
H A Dsmpboot.c84 unsigned long hart; in acpi_parse_rintc() local
101 hart = processor->hart_id; in acpi_parse_rintc()
102 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
107 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
119 cpuid_to_hartid_map(cpu_count) = hart; in acpi_parse_rintc()
148 unsigned long hart; in of_parse_and_init_cpus() local
156 rc = riscv_early_of_processor_hartid(dn, &hart); in of_parse_and_init_cpus()
160 if (hart == cpuid_to_hartid_map(0)) { in of_parse_and_init_cpus()
168 cpuid, hart); in of_parse_and_init_cpus()
172 cpuid_to_hartid_map(cpuid) = hart; in of_parse_and_init_cpus()
H A Dmachine_kexec.c133 * No more interrupts on this hart in machine_shutdown()
195 * suspended and this hart will be the new boot hart.
219 pr_notice("Will call new kernel at %08lx from hart id %lx\n", in machine_kexec()
223 /* Make sure the relocation code is visible to the hart */ in machine_kexec()
/openbmc/u-boot/arch/riscv/lib/
H A Dsifive_clint.c18 #define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) argument
20 #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) argument
47 int riscv_set_timecmp(int hart, u64 cmp) in riscv_set_timecmp() argument
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
56 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
60 writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_send_ipi()
65 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
69 writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_clear_ipi()
/openbmc/qemu/target/riscv/
H A Dtrace-events2 …ol async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d…
5 pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" P…
6 pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%"…
7 pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%…
8 pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write add…
10 mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
11 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
/openbmc/linux/Documentation/devicetree/bindings/iio/addac/
H A Dadi,ad74115.yaml70 10 - Current output with HART
71 11 - Current input, externally-powered, with HART
72 12 - Current input, loop-powered, with HART
188 adi,dac-hart-slew:
190 description: Whether to use a HART-compatible slew rate.
268 3 - Control HART CD
269 4 - Monitor HART CD
270 5 - Monitor HART EOM status
282 3 - Control HART RXD
283 4 - Monitor HART RXD
[all …]
/openbmc/qemu/include/hw/riscv/
H A Dboot_opensbi.h44 * Preferred boot HART id
51 * the previous booting stage can specify last HART that will jump
52 * to the FW_DYNAMIC firmware as the preferred boot HART.
54 * To avoid specifying a preferred boot HART, the previous booting
74 * Preferred boot HART id
81 * the previous booting stage can specify last HART that will jump
82 * to the FW_DYNAMIC firmware as the preferred boot HART.
84 * To avoid specifying a preferred boot HART, the previous booting
/openbmc/linux/arch/riscv/mm/
H A Dcacheflush.c34 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
37 * execution resumes on each hart.
46 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
49 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
63 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
64 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
66 * messages are sent we still need to order this hart's writes in flush_icache_mm()
H A Dcontext.c242 * we polluted the TLB of current HART so let's do TLB flushed in asids_init()
291 * behavior in a common case (a bunch of single-hart processes on a many-hart
294 * cache flush to be performed before execution resumes on each hart. This
296 * refers to the current hart.
308 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
/openbmc/linux/drivers/irqchip/
H A Dirq-riscv-intc.c38 * on the local hart, these functions can only be called on the hart that
81 * for the per-HART local interrupts and child irqchip drivers in riscv_intc_irq_eoi()
83 * chained handlers for the per-HART local interrupts. in riscv_intc_irq_eoi()
87 * will do unnecessary mask/unmask of per-HART local interrupts in riscv_intc_irq_eoi()
197 pr_warn("unable to find hart id for %pOF\n", node); in riscv_intc_init()
202 * The DT will have one INTC DT node under each CPU (or HART) in riscv_intc_init()
205 * for the INTC DT node belonging to boot CPU (or boot HART). in riscv_intc_init()
242 * The ACPI MADT will have one INTC for each CPU (or HART) in riscv_intc_acpi_init()
245 * for the INTC belonging to the boot CPU (or boot HART). in riscv_intc_acpi_init()
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
H A Dsifive,plic-1.0.0.yaml14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
19 privilege modes per hart; machine mode and supervisor mode.
/openbmc/linux/arch/riscv/include/asm/
H A Dcpu_ops_sbi.h16 * struct sbi_hart_boot_data - Hart specific boot used during booting and
18 * @task_ptr: A pointer to the hart specific tp
19 * @stack_ptr: A pointer to the hart specific sp
H A Dsmp.h62 /* Secondary hart entry */
66 * Obtains the hart ID of the currently executing task. This relies on
H A Dbarrier.h66 * task is marked as available for scheduling on a new hart. While I don't see
70 * the new hart.
/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml18 hart: A hardware execution context, which contains all the state
59 Identifies that the hart uses the RISC-V instruction set
60 and identifies the type of the hart.
65 hart. These values originate from the RISC-V Privileged
117 by this hart (see ./idle-states.yaml).
193 // Example 2: Spike ISA Simulator with 1 Hart
H A Dextensions.yaml18 This document defines properties that indicate whether a hart supports a
37 supported by the hart. These are documented in the RISC-V
56 The base ISA implemented by this hart, as described by the 20191213
65 description: Extensions supported by the hart.
/openbmc/linux/arch/csky/abiv2/
H A Dcacheflush.c47 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
71 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
/openbmc/openbmc/poky/meta/recipes-core/base-passwd/base-passwd/
H A D0004-Add-an-input-group-for-the-dev-input-devices.patch2 From: Darren Hart <dvhart@linux.intel.com>
7 Signed-off-by: Darren Hart <dvhart@linux.intel.com>
/openbmc/linux/tools/testing/selftests/futex/
H A Drun.sh13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
/openbmc/linux/tools/arch/riscv/include/uapi/asm/
H A Dunistd.h29 * kernel might schedule a process on another hart. There is no way for
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
/openbmc/linux/arch/riscv/include/uapi/asm/
H A Dunistd.h32 * kernel might schedule a process on another hart. There is no way for
34 * thread->hart mappings), so we've defined a RISC-V specific system call to
/openbmc/linux/tools/testing/selftests/futex/functional/
H A Drun.sh12 # Darren Hart <dvhart@linux.intel.com>
15 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
/openbmc/linux/tools/testing/selftests/futex/include/
H A Datomic.h11 * Darren Hart <dvhart@linux.intel.com>
14 * 2009-Nov-17: Initial version by Darren Hart <dvhart@linux.intel.com>

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