xref: /openbmc/linux/arch/csky/abiv2/cacheflush.c (revision e724e7aa)
100a9730eSGuo Ren // SPDX-License-Identifier: GPL-2.0
200a9730eSGuo Ren // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
300a9730eSGuo Ren 
400a9730eSGuo Ren #include <linux/cache.h>
500a9730eSGuo Ren #include <linux/highmem.h>
600a9730eSGuo Ren #include <linux/mm.h>
700a9730eSGuo Ren #include <asm/cache.h>
81f62ed00SGuo Ren #include <asm/tlbflush.h>
900a9730eSGuo Ren 
update_mmu_cache_range(struct vm_fault * vmf,struct vm_area_struct * vma,unsigned long address,pte_t * pte,unsigned int nr)10*e724e7aaSMatthew Wilcox (Oracle) void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
11*e724e7aaSMatthew Wilcox (Oracle) 		unsigned long address, pte_t *pte, unsigned int nr)
1200a9730eSGuo Ren {
13*e724e7aaSMatthew Wilcox (Oracle) 	unsigned long pfn = pte_pfn(*pte);
14*e724e7aaSMatthew Wilcox (Oracle) 	struct folio *folio;
15*e724e7aaSMatthew Wilcox (Oracle) 	unsigned int i;
1600a9730eSGuo Ren 
171f62ed00SGuo Ren 	flush_tlb_page(vma, address);
181f62ed00SGuo Ren 
19*e724e7aaSMatthew Wilcox (Oracle) 	if (!pfn_valid(pfn))
203e455cf5SGuo Ren 		return;
213e455cf5SGuo Ren 
22*e724e7aaSMatthew Wilcox (Oracle) 	folio = page_folio(pfn_to_page(pfn));
23*e724e7aaSMatthew Wilcox (Oracle) 
24*e724e7aaSMatthew Wilcox (Oracle) 	if (test_and_set_bit(PG_dcache_clean, &folio->flags))
2500a9730eSGuo Ren 		return;
2600a9730eSGuo Ren 
27*e724e7aaSMatthew Wilcox (Oracle) 	icache_inv_range(address, address + nr*PAGE_SIZE);
28*e724e7aaSMatthew Wilcox (Oracle) 	for (i = 0; i < folio_nr_pages(folio); i++) {
29*e724e7aaSMatthew Wilcox (Oracle) 		unsigned long addr = (unsigned long) kmap_local_folio(folio,
3000a9730eSGuo Ren 								i * PAGE_SIZE);
31d936a7e7SGuo Ren 
32d936a7e7SGuo Ren 		dcache_wb_range(addr, addr + PAGE_SIZE);
33d936a7e7SGuo Ren 		if (vma->vm_flags & VM_EXEC)
34*e724e7aaSMatthew Wilcox (Oracle) 			icache_inv_range(addr, addr + PAGE_SIZE);
35*e724e7aaSMatthew Wilcox (Oracle) 		kunmap_local((void *) addr);
3600a9730eSGuo Ren 	}
37997153b9SGuo Ren }
38997153b9SGuo Ren 
flush_icache_deferred(struct mm_struct * mm)39997153b9SGuo Ren void flush_icache_deferred(struct mm_struct *mm)
40997153b9SGuo Ren {
41997153b9SGuo Ren 	unsigned int cpu = smp_processor_id();
42997153b9SGuo Ren 	cpumask_t *mask = &mm->context.icache_stale_mask;
43997153b9SGuo Ren 
44997153b9SGuo Ren 	if (cpumask_test_cpu(cpu, mask)) {
45997153b9SGuo Ren 		cpumask_clear_cpu(cpu, mask);
46997153b9SGuo Ren 		/*
47997153b9SGuo Ren 		 * Ensure the remote hart's writes are visible to this hart.
48997153b9SGuo Ren 		 * This pairs with a barrier in flush_icache_mm.
49997153b9SGuo Ren 		 */
50997153b9SGuo Ren 		smp_mb();
51997153b9SGuo Ren 		local_icache_inv_all(NULL);
52997153b9SGuo Ren 	}
53997153b9SGuo Ren }
54997153b9SGuo Ren 
flush_icache_mm_range(struct mm_struct * mm,unsigned long start,unsigned long end)55997153b9SGuo Ren void flush_icache_mm_range(struct mm_struct *mm,
56997153b9SGuo Ren 		unsigned long start, unsigned long end)
57997153b9SGuo Ren {
58997153b9SGuo Ren 	unsigned int cpu;
59997153b9SGuo Ren 	cpumask_t others, *mask;
60997153b9SGuo Ren 
61997153b9SGuo Ren 	preempt_disable();
62997153b9SGuo Ren 
63997153b9SGuo Ren #ifdef CONFIG_CPU_HAS_ICACHE_INS
64997153b9SGuo Ren 	if (mm == current->mm) {
65997153b9SGuo Ren 		icache_inv_range(start, end);
66997153b9SGuo Ren 		preempt_enable();
67997153b9SGuo Ren 		return;
68997153b9SGuo Ren 	}
69997153b9SGuo Ren #endif
70997153b9SGuo Ren 
71997153b9SGuo Ren 	/* Mark every hart's icache as needing a flush for this MM. */
72997153b9SGuo Ren 	mask = &mm->context.icache_stale_mask;
73997153b9SGuo Ren 	cpumask_setall(mask);
74997153b9SGuo Ren 
75997153b9SGuo Ren 	/* Flush this hart's I$ now, and mark it as flushed. */
76997153b9SGuo Ren 	cpu = smp_processor_id();
77997153b9SGuo Ren 	cpumask_clear_cpu(cpu, mask);
78997153b9SGuo Ren 	local_icache_inv_all(NULL);
79997153b9SGuo Ren 
80997153b9SGuo Ren 	/*
81997153b9SGuo Ren 	 * Flush the I$ of other harts concurrently executing, and mark them as
82997153b9SGuo Ren 	 * flushed.
83997153b9SGuo Ren 	 */
84997153b9SGuo Ren 	cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
85997153b9SGuo Ren 
86997153b9SGuo Ren 	if (mm != current->active_mm || !cpumask_empty(&others)) {
87997153b9SGuo Ren 		on_each_cpu_mask(&others, local_icache_inv_all, NULL, 1);
88997153b9SGuo Ren 		cpumask_clear(mask);
89997153b9SGuo Ren 	}
90997153b9SGuo Ren 
91997153b9SGuo Ren 	preempt_enable();
92 }
93