Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0, v8.0.0, v7.2.0, v7.0.0, v6.2.0, v6.1.0 |
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3e9f48bc |
| 12-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging
A large collection of RISC-V fixes, improvements and features
- Clenaup some left over v1.9 code - D
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging
A large collection of RISC-V fixes, improvements and features
- Clenaup some left over v1.9 code - Documentation improvements - Support for the shakti_c machine - Internal cleanup of the CSR accesses - Updates to the OpenTitan platform - Support for the virtio-vga - Fix for the saturate subtract in vector extensions - Experimental support for the ePMP spec - A range of other internal code cleanups and bug fixes
# gpg: Signature made Tue 11 May 2021 11:17:10 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210511: (42 commits) target/riscv: Fix the RV64H decode comment target/riscv: Consolidate RV32/64 16-bit instructions target/riscv: Consolidate RV32/64 32-bit instructions target/riscv: Remove an unused CASE_OP_32_64 macro target/riscv: Remove the unused HSTATUS_WPRI macro target/riscv: Remove the hardcoded SATP_MODE macro target/riscv: Remove the hardcoded MSTATUS_SD macro target/riscv: Remove the hardcoded HGATP_MODE macro target/riscv: Remove the hardcoded SSTATUS_SD macro target/riscv: Remove the hardcoded RVXLEN macro target/riscv: fix a typo with interrupt names fpu/softfloat: set invalid excp flag for RISC-V muladd instructions hw/riscv: Fix OT IBEX reset vector target/riscv: fix exception index on instruction access fault target/riscv: fix vrgather macro index variable type bug target/riscv: Add ePMP support for the Ibex CPU target/riscv/pmp: Remove outdated comment target/riscv: Add a config option for ePMP target/riscv: Implementation of enhanced PMP (ePMP) target/riscv: Add ePMP CSR access functions ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2582a95c |
| 19-Apr-2021 |
Hou Weiying <weiying_hou@outlook.com> |
target/riscv: Add ePMP CSR access functions
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com> Signed-off-by: Hou Weiying <weiying_hou@outlook.com> Signed-off-by: Myriad-Dreamin <camiyoru@gmail.c
target/riscv: Add ePMP CSR access functions
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com> Signed-off-by: Hou Weiying <weiying_hou@outlook.com> Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com [ Changes by AF: - Rebase on master - Fix build errors - Fix some style issues ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Revision tags: v5.2.0 |
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922781b7 |
| 10-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
Pull request
v2: * Rebased after meson and resolved conflict in "softmmu: Add missing trace-events file" * D
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
Pull request
v2: * Rebased after meson and resolved conflict in "softmmu: Add missing trace-events file" * Dropped "meson: Don't make object files for dtrace on macOS" (already merged via Paolo's tree)
# gpg: Signature made Thu 10 Sep 2020 09:09:47 BST # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/tracing-pull-request: trace-events: Fix attribution of trace points to source trace-events: Delete unused trace points scripts/cleanup-trace-events: Emit files in alphabetical order scripts/cleanup-trace-events: Fix for vcpu property net/colo: Match is-enabled probe to tracepoint scripts/tracetool: Use void pointer for vcpu scripts/tracetool: Fix dtrace generation for macOS softmmu: Add missing trace-events file
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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b15e402f |
| 06-Aug-2020 |
Markus Armbruster <armbru@redhat.com> |
trace-events: Fix attribution of trace points to source
Some trace points are attributed to the wrong source file. Happens when we neglect to update trace-events for code motion, or add events in t
trace-events: Fix attribution of trace points to source
Some trace points are attributed to the wrong source file. Happens when we neglect to update trace-events for code motion, or add events in the wrong place, or misspell the file name.
Clean up with help of scripts/cleanup-trace-events.pl. Funnies requiring manual post-processing:
* accel/tcg/cputlb.c trace points are in trace-events.
* block.c and blockdev.c trace points are in block/trace-events.
* hw/block/nvme.c uses the preprocessor to hide its trace point use from cleanup-trace-events.pl.
* hw/tpm/tpm_spapr.c uses pseudo trace point tpm_spapr_show_buffer to guard debug code.
* include/hw/xen/xen_common.h trace points are in hw/xen/trace-events.
* linux-user/trace-events abbreviates a tedious list of filenames to */signal.c.
* net/colo-compare and net/filter-rewriter.c use pseudo trace points colo_compare_miscompare and colo_filter_rewriter_debug to guard debug code.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200806141334.3646302-5-armbru@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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Revision tags: v5.0.0, v4.2.0 |
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7cc0cdcd |
| 19-Sep-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3' into staging
RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3
This contains quite a few patches that I'd like to tar
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3' into staging
RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3
This contains quite a few patches that I'd like to target for 4.2. They're mostly emulation fixes for the sifive_u board, which now much more closely matches the hardware and can therefor run the same fireware as what gets loaded onto the board. Additional user-visible improvements include:
* support for loading initrd files from the command line into Linux, via /chosen/linux,initrd-{start,end} device tree nodes. * The conversion of LOG_TRACE to trace events. * The addition of clock DT nodes for our uart and ethernet.
This also includes some preliminary work for the H extension patches, but does not include the H extension patches as I haven't had time to review them yet.
This passes my OE boot test on 32-bit and 64-bit virt machines, as well as a 64-bit upstream Linux boot on the sifive_u machine. It has been fixed to actually pass "make check" this time.
Changes since v2 (never made it to the list):
* Sets the sifive_u machine default core count to 2 instead of 5.
Changes since v1 <20190910190513.21160-1-palmer@sifive.com>:
* Sets the sifive_u machine default core count to 5 instead of 1, as it's impossible to have a single core sifive_u machine.
# gpg: Signature made Tue 17 Sep 2019 16:43:30 BST # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
* remotes/palmer/tags/riscv-for-master-4.2-sf1-v3: (48 commits) gdbstub: riscv: fix the fflags registers target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point target/riscv: Fix mstatus dirty mask target/riscv: Use both register name and ABI name riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive: Implement a model for SiFive FU540 OTP riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Set the minimum number of cpus to 2 riscv: hart: Add a "hartid-base" property to RISC-V hart array ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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6591efb5 |
| 23-Jul-2019 |
Philippe Mathieu-Daudé <philmd@redhat.com> |
target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
Use the always-compiled trace events, remove the now unused RISCV_DEBUG_PMP definition.
Note pmpaddr_csr_read() could previously d
target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
Use the always-compiled trace events, remove the now unused RISCV_DEBUG_PMP definition.
Note pmpaddr_csr_read() could previously do out-of-bound accesses passing addr_index >= MAX_RISCV_PMPS.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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Revision tags: v4.0.0, v4.0.0-rc1, v4.0.0-rc0 |
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b98a6620 |
| 19-Mar-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc0-2' into staging
RISC-V Patches for 4.0-rc0, Part 2
This patch set contains three major sources of bug fixes:
* Jim has ad
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc0-2' into staging
RISC-V Patches for 4.0-rc0, Part 2
This patch set contains three major sources of bug fixes:
* Jim has added support for GDB XML files, as well as fixing access to CSRs via the GDB stub. * Alistair has rebased a large set of fixes from Michael that were still in his patch queue. These fix bugs all over our tree, including: * Logging of PMP errors. * User ABI cleanups and fixes, most notably on RVE guests. * Fixes for interrupt emulation fidelity. * Improvements to the emulation fidelity of the sifive_u machine. * Bin Meng has improved the emulation fidelity of the SiFive UART, which now supports both TX and RX interrupts (as well as setting the correct interrupt line).
# gpg: Signature made Tue 19 Mar 2019 12:42:11 GMT # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
* remotes/palmer/tags/riscv-for-master-4.0-rc0-2: riscv: sifive_u: Correct UART0's IRQ in the device tree riscv: sifive_uart: Generate TX interrupt target/riscv: Remove unused struct riscv: sifive_u: Allow up to 4 CPUs to be created RISC-V: Update load reservation comment in do_interrupt RISC-V: Convert trap debugging to trace events RISC-V: Add support for vectored interrupts RISC-V: Change local interrupts from edge to level RISC-V: linux-user support for RVE ABI elf: Add RISC-V PSABI ELF header defines RISC-V: Remove unnecessary disassembler constraints RISC-V: Allow interrupt controllers to claim interrupts RISC-V: Replace __builtin_popcount with ctpop8 in PLIC riscv: pmp: Log pmp access errors as guest errors RISC-V: Add hooks to use the gdb xml files. RISC-V: Add debug support for accessing CSRs. RISC-V: Fixes to CSR_* register macros. RISC-V: Add 64-bit gdb xml files. RISC-V: Add 32-bit gdb xml files.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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929f0a7f |
| 15-Mar-2019 |
Michael Clark <mjc@sifive.com> |
RISC-V: Convert trap debugging to trace events
Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Ali
RISC-V: Convert trap debugging to trace events
Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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