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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,mmcc.yaml113 - description: MMSS GPLL0 voted clock
114 - description: GPLL0 voted clock
141 - description: MMSS GPLL0 voted clock
142 - description: GPLL0 voted clock
180 - description: MMSS GPLL0 voted clock
181 - description: GPLL0 clock
182 - description: GPLL0 voted clock
197 - const: gpll0
244 - const: gpll0
274 - const: gpll0
[all …]
H A Dqcom,msm8998-gpucc.yaml25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
30 - const: gpll0
66 clock-names = "xo", "gpll0";
H A Dqcom,sm6115-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 main div source
H A Dqcom,sm8450-gpucc.yaml30 - description: GPLL0 main branch source
31 - description: GPLL0 div branch source
H A Dqcom,gpucc-sdm660.yaml27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
H A Dqcom,sm6375-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 div branch source
H A Dqcom,qcm2290-dispcc.yaml26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
H A Dqcom,sdm845-dispcc.yaml28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
H A Dqcom,gpucc.yaml44 - description: GPLL0 main branch source
45 - description: GPLL0 div branch source
/openbmc/u-boot/arch/arm/mach-snapdragon/
H A Dclock-snapdragon.c33 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) in clk_enable_gpll0() argument
35 if (readl(base + gpll0->status) & gpll0->status_bit) in clk_enable_gpll0()
38 setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); in clk_enable_gpll0()
40 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) in clk_enable_gpll0()
H A Dclock-apq8016.c18 /* GPLL0 clock control registers */
60 /* 800Mhz/div, gpll0 */ in clk_init_sdc()
83 /* 7372800 uart block clock @ GPLL0 */ in clk_init_uart()
87 /* Vote for gpll0 clock */ in clk_init_uart()
H A Dclock-apq8096.c18 /* GPLL0 clock control registers */
69 /* 7372800 uart block clock @ GPLL0 */ in clk_init_uart()
73 /* Vote for gpll0 clock */ in clk_init_uart()
H A Dclock-snapdragon.h38 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,osm-l3.yaml66 #define GPLL0 165
73 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-sc7180.c35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
68 &gpll0.clkr.hw,
81 &gpll0.clkr.hw,
168 { .hw = &gpll0.clkr.hw },
174 { .hw = &gpll0.clkr.hw },
187 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
215 { .hw = &gpll0.clkr.hw },
227 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-qcm2290.c57 static struct clk_alpha_pll gpll0 = { variable
64 .name = "gpll0",
88 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
416 { .hw = &gpll0.clkr.hw },
429 { .hw = &gpll0.clkr.hw },
443 { .hw = &gpll0.clkr.hw },
459 { .hw = &gpll0.clkr.hw },
477 { .hw = &gpll0.clkr.hw },
494 { .hw = &gpll0.clkr.hw },
512 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm7150.c41 static struct clk_alpha_pll gpll0 = { variable
48 .name = "gpll0",
76 &gpll0.clkr.hw,
89 &gpll0.clkr.hw,
138 { .hw = &gpll0.clkr.hw },
143 { .hw = &gpll0.clkr.hw },
156 { .hw = &gpll0.clkr.hw },
168 { .hw = &gpll0.clkr.hw },
173 { .hw = &gpll0.clkr.hw },
203 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6115.c57 static struct clk_alpha_pll gpll0 = { variable
66 .name = "gpll0",
90 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
110 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
475 { .hw = &gpll0.clkr.hw },
488 { .hw = &gpll0.clkr.hw },
502 { .hw = &gpll0.clkr.hw },
517 { .hw = &gpll0.clkr.hw },
532 { .hw = &gpll0.clkr.hw },
548 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6375.c61 static struct clk_alpha_pll gpll0 = { variable
68 .name = "gpll0",
93 &gpll0.clkr.hw,
115 &gpll0.clkr.hw,
447 { .hw = &gpll0.clkr.hw },
460 { .hw = &gpll0.clkr.hw },
474 { .hw = &gpll0.clkr.hw },
481 { .hw = &gpll0.clkr.hw },
497 { .hw = &gpll0.clkr.hw },
515 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-mdm9607.c54 static struct clk_alpha_pll_postdiv gpll0 = { variable
59 .name = "gpll0",
73 { .hw = &gpll0.clkr.hw },
114 { .hw = &gpll0.clkr.hw },
157 { .hw = &gpll0.clkr.hw },
170 { .hw = &gpll0.clkr.hw },
232 { .hw = &gpll0.clkr.hw },
1477 [GPLL0] = &gpll0.clkr,
1604 /* Vote for GPLL0 to turn on. Needed by acpuclock. */ in gcc_mdm9607_probe()
H A Dgcc-sdx55.c36 static struct clk_alpha_pll gpll0 = { variable
45 .name = "gpll0",
73 &gpll0.clkr.hw,
143 { .hw = &gpll0.clkr.hw },
149 { .hw = &gpll0.clkr.hw },
163 { .hw = &gpll0.clkr.hw },
178 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
1556 [GPLL0] = &gpll0.clkr,
H A Dgcc-sm6350.c34 static struct clk_alpha_pll gpll0 = { variable
41 .name = "gpll0",
66 &gpll0.clkr.hw,
88 &gpll0.clkr.hw,
160 { .hw = &gpll0.clkr.hw },
193 { .hw = &gpll0.clkr.hw },
252 &gpll0.clkr.hw,
266 &gpll0.clkr.hw,
1157 &gpll0.clkr.hw,
1271 &gpll0.clkr.hw,
[all …]
H A Dmmcc-msm8996.c53 { .fw_name = "gpll0", .name = "gpll0" },
355 { .fw_name = "gpll0", .name = "gpll0" },
381 { .fw_name = "gpll0", .name = "gpll0" },
397 { .fw_name = "gpll0", .name = "gpll0" },
413 { .fw_name = "gpll0", .name = "gpll0" },
429 { .fw_name = "gpll0", .name = "gpll0" },
445 { .fw_name = "gpll0", .name = "gpll0" },
464 { .fw_name = "gpll0", .name = "gpll0" },
483 { .fw_name = "gpll0", .name = "gpll0" },
503 { .fw_name = "gpll0", .name = "gpll0" },
H A Dgcc-ipq9574.c94 static struct clk_alpha_pll_postdiv gpll0 = { variable
99 .name = "gpll0",
183 { .hw = &gpll0.clkr.hw },
195 { .hw = &gpll0.clkr.hw },
205 { .hw = &gpll0.clkr.hw },
217 { .hw = &gpll0.clkr.hw },
219 { .hw = &gpll0.clkr.hw },
231 { .hw = &gpll0.clkr.hw },
245 { .hw = &gpll0.clkr.hw },
257 { .hw = &gpll0.clkr.hw },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,msm8996-mss-pil.yaml220 - description: GCC MSS GPLL0 clock
258 - description: GCC MSS GPLL0 clock
295 - description: GCC MSS GPLL0 clock

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