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/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * See the COPYING file in the top-level directory.
12 #include "libqtest-single.h"
84 #define GPIO_ADDR_MASK (~(GPIO_SIZE - 1))
94 static uint32_t gpio_readl(unsigned int gpio, unsigned int offset) in gpio_readl() argument
96 return readl(gpio + offset); in gpio_readl()
99 static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value) in gpio_writel() argument
101 writel(gpio + offset, value); in gpio_writel()
104 static void gpio_set_bit(unsigned int gpio, unsigned int reg, in gpio_set_bit() argument
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * OF helpers for the GPIO API
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
22 #include <linux/gpio/consumer.h>
23 #include <linux/gpio/machine.h>
26 #include "gpiolib-of.h"
29 * This is Linux-specific flags. By default controllers' and Linux' mapping
30 * match, but GPIO controllers are free to translate their own flags to
31 * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
44 * of_gpio_named_count() - Count GPIOs for a device
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/openbmc/docs/designs/
H A Ddevice-tree-gpio-naming.md1 # Device Tree GPIO Naming in OpenBMC
11 The Linux kernel has deprecated the use of sysfs to interact with the GPIO
12 subsystem. The replacement is a "descriptor-based" character device interface.
15 provides an abstraction to this new character device gpio interface.
19 for these GPIO names and if you want userspace code to be able to be consistent
24 The kernel [documentation][2] has a good summary of the GPIO subsystem. The
25 specific field used to name the GPIOs in the DTS is `gpio-line-names`. This
29 scheme in the face of a universe of potential use-cases.
37 - Ensure common function GPIOs within OpenBMC use the same naming convention
42 naming convention and then the sub bullets list the common GPIO names to be used
[all …]
H A Dmultihost-phosphor-buttons.md1 # Multi-host front panel phosphor buttons interface
12 Phosphor buttons module has currently option to monitor gpio events of power and
13 reset buttons and trigger power event handlers.
15 phosphor-buttons currently only support push type buttons.support for different
20 Currently handler events are only based on monitoring gpio events as input
21 (power and reset).There may be cases where we need to create button interface
22 which monitors non gpio events and triggers button actions for example events
29 available in the front panel apart from existing power and reset button
34 The front panel of bmc has buttons like power button, reset button in general
38 +----------------------------------------------+
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/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
13 Drive a GPIO line that can be used to restart the system from a restart handler.
15 This binding supports level and edge triggered reset. At driver load time, the driver will
16 request the given gpio line and install a restart handler. If the optional properties
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra20-ac97.txt4 - compatible : "nvidia,tegra20-ac97"
5 - reg : Should contain AC97 controller registers location and length
6 - interrupts : Should contain AC97 interrupt
7 - resets : Must contain an entry for each entry in reset-names.
8 See ../reset/reset.txt for details.
9 - reset-names : Must include the following entries:
10 - ac97
11 - dmas : Must contain an entry for each entry in clock-names.
13 - dma-names : Must include the following entries:
14 - rx
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H A Drt5677.txt7 - compatible : "realtek,rt5677".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
13 - gpio-controller : Indicates this device is a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
20 - realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
21 - realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low.
23 - realtek,in1-differential
24 - realtek,in2-differential
25 - realtek,lout1-differential
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H A Dcs4271.txt7 - compatible: "cirrus,cs4271"
10 Documentation/devicetree/bindings/spi/spi-bus.txt
14 - reg: the i2c address
19 - reset-gpio: a GPIO spec to define which pin is connected to the chip's
20 !RESET pin
21 - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
23 - cirrus,enable-soft-reset:
24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
25 line is de-asserted. That also means that clocks cannot be changed
26 without putting the chip back into hardware reset, which also requires
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Daltera-a10sr.txt4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
19 a10sr_gpio GPIO Controller
[all …]
H A Ddelta,tn48m-cpld.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/delta,tn48m-cpld.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
19 It is also being used as a GPIO expander and reset controller
20 for the switch MAC-s and other peripherals.
24 const: delta,tn48m-cpld
31 "#address-cells":
34 "#size-cells":
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/openbmc/linux/drivers/media/pci/cx23885/
H A Dcx23885-cards.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <media/drv-intf/cx25840.h>
19 #include "netup-eeprom.h"
20 #include "netup-init.h"
21 #include "altera-ci.h"
24 #include "cx23888-ir.h"
29 "NetUP Dual DVB-T/C CI card revision");
35 "\t\t\tHVR-1250 (reported safe)\n"
41 /* ------------------------------------------------------------------ */
64 .name = "Hauppauge WinTV-HVR1800lp",
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
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/openbmc/u-boot/arch/arm/dts/
H A Dhi3798cv200.dtsi4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 * SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/clock/histb-clock.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/ti-syscon.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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/openbmc/linux/arch/mips/boot/dts/ralink/
H A Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
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/openbmc/u-boot/arch/mips/dts/
H A Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
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H A Dbrcm,bcm3380.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm3380-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/bcm3380-reset.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
22 u-boot,dm-pre-reloc;
25 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
28 u-boot,dm-pre-reloc;
32 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
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/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/gpio/
H A Dphosphor-gpio-monitor_%.bbappend3 inherit obmc-phosphor-systemd systemd
5 SRC_URI += "file://assert-gpio-log@.service \
6 file://assert-post-end \
7 file://assert-post-end.service \
8 file://assert-power-good \
9 file://assert-power-good.service \
10 file://assert-reset-button \
11 file://assert-reset-button.service \
12 file://auto-power \
13 file://auto-poweroff \
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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-consumer-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-consumer-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common GPIO lines
10 - Bartosz Golaszewski <brgl@bgdev.pl>
11 - Linus Walleij <linus.walleij@linaro.org>
14 Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs
20 enable-gpios:
23 GPIO connected to the enable control pin.
[all …]
H A Dgpio-xra1403.txt1 GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
3 The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
4 - Individually programmable inputs:
5 - Internal pull-up resistors
6 - Polarity inversion
7 - Individual interrupt enable
8 - Rising edge and/or Falling edge interrupt
9 - Input filter
10 - Individually programmable outputs
11 - Output Level Control
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * cx18 gpio functions
5 * Derived from ivtv-gpio.c
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
14 #include "cx18-gpio.h"
17 /********************* GPIO stuffs *********************/
19 /* GPIO registers */
27 * HVR-1600 GPIO pins, courtesy of Hauppauge:
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-emmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple eMMC hardware reset provider
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 The purpose of this driver is to perform standard eMMC hw reset
19 doesn't have hardware reset logic connected to emmc card and (limited or
25 const: mmc-pwrseq-emmc
27 reset-gpios:
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/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/ieee802154/
H A Dcc2520.txt4 - compatible: should be "ti,cc2520"
5 - spi-max-frequency: maximal bus speed (8000000), should be set to 4000000 depends
7 - reg: the chipselect index
8 - pinctrl-0: pin control group to be used for this controller.
9 - pinctrl-names: must contain a "default" entry.
10 - fifo-gpio: GPIO spec for the FIFO pin
11 - fifop-gpio: GPIO spec for the FIFOP pin
12 - sfd-gpio: GPIO spec for the SFD pin
13 - cca-gpio: GPIO spec for the CCA pin
14 - vreg-gpio: GPIO spec for the VREG pin
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-hrefv60plus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
6 #include "ste-href-ab8500.dtsi"
7 #include "ste-href.dtsi"
10 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
11 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
13 thermal-zones {
14 chassis-thermal {
16 polling-delay = <20000>;
18 polling-delay-passive = <2000>;
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