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/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * See the COPYING file in the top-level directory.
12 #include "libqtest-single.h"
84 #define GPIO_ADDR_MASK (~(GPIO_SIZE - 1))
94 static uint32_t gpio_readl(unsigned int gpio, unsigned int offset) in gpio_readl() argument
96 return readl(gpio + offset); in gpio_readl()
99 static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value) in gpio_writel() argument
101 writel(gpio + offset, value); in gpio_writel()
104 static void gpio_set_bit(unsigned int gpio, unsigned int reg, in gpio_set_bit() argument
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/openbmc/docs/designs/
H A Ddevice-tree-gpio-naming.md1 # Device Tree GPIO Naming in OpenBMC
11 The Linux kernel has deprecated the use of sysfs to interact with the GPIO
12 subsystem. The replacement is a "descriptor-based" character device interface.
15 provides an abstraction to this new character device gpio interface.
19 for these GPIO names and if you want userspace code to be able to be consistent
24 The kernel [documentation][2] has a good summary of the GPIO subsystem. The
25 specific field used to name the GPIOs in the DTS is `gpio-line-names`. This
29 scheme in the face of a universe of potential use-cases.
37 - Ensure common function GPIOs within OpenBMC use the same naming convention
42 naming convention and then the sub bullets list the common GPIO names to be used
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H A Dmultihost-phosphor-buttons.md1 # Multi-host front panel phosphor buttons interface
12 Phosphor buttons module has currently option to monitor gpio events of power and
13 reset buttons and trigger power event handlers.
15 phosphor-buttons currently only support push type buttons.support for different
20 Currently handler events are only based on monitoring gpio events as input
21 (power and reset).There may be cases where we need to create button interface
22 which monitors non gpio events and triggers button actions for example events
29 available in the front panel apart from existing power and reset button
34 The front panel of bmc has buttons like power button, reset button in general
38 +----------------------------------------------+
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/openbmc/u-boot/arch/mips/dts/
H A Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
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H A Dbrcm,bcm3380.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm3380-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/bcm3380-reset.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
22 u-boot,dm-pre-reloc;
25 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
28 u-boot,dm-pre-reloc;
32 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
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/openbmc/openbmc/meta-facebook/meta-fbdarwin/recipes-phosphor/state/phosphor-state-manager/
H A Dhost-powercycle3 set -x
5 # There are two GPIO pins on the PSU (BMC) slot:
6 # BMC_SYS_PWR_CYC0 (connects to CPLD and control the whole system power cycling) -> Maps to GPIOO0
7 # BMC_SYS_PWR_CYC1 (to power cycle CPU through CPLD) -> Maps to GPIOO2
8 # Mapping sourced from: meta-facebook/meta-fbdarwin/recipes-utils/openbmc-utils/files/setup-gpio.sh
13 # Sourced from the fbdarwin image with: gpiocli --chip aspeed-gpio --pin-name GPIOO2 map-name-to-of…
20 # Drive the pin HIGH, triggering the x86 reset
22 echo "GPIO Reset pin - drive-high failed"
25 echo "Reset initialized."
27 # The GPIO must be driven low before a subsequent reset can be issued
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/openbmc/u-boot/doc/device-tree-bindings/exynos/
H A Demmc-reset.txt1 * Samsung eMMC reset
7 - compatible: should be "samsung,emmc-reset"
8 - reset-gpio: gpio chip for eMMC reset.
12 emmc-reset {
13 compatible = "samsung,emmc-reset";
14 reset-gpio = <&gpk1 2 0>;
/openbmc/openbmc/meta-google/recipes-google/host-power-ctrl/
H A Dgpio-host-pwr_git.bb1 SUMMARY = "GPIO based powercontrol for a host system"
2 DESCRIPTION = "GPIO based powercontrol for a host system."
4 LICENSE = "Apache-2.0"
5 LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/Apache-2.0;md5=89aea4e17d99a7cacd…
11 gpio-ctrl \
15 file://host-ensure-off.service \
16 file://host-powercycle-watchdog.service \
17 file://host-powercycle.service \
18 file://host-poweroff-watchdog.service \
19 file://host-poweroff.service \
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/openbmc/u-boot/arch/arm/dts/
H A Dhi3798cv200.dtsi4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 * SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/clock/histb-clock.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/ti-syscon.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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H A Darmada-385-atl-x530DP.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "armada-385-atl-x530.dtsi"
5 #include "armada-385-atl-x530-u-boot.dtsi"
6 #include "armada-385-atl-x530DP.dtsi"
12 nand-protect {
13 compatible = "atl,nand-protect";
14 protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
17 usb-enable {
18 compatible = "atl,usb-enable";
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H A Darmada-385-atl-x530.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "armada-385-atl-x530.dtsi"
5 #include "armada-385-atl-x530-u-boot.dtsi"
11 nand-protect {
12 compatible = "atl,nand-protect";
13 protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
16 usb-enable {
17 compatible = "atl,usb-enable";
18 enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
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H A Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
19 compatible = "amlogic,meson-gxl-dwc3";
20 #address-cells = <2>;
21 #size-cells = <2>;
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H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
15 model = "Hardkernel ODROID-C2";
23 stdout-path = "serial0:115200n8";
31 usb_otg_pwr: regulator-usb-pwrs {
32 compatible = "regulator-fixed";
34 regulator-name = "USB_OTG_PWR";
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H A Darmada-385-atl-x530.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/gpio.h>
4 #include "armada-385.dtsi"
11 stdout-path = "serial0:115200n8";
30 pcie-mem-aperture = <0xa0000000 0x40000000>;
33 eco-button-interrupt {
34 compatible = "atl,eco-button-interrupt";
35 eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
38 board-reset {
40 /* Physical board layout of reset pin is active-low but for the
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/openbmc/openbmc/meta-hpe/meta-common/recipes-hpe/vehci/
H A Dhost-ehci-owner-reset.bb1 SUMMARY = "GXP EHCI Owner Reset"
3 LICENSE = "Apache-2.0"
4 LIC_FILES_CHKSUM = "file://${HPEBASE}/COPYING.apache-2.0;md5=34400b68072d710fecd0a2940a0d1658"
6 inherit obmc-phosphor-systemd
8 DEPENDS += "phosphor-gpio-monitor"
9 RDEPENDS:${PN} += "phosphor-gpio-monitor-monitor"
11 SYSTEMD_ENVIRONMENT_FILE:${PN} += "obmc/gpio/port_owner_udc0"
12 SYSTEMD_ENVIRONMENT_FILE:${PN} += "obmc/gpio/port_owner_udc1"
13 SYSTEMD_ENVIRONMENT_FILE:${PN} += "obmc/gpio/port_owner_udc2"
18 TMPL_GPIO = "phosphor-gpio-monitor@.service"
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/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dpm8916_gpio.txt1 Driver for part of pm8916 PMIC - gpio and power/reset keys
5 1) GPIO driver
8 - compatible: "qcom,pm8916-gpio"
9 - reg: peripheral ID, size of register block
10 - gpio-controller
11 - gpio-count: number of GPIOs
12 - #gpio-cells: 2
15 - gpio-bank-name: name of bank (as default "pm8916" is used)
20 compatible = "qcom,pm8916-gpio";
22 gpio-controller;
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/openbmc/openbmc/meta-facebook/meta-santabarbara/recipes-phosphor/gpio/
H A Dphosphor-gpio-monitor_%.bbappend3 inherit obmc-phosphor-systemd systemd
5 SERVICE_LIST = "assert-post-end.service \
6 assert-power-good-drop.service \
7 assert-reset-button.service \
8 assert-rmc-main-power-enable.service \
9 deassert-post-end.service \
10 deassert-power-good-drop.service \
11 deassert-reset-button.service \
12 deassert-rmc-main-power-enable.service \
13 platform-host-ready.target \
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/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/gpio/
H A Dphosphor-gpio-monitor_%.bbappend3 inherit obmc-phosphor-systemd systemd
5 SRC_URI += "file://assert-post-end \
6 file://assert-post-end.service \
7 file://assert-power-good \
8 file://assert-power-good.service \
9 file://assert-reset-button \
10 file://assert-reset-button.service \
11 file://auto-power \
12 file://auto-poweroff \
13 file://auto-poweroff@.service \
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/openbmc/openpower-proc-control/procedures/common/
H A Dcfam_reset.cpp4 #include <phosphor-logging/log.hpp>
17 constexpr auto cfamResetPath = "/sys/class/fsi-master/fsi0/device/cfam_reset";
22 * @brief Reset the CFAM using the appropriate GPIO
27 // First look if system supports kernel sysfs based cfam reset in cfamReset()
28 // If it does then write a 1 and let the kernel handle the reset in cfamReset()
33 log<level::DEBUG>("system does not support kernel cfam reset, default " in cfamReset()
38 // Write a 1 to have kernel toggle the reset in cfamReset()
41 log<level::DEBUG>("cfam reset via sysfs complete"); in cfamReset()
45 // No kernel support so toggle gpio from userspace in cfamReset()
46 const std::string cfamReset = {"cfam-reset"}; in cfamReset()
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/openbmc/openbmc/meta-tyan/meta-common/recipes-x86/chassis/x86-power-control/
H A Dpower-config-host0.json5 "LineName" : "id-button",
6 "Type" : "GPIO",
11 "LineName" : "nmi-button",
12 "Type" : "GPIO",
17 "LineName" : "nmi-control",
18 "Type" : "GPIO",
23 "LineName" : "post-complete",
24 "Type" : "GPIO",
29 "LineName" : "power-button",
30 "Type" : "GPIO",
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/openbmc/openbmc/meta-asrock/meta-x570d4u/recipes-x86/chassis/x86-power-control/
H A Dpower-config-host0.json6 "Type" : "GPIO",
12 "Type" : "GPIO",
18 "Type" : "GPIO",
23 "LineName" : "input-bios-post-cmplt-n",
24 "Type" : "GPIO",
29 "LineName" : "button-power-n",
30 "Type" : "GPIO",
35 "LineName" : "input-power-good",
36 "Type" : "GPIO",
41 "LineName" : "control-power-n",
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/openbmc/openbmc/meta-amd/meta-common/recipes-x86/chassis/x86-power-control/daytonax/
H A Dpower-config-host0.json5 "LineName" : "id-button",
6 "Type" : "GPIO",
12 "Type" : "GPIO",
17 "LineName" : "power-ok",
18 "Type" : "GPIO",
23 "LineName" : "power-button",
24 "Type" : "GPIO",
29 "LineName" : "power-good",
30 "Type" : "GPIO",
35 "LineName" : "power-control",
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/openbmc/u-boot/board/compulab/common/
H A Domap3_smc911x.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <asm/gpio.h>
35 &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M); in cl_omap3_smc911x_setup_net_chip_gmpc()
38 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in cl_omap3_smc911x_setup_net_chip_gmpc()
41 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in cl_omap3_smc911x_setup_net_chip_gmpc()
44 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in cl_omap3_smc911x_setup_net_chip_gmpc()
45 &ctrl_base->gpmc_nadv_ale); in cl_omap3_smc911x_setup_net_chip_gmpc()
49 static int cl_omap3_smc911x_reset_net_chip(int gpio) in cl_omap3_smc911x_reset_net_chip() argument
53 if (!gpio_is_valid(gpio)) in cl_omap3_smc911x_reset_net_chip()
54 return -EINVAL; in cl_omap3_smc911x_reset_net_chip()
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/openbmc/x86-power-control/
H A DREADME.md18 x86-power-control uses default json file (power-config-host0.json) for GPIO
20 power-config-host0.json file.
24 Definitions can be configured by two type: GPIO and DBUS
26 ### GPIO subsection
28 For the platform having direct GPIO access can use the type GPIO and define like
35 "Type": "GPIO"
41 For the platform not having direct GPIO access can use dbus based event monitor
55 x86-power-control will monitor the property change from the given DbusName and
64 ### chassis-system-reset
66 Enable chassis system power reset to allow removing power and restoring back.
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/openbmc/u-boot/board/renesas/sh7752evb/
H A Dsh7752evb.c1 // SPDX-License-Identifier: GPL-2.0+
24 struct gpio_regs *gpio = GPIO_BASE; in init_gpio() local
27 /* GPIO */ in init_gpio()
28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
32 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
33 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
34 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
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