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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Multi Core Timer (MCT)
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
[all …]
H A Darm,twd-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-h3.c22 #include "qemu/error-report.h"
25 #include "hw/qdev-core.h"
27 #include "hw/char/serial-mm.h"
29 #include "hw/usb/hcd-ehci.h"
32 #include "hw/arm/allwinner-h3.h"
33 #include "target/arm/cpu-qom.h"
82 { "d-engine", 0x01000000, 4 * MiB },
83 { "d-inter", 0x01400000, 128 * KiB },
96 { "usb0-otg", 0x01c19000, 4 * KiB },
97 { "usb0-phy", 0x01c1a000, 4 * KiB },
[all …]
H A Dallwinner-r40.c22 #include "qemu/error-report.h"
27 #include "hw/qdev-core.h"
29 #include "hw/char/serial-mm.h"
31 #include "hw/usb/hcd-ehci.h"
34 #include "hw/arm/allwinner-r40.h"
35 #include "hw/misc/allwinner-r40-dramc.h"
36 #include "target/arm/cpu-qom.h"
87 { "d-engine", 0x01000000, 4 * MiB },
88 { "d-inter", 0x01400000, 128 * KiB },
96 { "usb0-otg", 0x01c13000, 4 * KiB },
[all …]
/openbmc/qemu/hw/cpu/
H A Da9mpcore.c2 * Cortex-A9MPCore internal peripheral emulation.
16 #include "hw/qdev-properties.h"
18 #include "target/arm/cpu-qom.h"
26 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in a9mp_priv_set_irq()
33 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); in a9mp_priv_initfn()
34 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); in a9mp_priv_initfn()
36 object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); in a9mp_priv_initfn()
38 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in a9mp_priv_initfn()
40 object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER); in a9mp_priv_initfn()
42 object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); in a9mp_priv_initfn()
[all …]
H A Darm11mpcore.c4 * Copyright (c) 2006-2007 CodeSourcery.
16 #include "hw/qdev-properties.h"
24 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in mpcore_priv_set_irq()
30 SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); in mpcore_priv_map_setup()
31 DeviceState *gicdev = DEVICE(&s->gic); in mpcore_priv_map_setup()
32 SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); in mpcore_priv_map_setup()
33 SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); in mpcore_priv_map_setup()
34 SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); in mpcore_priv_map_setup()
36 memory_region_add_subregion(&s->container, 0, in mpcore_priv_map_setup()
38 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs in mpcore_priv_map_setup()
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt8127.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "mediatek,mt81xx-tz-smp";
24 compatible = "arm,cortex-a7";
[all …]
H A Dmt6580.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
28 compatible = "arm,cortex-a7";
[all …]
H A Dmt6582.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
13 interrupt-parent = <&sysirq>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a7";
26 compatible = "arm,cortex-a7";
[all …]
H A Dmt6589.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "mediatek,mt6589-smp";
24 compatible = "arm,cortex-a7";
[all …]
H A Dmt6592.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
28 compatible = "arm,cortex-a7";
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Dmilbeaut-m10v.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/clocksource/
H A Dmips-gic-timer.c1 // SPDX-License-Identifier: GPL-2.0
4 #define pr_fmt(fmt) "mips-gic-timer: " fmt
17 #include <asm/mips-cps.h>
54 int cpu = cpumask_first(evt->cpumask); in gic_next_event()
66 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; in gic_next_event()
75 cd->event_handler(cd); in gic_compare_interrupt()
83 .name = "timer",
89 cd->name = "MIPS GIC"; in gic_clockevent_cpu_init()
90 cd->features = CLOCK_EVT_FEAT_ONESHOT | in gic_clockevent_cpu_init()
93 cd->rating = 350; in gic_clockevent_cpu_init()
[all …]
/openbmc/qemu/include/hw/intc/
H A Dmips_gic.h15 #include "hw/timer/mips_gictimer.h"
20 * GIC Specific definitions
33 #define MSK(n) ((1ULL << (n)) - 1)
35 /* GIC Address Space */
57 /* Reset Mask - Disables Interrupt */
61 /* Set Mask (WO) - Enables Interrupt */
65 /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
101 /* User-Mode Visible Section Register */
102 /* Read-only alias for GIC Shared CounterLo */
104 /* Read-only alias for GIC Shared CounterHi */
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dmips-gic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
16 /* The base address of the GIC registers */
19 /* Offsets from the GIC base address to various control blocks */
29 /* For read-only shared registers */
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
33 /* For read-write shared registers */
35 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
37 /* For read-only local registers */
39 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
48 timer: timer { label
49 compatible = "arm,armv7-timer";
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-ns.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-aemv8a.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
36 #address-cells = <2>;
37 #size-cells = <0>;
[all …]
H A Dcorstone1000.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a35";
32 next-level-cache = <&L2_0>;
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * code for switching cores into non-secure state and into HYP mode
10 #include <asm/gic.h>
12 #include <asm/proc-armv/ptrace.h>
39 * U-Boot calls this "software interrupt" in start.S
41 * to non-secure state.
94 ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
104 movs pc, lr @ ERET to non-secure
125 add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
131 movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
[all …]

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