hw/cpu/arm11mpcore.c

4  * Copyright (c) 2006-2007 CodeSourcery.
16 #include "hw/qdev-properties.h"
24     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);  in mpcore_priv_set_irq()
30     SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu);  in mpcore_priv_map_setup()
31     DeviceState *gicdev = DEVICE(&s->gic);  in mpcore_priv_map_setup()
32     SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic);  in mpcore_priv_map_setup()
33     SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer);  in mpcore_priv_map_setup()
34     SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer);  in mpcore_priv_map_setup()
36     memory_region_add_subregion(&s->container, 0,  in mpcore_priv_map_setup()
38     /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs  in mpcore_priv_map_setup()
41     for (i = 0; i < (s->num_cpu + 1); i++) {  in mpcore_priv_map_setup()
43         memory_region_add_subregion(&s->container, offset,  in mpcore_priv_map_setup()
46     /* Add the regions for timer and watchdog for "current CPU" and  in mpcore_priv_map_setup()
49     for (i = 0; i < (s->num_cpu + 1); i++) {  in mpcore_priv_map_setup()
52         memory_region_add_subregion(&s->container, offset,  in mpcore_priv_map_setup()
54         memory_region_add_subregion(&s->container, offset + 0x20,  in mpcore_priv_map_setup()
57     memory_region_add_subregion(&s->container, 0x1000,  in mpcore_priv_map_setup()
59     /* Wire up the interrupt from each watchdog and timer.  in mpcore_priv_map_setup()
60      * For each core the timer is PPI 29 and the watchdog PPI 30.  in mpcore_priv_map_setup()
62     for (i = 0; i < s->num_cpu; i++) {  in mpcore_priv_map_setup()
63         int ppibase = (s->num_irq - 32) + i * 32;  in mpcore_priv_map_setup()
75     DeviceState *scudev = DEVICE(&s->scu);  in mpcore_priv_realize()
76     DeviceState *gicdev = DEVICE(&s->gic);  in mpcore_priv_realize()
77     DeviceState *mptimerdev = DEVICE(&s->mptimer);  in mpcore_priv_realize()
78     DeviceState *wdtimerdev = DEVICE(&s->wdtimer);  in mpcore_priv_realize()
80     qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);  in mpcore_priv_realize()
81     if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {  in mpcore_priv_realize()
85     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);  in mpcore_priv_realize()
86     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);  in mpcore_priv_realize()
87     qdev_prop_set_uint32(gicdev, "num-priority-bits",  in mpcore_priv_realize()
91     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {  in mpcore_priv_realize()
95     /* Pass through outbound IRQ lines from the GIC */  in mpcore_priv_realize()
96     sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));  in mpcore_priv_realize()
98     /* Pass through inbound GPIO lines to the GIC */  in mpcore_priv_realize()
99     qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);  in mpcore_priv_realize()
101     qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);  in mpcore_priv_realize()
102     if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) {  in mpcore_priv_realize()
106     qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);  in mpcore_priv_realize()
107     if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdtimer), errp)) {  in mpcore_priv_realize()
119     memory_region_init(&s->container, OBJECT(s),  in mpcore_priv_initfn()
120                        "mpcore-priv-container", 0x2000);  in mpcore_priv_initfn()
121     sysbus_init_mmio(sbd, &s->container);  in mpcore_priv_initfn()
123     object_initialize_child(obj, "scu", &s->scu, TYPE_ARM11_SCU);  in mpcore_priv_initfn()
125     object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);  in mpcore_priv_initfn()
126     /* Request the legacy 11MPCore GIC behaviour: */  in mpcore_priv_initfn()
127     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);  in mpcore_priv_initfn()
129     object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);  in mpcore_priv_initfn()
131     object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER);  in mpcore_priv_initfn()
135     DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
136     /* The ARM11 MPCORE TRM says the on-chip controller may have
144     DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
152     dc->realize = mpcore_priv_realize;  in mpcore_priv_class_init()