Lines Matching +full:gic +full:- +full:timer

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * code for switching cores into non-secure state and into HYP mode
10 #include <asm/gic.h>
12 #include <asm/proc-armv/ptrace.h>
39  * U-Boot calls this "software interrupt" in start.S
41  * to non-secure state.
94 	ands	r4, r4, #CPUID_ARM_GENTIMER_MASK	@ test arch timer bits
104 	movs	pc, lr				@ ERET to non-secure
125 	add	\addr, \addr, #GIC_DIST_OFFSET	@ GIC dist i/f offset
131 	movne	\tmp, #GIC_CPU_OFFSET_A9	@ GIC CPU offset for A9
132 	moveq	\tmp, #GIC_CPU_OFFSET_A15	@ GIC CPU offset for A15/A7
139  * of the non-secure and HYP mode transition. The GIC distributor specific
155  * Switch a core to non-secure state.
157  *  1. initialize the GIC per-core interface
158  *  2. allow coprocessor access in non-secure modes
162  * r0-r3 and r12.
164  * PERIPHBASE is used to get the GIC address. This could be 40 bits long,
184 	mcr	p15, 0, r0, c1, c1, 2		@ NSACR = all copros to non-sec
186 /* The CNTFRQ register of the generic timer needs to be
190  * But first check if we have the generic timer.
194 	and	r0, r0, #CPUID_ARM_GENTIMER_MASK	@ mask arch timer bits