/openbmc/qemu/hw/misc/ |
H A D | mips_cmgcr.c | 32 static inline void update_gcr_base(MIPSGCRState *gcr, uint64_t val) in update_gcr_base() argument 37 gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK; in update_gcr_base() 38 memory_region_set_address(&gcr->iomem, gcr->gcr_base); in update_gcr_base() 42 mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4; in update_gcr_base() 46 static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val) in update_cpc_base() argument 48 if (is_cpc_connected(gcr)) { in update_cpc_base() 49 gcr->cpc_base = val & GCR_CPC_BASE_MSK; in update_cpc_base() 51 memory_region_set_address(gcr->cpc_mr, in update_cpc_base() 52 gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK); in update_cpc_base() 53 memory_region_set_enabled(gcr->cpc_mr, in update_cpc_base() [all …]
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/openbmc/linux/sound/arm/ |
H A D | pxa2xx-ac97-lib.c | 127 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa25x() 132 …writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything bu… in pxa_ac97_cold_pxa25x() 133 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */ in pxa_ac97_cold_pxa25x() 137 writel(GCR_COLD_RST, ac97_reg_base + GCR); in pxa_ac97_cold_pxa25x() 149 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa27x() 156 …writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything bu… in pxa_ac97_cold_pxa27x() 157 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */ in pxa_ac97_cold_pxa27x() 165 writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR); in pxa_ac97_cold_pxa27x() 175 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa3xx() 181 writel(0, ac97_reg_base + GCR); in pxa_ac97_cold_pxa3xx() [all …]
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-gnome/gcr/ |
H A D | gcr3_3.41.2.bb | 2 DESCRIPTION = "GCR is a library for displaying certificates, and crypto UI, \ 5 HOMEPAGE = "https://gitlab.gnome.org/GNOME/gcr" 6 BUGTRACKER = "https://gitlab.gnome.org/GNOME/gcr/issues" 24 SRC_URI = "https://download.gnome.org/sources/gcr/3.41/gcr-${PV}.tar.xz;name=archive" 28 S = "${WORKDIR}/gcr-${PV}" 42 ${datadir}/gcr-3 \ 44 ${systemd_user_unitdir}/gcr-ssh-agent.socket \ 45 ${systemd_user_unitdir}/gcr-ssh-agent.service \
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/openbmc/linux/Documentation/devicetree/bindings/soc/nuvoton/ |
H A D | nuvoton,npcm-gcr.yaml | 4 $id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml# 14 The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs 22 - nuvoton,wpcm450-gcr 23 - nuvoton,npcm750-gcr 24 - nuvoton,npcm845-gcr 40 gcr: syscon@800000 { 41 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
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/openbmc/linux/drivers/soc/nuvoton/ |
H A D | wpcm450-soc.c | 52 struct regmap *gcr; in wpcm450_soc_init() local 59 gcr = syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr"); in wpcm450_soc_init() 60 if (IS_ERR(gcr)) in wpcm450_soc_init() 61 return PTR_ERR(gcr); in wpcm450_soc_init() 62 ret = regmap_read(gcr, GCR_PDID, &pdid); in wpcm450_soc_init() 67 pr_warn("Unknown chip ID in GCR.PDID: 0x%06x\n", PDID_CHIP(pdid)); in wpcm450_soc_init() 73 pr_warn("Unknown chip revision in GCR.PDID: 0x%02x\n", PDID_REV(pdid)); in wpcm450_soc_init()
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/openbmc/linux/arch/s390/kvm/ |
H A D | guestdbg.c | 62 u64 *cr9 = &vcpu->arch.sie_block->gcr[9]; in enable_all_hw_bp() 63 u64 *cr10 = &vcpu->arch.sie_block->gcr[10]; in enable_all_hw_bp() 64 u64 *cr11 = &vcpu->arch.sie_block->gcr[11]; in enable_all_hw_bp() 102 u64 *cr9 = &vcpu->arch.sie_block->gcr[9]; in enable_all_hw_wp() 103 u64 *cr10 = &vcpu->arch.sie_block->gcr[10]; in enable_all_hw_wp() 104 u64 *cr11 = &vcpu->arch.sie_block->gcr[11]; in enable_all_hw_wp() 132 vcpu->arch.guestdbg.cr0 = vcpu->arch.sie_block->gcr[0]; in kvm_s390_backup_guest_per_regs() 133 vcpu->arch.guestdbg.cr9 = vcpu->arch.sie_block->gcr[9]; in kvm_s390_backup_guest_per_regs() 134 vcpu->arch.guestdbg.cr10 = vcpu->arch.sie_block->gcr[10]; in kvm_s390_backup_guest_per_regs() 135 vcpu->arch.guestdbg.cr11 = vcpu->arch.sie_block->gcr[11]; in kvm_s390_backup_guest_per_regs() [all …]
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/openbmc/qemu/hw/mips/ |
H A D | cps.c | 150 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); in mips_cps_realize() 151 object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, in mips_cps_realize() 153 object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, in mips_cps_realize() 155 object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base, in mips_cps_realize() 157 object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr), in mips_cps_realize() 159 object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), in mips_cps_realize() 161 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { in mips_cps_realize() 166 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); in mips_cps_realize()
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/openbmc/openbmc/poky/meta/recipes-gnome/gcr/ |
H A D | gcr_4.3.0.bb | 2 DESCRIPTION = "GCR is a library for displaying certificates, and crypto UI, \ 5 HOMEPAGE = "https://gitlab.gnome.org/GNOME/gcr" 6 BUGTRACKER = "https://gitlab.gnome.org/GNOME/gcr/issues" 37 ${datadir}/gcr-4 \ 38 ${systemd_user_unitdir}/gcr-ssh-agent.socket \ 39 ${systemd_user_unitdir}/gcr-ssh-agent.service \
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/openbmc/openbmc/meta-openembedded/meta-gnome/recipes-connectivity/libnma/ |
H A D | libnma_1.10.6.bb | 9 REQUIRED_DISTRO_FEATURES = "${@bb.utils.contains('PACKAGECONFIG','gcr','x11','',d)} opengl" 14 PACKAGECONFIG ?= "gcr iso_codes mobile_broadband_provider_info" 15 PACKAGECONFIG[gcr] = "-Dgcr=true,-Dgcr=false,gcr"
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/openbmc/linux/include/linux/mfd/ |
H A D | intel_pmc_bxt.h | 5 /* GCR reg offsets from GCR base */ 17 * @gcr_mem_base: Virtual base address of GCR (Global Configuration Registers) 18 * @gcr_lock: Lock used to serialize access to GCR registers
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/surf/surf/ |
H A D | 0001-config.ml-make-compatible-with-webkitgtk-2.34.0.patch | 32 -GTKINC = `pkg-config --cflags gtk+-3.0 gcr-3 webkit2gtk-4.0` 33 -GTKLIB = `pkg-config --libs gtk+-3.0 gcr-3 webkit2gtk-4.0` 36 +GTKINC = $(shell $(PKG_CONFIG) --cflags gtk+-3.0 gcr-3 webkit2gtk-4.1) 37 +GTKLIB = $(shell $(PKG_CONFIG) --libs gtk+-3.0 gcr-3 webkit2gtk-4.1)
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/openbmc/linux/arch/arm64/boot/dts/nuvoton/ |
H A D | nuvoton-common-npcm8xx.dtsi | 20 gcr: system-controller@f0800000 { label 21 compatible = "nuvoton,npcm845-gcr", "syscon"; 54 nuvoton,sysgcr = <&gcr>; 157 syscon = <&gcr>; 166 syscon = <&gcr>; 175 syscon = <&gcr>;
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/openbmc/linux/drivers/mfd/ |
H A D | intel_pmc_bxt.c | 74 * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register 76 * @offset: offset of GCR register from GCR address base 79 * Reads the 64-bit PMC GCR register at given offset. 97 * intel_pmc_gcr_update() - Update PMC GCR register bits 99 * @offset: offset of GCR register from GCR address base 103 * Updates the bits of given GCR register as specified by 326 /* GCR registers */ in intel_pmc_get_resources()
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-gnome/gcr/gcr3/ |
H A D | 0001-meson.build-correctly-handle-disabled-ssh_agent-opti.patch | 7 | gcr/meson.build:61:0: ERROR: Unable to get the path of a not-found external program 8 | gcr/meson.build:101:5: ERROR: Unknown variable "ssh_add_path". 12 Upstream-Status: Backport [ https://gitlab.gnome.org/GNOME/gcr/-/commit/9b67bb18d8409e0e693cc600050…
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/openbmc/linux/arch/mips/include/asm/ |
H A D | mips-cm.h | 18 /* The base address of the CM GCR block */ 115 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name) \ 116 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name) 119 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name) \ 120 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name) 123 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \ 124 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name) 127 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \ 128 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name) 300 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | interrupts.c | 35 out_be32(&pic->gcr, MPC85xx_PICGCR_RST); in interrupt_init_cpu() 36 while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) in interrupt_init_cpu() 38 out_be32(&pic->gcr, MPC85xx_PICGCR_M); in interrupt_init_cpu() 39 in_be32(&pic->gcr); in interrupt_init_cpu()
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/openbmc/linux/arch/arm/mach-npcm/ |
H A D | platsmp.c | 28 gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr"); in npcm7xx_smp_boot_secondary() 30 pr_err("no gcr device node\n"); in npcm7xx_smp_boot_secondary() 36 pr_err("could not iomap gcr"); in npcm7xx_smp_boot_secondary()
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/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/ |
H A D | interrupts.c | 39 pic->gcr = MPC86xx_PICGCR_RST; in interrupt_init_cpu() 40 while (pic->gcr & MPC86xx_PICGCR_RST) in interrupt_init_cpu() 42 pic->gcr = MPC86xx_PICGCR_MODE; in interrupt_init_cpu()
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/openbmc/u-boot/arch/mips/cpu/ |
H A D | cm_init.S | 26 /* Find the current physical GCR base address */ 40 /* Re-check the GCR base */
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/openbmc/linux/Documentation/devicetree/bindings/reset/ |
H A D | nuvoton,npcm750-reset.yaml | 33 description: a phandle to access GCR registers. 69 nuvoton,sysgcr = <&gcr>;
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/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | nuvoton,npcm-vcd.yaml | 33 description: phandle to access GCR (Global Control Register) registers. 69 nuvoton,sysgcr = <&gcr>;
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/openbmc/linux/sound/soc/stm/ |
H A D | stm32_sai.c | 72 /* Enable peripheral clock to allow GCR register access */ in stm32_sai_sync_conf_client() 89 /* Enable peripheral clock to allow GCR register access */ in stm32_sai_sync_conf_provider() 252 sai->gcr = readl_relaxed(sai->base); in stm32_sai_suspend() 267 writel_relaxed(sai->gcr, sai->base); in stm32_sai_resume()
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/openbmc/linux/drivers/gpio/ |
H A D | gpio-xra1403.c | 124 unsigned int gcr; in xra1403_dbg_show() local 137 gcr = value[XRA_GCR + 1] << 8 | value[XRA_GCR]; in xra1403_dbg_show() 142 (gcr & BIT(i)) ? "in" : "out", in xra1403_dbg_show()
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/openbmc/u-boot/board/esd/vme8349/ |
H A D | pci.c | 112 out_be32(&immr->pci_ctrl[0].gcr, 0); in pci_init_board() 114 out_be32(&immr->pci_ctrl[0].gcr, 1); in pci_init_board()
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/openbmc/qemu/tests/tcg/aarch64/system/ |
H A D | mte.S | 77 * Set GCR for random tag generation. 0xA5 is just a random value to set 78 * GCR != 0 so the tag generated by 'irg' insn. is not zero, which is
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