32 static inline void update_gcr_base(MIPSGCRState *gcr, uint64_t val)  in update_gcr_base()  argument
37     gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK;  in update_gcr_base()
38     memory_region_set_address(&gcr->iomem, gcr->gcr_base);  in update_gcr_base()
42         mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4;  in update_gcr_base()
46 static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val)  in update_cpc_base()  argument
48     if (is_cpc_connected(gcr)) {  in update_cpc_base()
49         gcr->cpc_base = val & GCR_CPC_BASE_MSK;  in update_cpc_base()
51         memory_region_set_address(gcr->cpc_mr,  in update_cpc_base()
52                                   gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK);  in update_cpc_base()
53         memory_region_set_enabled(gcr->cpc_mr,  in update_cpc_base()
54                                   gcr->cpc_base & GCR_CPC_BASE_CPCEN_MSK);  in update_cpc_base()
59 static inline void update_gic_base(MIPSGCRState *gcr, uint64_t val)  in update_gic_base()  argument
61     if (is_gic_connected(gcr)) {  in update_gic_base()
62         gcr->gic_base = val & GCR_GIC_BASE_MSK;  in update_gic_base()
64         memory_region_set_address(gcr->gic_mr,  in update_gic_base()
65                                   gcr->gic_base & GCR_GIC_BASE_GICBASE_MSK);  in update_gic_base()
66         memory_region_set_enabled(gcr->gic_mr,  in update_gic_base()
67                                   gcr->gic_base & GCR_GIC_BASE_GICEN_MSK);  in update_gic_base()
72 /* Read GCR registers */
75     MIPSGCRState *gcr = (MIPSGCRState *) opaque;  in gcr_read()  local
76     MIPSGCRVPState *current_vps = &gcr->vps[current_cpu->cpu_index];  in gcr_read()
77     MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other];  in gcr_read()
85         return gcr->gcr_base;  in gcr_read()
87         return gcr->gcr_rev;  in gcr_read()
89         return gcr->gic_base;  in gcr_read()
91         return gcr->cpc_base;  in gcr_read()
93         return is_gic_connected(gcr);  in gcr_read()
95         return is_cpc_connected(gcr);  in gcr_read()
103         return gcr->num_vps - 1;  in gcr_read()
113         qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" HWADDR_PRIx  in gcr_read()
126 /* Write GCR registers */
129     MIPSGCRState *gcr = (MIPSGCRState *)opaque;  in gcr_write()  local
130     MIPSGCRVPState *current_vps = &gcr->vps[current_cpu->cpu_index];  in gcr_write()
131     MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other];  in gcr_write()
135         update_gcr_base(gcr, data);  in gcr_write()
138         update_gic_base(gcr, data);  in gcr_write()
141         update_cpc_base(gcr, data);  in gcr_write()
154         if ((data & GCR_CL_OTHER_MSK) < gcr->num_vps) {  in gcr_write()
159         if ((data & GCR_CL_OTHER_MSK) < gcr->num_vps) {  in gcr_write()
164         qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx  in gcr_write()
185                           "mips-gcr", GCR_ADDRSPACE_SZ);  in mips_gcr_init()
205     .name = "mips-gcr",
216     DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
217     DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR),