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Searched +full:gamma +full:- +full:lut (Results 1 – 25 of 54) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_color.c38 * - Input gamma LUT (de-normalized)
39 * - Input CSC (normalized)
40 * - Surface degamma LUT (normalized)
41 * - Surface CSC (normalized)
42 * - Surface regamma LUT (normalized)
43 * - Output CSC (normalized)
49 * Plane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM
51 * The input gamma LUT block isn't really applicable here since it operates
59 * support any CRTC props with correct blending with multiple planes - but we
64 * respective property is set to NULL. A linear DGM/RGM LUT should also
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/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_gamma.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/soc/mediatek/mtk-cmdq.h>
34 * struct mtk_disp_gamma - DISP_GAMMA driver structure
45 struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); in mtk_gamma_clk_enable() local
47 return clk_prepare_enable(gamma->clk); in mtk_gamma_clk_enable()
52 struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); in mtk_gamma_clk_disable() local
54 clk_disable_unprepare(gamma->clk); in mtk_gamma_clk_disable()
60 struct drm_color_lut *lut; in mtk_gamma_set_common() local
65 if (state->gamma_lut) { in mtk_gamma_set_common()
70 lut = (struct drm_color_lut *)state->gamma_lut->data; in mtk_gamma_set_common()
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/openbmc/linux/drivers/gpu/drm/
H A Ddrm_color_mgmt.c42 * Blob property to set the degamma lookup table (LUT) mapping pixel data
45 * Hardware might choose not to use the full precision of the LUT elements
46 * nor use all the elements of the LUT (for example the hardware might
47 * choose to interpolate between LUT[0] and LUT[4]).
50 * linear/pass-thru gamma table should be used. This is generally the
51 * driver boot-up state too. Drivers can access this blob through
57 * hardware). If drivers support multiple LUT sizes then they should
58 * publish the largest size, and sub-sample smaller sized LUTs (e.g. for
59 * split-gamma modes) appropriately.
63 * pixel data after the lookup through the degamma LUT and before the
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_surface.c40 plane_state->ctx = ctx; in dc_plane_construct()
42 plane_state->gamma_correction = dc_create_gamma(); in dc_plane_construct()
43 if (plane_state->gamma_correction != NULL) in dc_plane_construct()
44 plane_state->gamma_correction->is_identity = true; in dc_plane_construct()
46 plane_state->in_transfer_func = dc_create_transfer_func(); in dc_plane_construct()
47 if (plane_state->in_transfer_func != NULL) { in dc_plane_construct()
48 plane_state->in_transfer_func->type = TF_TYPE_BYPASS; in dc_plane_construct()
50 plane_state->in_shaper_func = dc_create_transfer_func(); in dc_plane_construct()
51 if (plane_state->in_shaper_func != NULL) { in dc_plane_construct()
52 plane_state->in_shaper_func->type = TF_TYPE_BYPASS; in dc_plane_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_ipp.c31 (ipp_dce->regs->reg)
35 ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name
38 ipp_dce->base.ctx
53 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); in dce_ipp_cursor_set_position()
56 CURSOR_X_POSITION, position->x, in dce_ipp_cursor_set_position()
57 CURSOR_Y_POSITION, position->y); in dce_ipp_cursor_set_position()
60 CURSOR_HOT_SPOT_X, position->x_hotspot, in dce_ipp_cursor_set_position()
61 CURSOR_HOT_SPOT_Y, position->y_hotspot); in dce_ipp_cursor_set_position()
78 switch (attributes->color_format) { in dce_ipp_cursor_set_attributes()
98 CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, in dce_ipp_cursor_set_attributes()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_cm.c43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
129 dpp->base.ctx, in program_gamut_remap()
139 dpp->base.ctx, in program_gamut_remap()
149 dpp->base.ctx, in program_gamut_remap()
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/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,rk3566-vop
22 - rockchip,rk3568-vop
26 - description:
29 - description:
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H A Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
23 - rockchip,rk3036-vop
24 - rockchip,rk3066-vop
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/openbmc/linux/drivers/gpu/drm/ci/xfails/
H A Dmediatek-mt8173-fails.txt2 kms_addfb_basic@addfb25-bad-modifier,Fail
3 kms_bw@linear-tiling-1-displays-1920x1080p,Fail
4 kms_bw@linear-tiling-1-displays-2560x1440p,Fail
5 kms_bw@linear-tiling-1-displays-3840x2160p,Fail
6 kms_bw@linear-tiling-2-displays-1920x1080p,Fail
7 kms_bw@linear-tiling-2-displays-2560x1440p,Fail
8 kms_bw@linear-tiling-2-displays-3840x2160p,Fail
9 kms_bw@linear-tiling-3-displays-1920x1080p,Fail
10 kms_bw@linear-tiling-3-displays-2560x1440p,Fail
11 kms_bw@linear-tiling-3-displays-3840x2160p,Fail
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H A Dmediatek-mt8183-fails.txt1 kms_addfb_basic@addfb25-bad-modifier,Fail
2 kms_bw@linear-tiling-1-displays-2560x1440p,Fail
3 kms_bw@linear-tiling-2-displays-1920x1080p,Fail
4 kms_bw@linear-tiling-2-displays-2560x1440p,Fail
5 kms_bw@linear-tiling-2-displays-3840x2160p,Fail
6 kms_bw@linear-tiling-3-displays-2560x1440p,Fail
7 kms_bw@linear-tiling-3-displays-3840x2160p,Fail
8 kms_color@pipe-A-invalid-gamma-lut-sizes,Fail
9 kms_plane_scaling@upscale-with-rotation-20x20,Fail
10 kms_rmfb@close-fd,Fail
H A Dmsm-sc7180-skips.txt4 # Test incorrectly assumes that CTM support implies gamma/degamma
5 # LUT support. None of the subtests handle the case of only having
10 # too gracefully.. https://gitlab.freedesktop.org/drm/msm/-/issues/15
11 kms_bw@linear-tiling-.*-displays-3840x2160p
14 kms_bw@linear-tiling-2.*
15 kms_bw@linear-tiling-3.*
16 kms_bw@linear-tiling-4.*
17 kms_bw@linear-tiling-5.*
18 kms_bw@linear-tiling-6.*
23 kms_plane_multiple@atomic-pipe-A-tiling-none
/openbmc/linux/include/drm/
H A Ddrm_color_mgmt.h34 * drm_color_lut_extract - clamp and round LUT entries
36 * @bit_precision: number of bits the hw LUT supports
38 * Extract a degamma/gamma LUT value provided by user (in the form of
45 u32 max = 0xffff >> (16 - bit_precision); in drm_color_lut_extract()
49 val += 1UL << (16 - bit_precision - 1); in drm_color_lut_extract()
50 val >>= 16 - bit_precision; in drm_color_lut_extract()
67 * drm_color_lut_size - calculate the number of entries in the LUT
68 * @blob: blob containing the LUT
71 * The number of entries in the color LUT stored in @blob.
75 return blob->length / sizeof(struct drm_color_lut); in drm_color_lut_size()
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_color.c34 * Program non-arming double buffered color management registers
90 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
93 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
106 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
107 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
108 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
109 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
122 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
125 #define ILK_CSC_COEFF_LIMITED_RANGE ((235 - 16) << (12 - 8)) /* exponent 0 */
126 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 << (12 - 8))
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H A Dhsw_ips.c1 // SPDX-License-Identifier: MIT
15 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_ips_enable()
16 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in hsw_ips_enable()
19 if (!crtc_state->ips_enabled) in hsw_ips_enable()
27 drm_WARN_ON(&i915->drm, in hsw_ips_enable()
28 !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); in hsw_ips_enable()
32 if (i915->display.ips.false_color) in hsw_ips_enable()
36 drm_WARN_ON(&i915->drm, in hsw_ips_enable()
37 snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, in hsw_ips_enable()
55 drm_err(&i915->drm, in hsw_ips_enable()
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/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_cmm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Color Management Module
27 * @lut: 1D-LUT state
28 * @lut.enabled: 1D-LUT enabled flag
32 } lut; member
37 return ioread32(rcmm->base + reg); in rcar_cmm_read()
42 iowrite32(data, rcmm->base + reg); in rcar_cmm_write()
46 * rcar_cmm_lut_write() - Scale the DRM LUT table entries to hardware precision
49 * @drm_lut: Pointer to the DRM LUT table
66 * rcar_cmm_setup() - Configure the CMM unit
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/openbmc/linux/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
35 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid()
38 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
53 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
55 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
63 clk_prepare_enable(hwdev->pxlclk); in malidp_crtc_atomic_enable()
66 clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000); in malidp_crtc_atomic_enable()
68 hwdev->hw->modeset(hwdev, &vm); in malidp_crtc_atomic_enable()
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/openbmc/linux/drivers/staging/media/ipu3/include/uapi/
H A Dintel-ipu3.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (C) 2017 - 2018 Intel Corporation */
11 /* Vendor specific - used for IPU3 camera sub-system */
17 /* from include/uapi/linux/v4l2-controls.h */
26 #define IPU3_UAPI_GRID_START_MASK ((1 << 12) - 1)
34 * struct ipu3_uapi_grid_config - Grid plane config
56 * create a grid-based output, and the data is then divided into "slices".
71 * struct ipu3_uapi_awb_set_item - Memory layout for each cell in AWB
108 * struct ipu3_uapi_awb_raw_buffer - AWB raw buffer
119 * struct ipu3_uapi_awb_config_s - AWB config
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
99 // for example, 1080p -> 8K is 4.0, or 4000 raw value
107 // for example, 8K -> 1080p is 0.25, or 250 raw value
119 * DOC: color-management-caps
124 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
131 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
134 * @gamma2_2: standard gamma
136 * @hlg: hybrid log–gamma transfer function
147 * struct dpp_color_caps - color pipeline capabilities for display pipe and
151 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
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/openbmc/linux/drivers/gpu/drm/mgag200/
H A Dmgag200_mode.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/iosys-map.h>
38 switch (format->format) { in mgag200_crtc_set_gamma_linear()
62 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", in mgag200_crtc_set_gamma_linear()
63 &format->format); in mgag200_crtc_set_gamma_linear()
70 struct drm_color_lut *lut) in mgag200_crtc_set_gamma() argument
76 switch (format->format) { in mgag200_crtc_set_gamma()
78 /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ in mgag200_crtc_set_gamma()
80 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].red >> 8); in mgag200_crtc_set_gamma()
81 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); in mgag200_crtc_set_gamma()
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/openbmc/linux/drivers/gpu/drm/amd/display/modules/color/
H A Dcolor_gamma.c30 /* When calculating LUT values the first region and at least one subsequent
43 /* Helper to optimize gamma calculation, only use in translate_from_linear, in
48 * X[i] = 2 * X[i-NUM_PTS_IN_REGION] for i>=16
49 * The other fact is that (2x)^gamma = 2^gamma * x^gamma
50 * So we compute and save x^gamma for the first 16 regions, and for every next region
51 * just multiply with 2^gamma which can be computed once, and save the result so we
66 /* one-time setup of X points */
78 for (segment = 6; segment > (6 - NUM_REGIONS); segment--) { in setup_x_points_distribution()
82 seg_offset = (segment + (NUM_REGIONS - 7)) * NUM_PTS_IN_REGION; in setup_x_points_distribution()
89 (coordinates_x[index-1].x, increment); in setup_x_points_distribution()
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/openbmc/linux/drivers/gpu/drm/omapdrm/
H A Domap_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
51 /* -----------------------------------------------------------------------------
58 return &omap_crtc->vm; in omap_crtc_timings()
64 return omap_crtc->channel; in omap_crtc_channel()
73 spin_lock_irqsave(&crtc->dev->event_lock, flags); in omap_crtc_is_pending()
74 pending = omap_crtc->pending; in omap_crtc_is_pending()
75 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in omap_crtc_is_pending()
88 return wait_event_timeout(omap_crtc->pending_wait, in omap_crtc_wait_pending()
93 /* -----------------------------------------------------------------------------
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/openbmc/linux/Documentation/gpu/amdgpu/display/
H A Ddisplay-manager.rst8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
47 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dhead.c43 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), in nv50_head_flush_clr()
46 if (clr.olut) head->func->olut_clr(head); in nv50_head_flush_clr()
47 if (clr.core) head->func->core_clr(head); in nv50_head_flush_clr()
48 if (clr.curs) head->func->curs_clr(head); in nv50_head_flush_clr()
54 if (asyh->set.curs ) head->func->curs_set(head, asyh); in nv50_head_flush_set_wndw()
55 if (asyh->set.olut ) { in nv50_head_flush_set_wndw()
56 asyh->olut.offset = nv50_lut_load(&head->olut, in nv50_head_flush_set_wndw()
57 asyh->olut.buffer, in nv50_head_flush_set_wndw()
58 asyh->state.gamma_lut, in nv50_head_flush_set_wndw()
59 asyh->olut.load); in nv50_head_flush_set_wndw()
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/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author:Mark Yao <mark.yao@rock-chips.com>
45 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
47 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
49 vop_reg_set(vop, &win->phy->scl->ext->name, \
50 win->base, ~0, v, #name)
54 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
55 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
60 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
61 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
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/openbmc/linux/drivers/net/wireless/ti/wl1251/
H A Dboot.c1 // SPDX-License-Identifier: GPL-2.0-only
19 wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask)); in wl1251_boot_target_enable_interrupts()
40 /* 1.2 check pWhalBus->uSelfClearTime if the in wl1251_boot_soft_reset()
43 return -1; in wl1251_boot_soft_reset()
70 static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = { in wl1251_boot_init_seq() local
118 * PG 1.2: set the clock request time to be ref_clk_settling_time - in wl1251_boot_init_seq()
122 tmp = init_data - 0x21; in wl1251_boot_init_seq()
143 tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000; in wl1251_boot_init_seq()
146 /* set fractional divider according to Appendix C-BB PLL in wl1251_boot_init_seq()
149 tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER]; in wl1251_boot_init_seq()
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