1dc794d3dSSakari Ailus /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2dc794d3dSSakari Ailus /* Copyright (C) 2017 - 2018 Intel Corporation */
3dc794d3dSSakari Ailus 
4dc794d3dSSakari Ailus #ifndef __IPU3_UAPI_H
5dc794d3dSSakari Ailus #define __IPU3_UAPI_H
6dc794d3dSSakari Ailus 
7dc794d3dSSakari Ailus #include <linux/types.h>
8dc794d3dSSakari Ailus 
9dc794d3dSSakari Ailus /* from /drivers/staging/media/ipu3/include/videodev2.h */
10dc794d3dSSakari Ailus 
11dc794d3dSSakari Ailus /* Vendor specific - used for IPU3 camera sub-system */
12dc794d3dSSakari Ailus /* IPU3 processing parameters */
13dc794d3dSSakari Ailus #define V4L2_META_FMT_IPU3_PARAMS	v4l2_fourcc('i', 'p', '3', 'p')
14dc794d3dSSakari Ailus /* IPU3 3A statistics */
15dc794d3dSSakari Ailus #define V4L2_META_FMT_IPU3_STAT_3A	v4l2_fourcc('i', 'p', '3', 's')
16dc794d3dSSakari Ailus 
17dc794d3dSSakari Ailus /* from include/uapi/linux/v4l2-controls.h */
18dc794d3dSSakari Ailus #define V4L2_CID_INTEL_IPU3_BASE	(V4L2_CID_USER_BASE + 0x10c0)
19dc794d3dSSakari Ailus #define V4L2_CID_INTEL_IPU3_MODE	(V4L2_CID_INTEL_IPU3_BASE + 1)
20dc794d3dSSakari Ailus 
21dc794d3dSSakari Ailus /******************* ipu3_uapi_stats_3a *******************/
22dc794d3dSSakari Ailus 
23dc794d3dSSakari Ailus #define IPU3_UAPI_MAX_STRIPES				2
24dc794d3dSSakari Ailus #define IPU3_UAPI_MAX_BUBBLE_SIZE			10
25dc794d3dSSakari Ailus 
26dc794d3dSSakari Ailus #define IPU3_UAPI_GRID_START_MASK			((1 << 12) - 1)
27dc794d3dSSakari Ailus #define IPU3_UAPI_GRID_Y_START_EN			(1 << 15)
28dc794d3dSSakari Ailus 
29dc794d3dSSakari Ailus /* controls generation of meta_data (like FF enable/disable) */
30dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_RGBS_THR_B_EN			(1 << 14)
31dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_RGBS_THR_B_INCL_SAT		(1 << 15)
32dc794d3dSSakari Ailus 
33dc794d3dSSakari Ailus /**
34dc794d3dSSakari Ailus  * struct ipu3_uapi_grid_config - Grid plane config
35dc794d3dSSakari Ailus  *
36dc794d3dSSakari Ailus  * @width:	Grid horizontal dimensions, in number of grid blocks(cells).
379b005ce9SBingbu Cao  *		For AWB, the range is (16, 80).
389b005ce9SBingbu Cao  *		For AF/AE, the range is (16, 32).
39dc794d3dSSakari Ailus  * @height:	Grid vertical dimensions, in number of grid cells.
409b005ce9SBingbu Cao  *		For AWB, the range is (16, 60).
419b005ce9SBingbu Cao  *		For AF/AE, the range is (16, 24).
42dc794d3dSSakari Ailus  * @block_width_log2:	Log2 of the width of each cell in pixels.
439b005ce9SBingbu Cao  *			For AWB, the range is [3, 6].
449b005ce9SBingbu Cao  *			For AF/AE, the range is [3, 7].
45dc794d3dSSakari Ailus  * @block_height_log2:	Log2 of the height of each cell in pixels.
469b005ce9SBingbu Cao  *			For AWB, the range is [3, 6].
479b005ce9SBingbu Cao  *			For AF/AE, the range is [3, 7].
48dc794d3dSSakari Ailus  * @height_per_slice:	The number of blocks in vertical axis per slice.
49dc794d3dSSakari Ailus  *			Default 2.
50dc794d3dSSakari Ailus  * @x_start: X value of top left corner of Region of Interest(ROI).
51dc794d3dSSakari Ailus  * @y_start: Y value of top left corner of ROI
52dc794d3dSSakari Ailus  * @x_end: X value of bottom right corner of ROI
53dc794d3dSSakari Ailus  * @y_end: Y value of bottom right corner of ROI
54dc794d3dSSakari Ailus  *
55dc794d3dSSakari Ailus  * Due to the size of total amount of collected data, most statistics
56dc794d3dSSakari Ailus  * create a grid-based output, and the data is then divided into "slices".
57dc794d3dSSakari Ailus  */
58dc794d3dSSakari Ailus struct ipu3_uapi_grid_config {
59dc794d3dSSakari Ailus 	__u8 width;
60dc794d3dSSakari Ailus 	__u8 height;
61dc794d3dSSakari Ailus 	__u16 block_width_log2:3;
62dc794d3dSSakari Ailus 	__u16 block_height_log2:3;
63dc794d3dSSakari Ailus 	__u16 height_per_slice:8;
64dc794d3dSSakari Ailus 	__u16 x_start;
65dc794d3dSSakari Ailus 	__u16 y_start;
66dc794d3dSSakari Ailus 	__u16 x_end;
67dc794d3dSSakari Ailus 	__u16 y_end;
68dc794d3dSSakari Ailus } __packed;
69dc794d3dSSakari Ailus 
706ab70300SJean-Michel Hautbois /**
716ab70300SJean-Michel Hautbois  * struct ipu3_uapi_awb_set_item - Memory layout for each cell in AWB
726ab70300SJean-Michel Hautbois  *
736ab70300SJean-Michel Hautbois  * @Gr_avg:	Green average for red lines in the cell.
746ab70300SJean-Michel Hautbois  * @R_avg:	Red average in the cell.
756ab70300SJean-Michel Hautbois  * @B_avg:	Blue average in the cell.
766ab70300SJean-Michel Hautbois  * @Gb_avg:	Green average for blue lines in the cell.
776ab70300SJean-Michel Hautbois  * @sat_ratio:  Percentage of pixels over the thresholds specified in
786ab70300SJean-Michel Hautbois  *		ipu3_uapi_awb_config_s, coded from 0 to 255.
796ab70300SJean-Michel Hautbois  * @padding0:   Unused byte for padding.
806ab70300SJean-Michel Hautbois  * @padding1:   Unused byte for padding.
816ab70300SJean-Michel Hautbois  * @padding2:   Unused byte for padding.
826ab70300SJean-Michel Hautbois  */
836ab70300SJean-Michel Hautbois struct ipu3_uapi_awb_set_item {
846ab70300SJean-Michel Hautbois 	__u8 Gr_avg;
856ab70300SJean-Michel Hautbois 	__u8 R_avg;
866ab70300SJean-Michel Hautbois 	__u8 B_avg;
876ab70300SJean-Michel Hautbois 	__u8 Gb_avg;
886ab70300SJean-Michel Hautbois 	__u8 sat_ratio;
896ab70300SJean-Michel Hautbois 	__u8 padding0;
906ab70300SJean-Michel Hautbois 	__u8 padding1;
916ab70300SJean-Michel Hautbois 	__u8 padding2;
926ab70300SJean-Michel Hautbois } __attribute__((packed));
936ab70300SJean-Michel Hautbois 
94dc794d3dSSakari Ailus /*
95dc794d3dSSakari Ailus  * The grid based data is divided into "slices" called set, each slice of setX
96dc794d3dSSakari Ailus  * refers to ipu3_uapi_grid_config width * height_per_slice.
97dc794d3dSSakari Ailus  */
98dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_MAX_SETS				60
99dc794d3dSSakari Ailus /* Based on grid size 80 * 60 and cell size 16 x 16 */
1006ab70300SJean-Michel Hautbois #define IPU3_UAPI_AWB_SET_SIZE				160
101dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_SPARE_FOR_BUBBLES \
1026ab70300SJean-Michel Hautbois 	(IPU3_UAPI_MAX_BUBBLE_SIZE * IPU3_UAPI_MAX_STRIPES)
103dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_MAX_BUFFER_SIZE \
104dc794d3dSSakari Ailus 	(IPU3_UAPI_AWB_MAX_SETS * \
105dc794d3dSSakari Ailus 	 (IPU3_UAPI_AWB_SET_SIZE + IPU3_UAPI_AWB_SPARE_FOR_BUBBLES))
106dc794d3dSSakari Ailus 
107dc794d3dSSakari Ailus /**
108dc794d3dSSakari Ailus  * struct ipu3_uapi_awb_raw_buffer - AWB raw buffer
109dc794d3dSSakari Ailus  *
110dc794d3dSSakari Ailus  * @meta_data: buffer to hold auto white balance meta data which is
111dc794d3dSSakari Ailus  *		the average values for each color channel.
112dc794d3dSSakari Ailus  */
113dc794d3dSSakari Ailus struct ipu3_uapi_awb_raw_buffer {
1146ab70300SJean-Michel Hautbois 	struct ipu3_uapi_awb_set_item meta_data[IPU3_UAPI_AWB_MAX_BUFFER_SIZE]
115dc794d3dSSakari Ailus 		__attribute__((aligned(32)));
116dc794d3dSSakari Ailus } __packed;
117dc794d3dSSakari Ailus 
118dc794d3dSSakari Ailus /**
119dc794d3dSSakari Ailus  * struct ipu3_uapi_awb_config_s - AWB config
120dc794d3dSSakari Ailus  *
121dc794d3dSSakari Ailus  * @rgbs_thr_gr: gr threshold value.
122dc794d3dSSakari Ailus  * @rgbs_thr_r: Red threshold value.
123dc794d3dSSakari Ailus  * @rgbs_thr_gb: gb threshold value.
124dc794d3dSSakari Ailus  * @rgbs_thr_b: Blue threshold value.
125dc794d3dSSakari Ailus  * @grid: &ipu3_uapi_grid_config, the default grid resolution is 16x16 cells.
126dc794d3dSSakari Ailus  *
127dc794d3dSSakari Ailus  * The threshold is a saturation measure range [0, 8191], 8191 is default.
128dc794d3dSSakari Ailus  * Values over threshold may be optionally rejected for averaging.
129dc794d3dSSakari Ailus  */
130dc794d3dSSakari Ailus struct ipu3_uapi_awb_config_s {
131dc794d3dSSakari Ailus 	__u16 rgbs_thr_gr;
132dc794d3dSSakari Ailus 	__u16 rgbs_thr_r;
133dc794d3dSSakari Ailus 	__u16 rgbs_thr_gb;
134dc794d3dSSakari Ailus 	__u16 rgbs_thr_b;
135dc794d3dSSakari Ailus 	struct ipu3_uapi_grid_config grid;
136dc794d3dSSakari Ailus } __attribute__((aligned(32))) __packed;
137dc794d3dSSakari Ailus 
138dc794d3dSSakari Ailus /**
139dc794d3dSSakari Ailus  * struct ipu3_uapi_awb_config - AWB config wrapper
140dc794d3dSSakari Ailus  *
141dc794d3dSSakari Ailus  * @config: config for auto white balance as defined by &ipu3_uapi_awb_config_s
142dc794d3dSSakari Ailus  */
143dc794d3dSSakari Ailus struct ipu3_uapi_awb_config {
144dc794d3dSSakari Ailus 	struct ipu3_uapi_awb_config_s config __attribute__((aligned(32)));
145dc794d3dSSakari Ailus } __packed;
146dc794d3dSSakari Ailus 
147dc794d3dSSakari Ailus #define IPU3_UAPI_AE_COLORS				4	/* R, G, B, Y */
148dc794d3dSSakari Ailus #define IPU3_UAPI_AE_BINS				256
149dc794d3dSSakari Ailus #define IPU3_UAPI_AE_WEIGHTS				96
150dc794d3dSSakari Ailus 
151dc794d3dSSakari Ailus /**
152dc794d3dSSakari Ailus  * struct ipu3_uapi_ae_raw_buffer - AE global weighted histogram
153dc794d3dSSakari Ailus  *
154dc794d3dSSakari Ailus  * @vals: Sum of IPU3_UAPI_AE_COLORS in cell
155dc794d3dSSakari Ailus  *
156dc794d3dSSakari Ailus  * Each histogram contains IPU3_UAPI_AE_BINS bins. Each bin has 24 bit unsigned
157dc794d3dSSakari Ailus  * for counting the number of the pixel.
158dc794d3dSSakari Ailus  */
159dc794d3dSSakari Ailus struct ipu3_uapi_ae_raw_buffer {
160dc794d3dSSakari Ailus 	__u32 vals[IPU3_UAPI_AE_BINS * IPU3_UAPI_AE_COLORS];
161dc794d3dSSakari Ailus } __packed;
162dc794d3dSSakari Ailus 
163dc794d3dSSakari Ailus /**
164dc794d3dSSakari Ailus  * struct ipu3_uapi_ae_raw_buffer_aligned - AE raw buffer
165dc794d3dSSakari Ailus  *
166dc794d3dSSakari Ailus  * @buff: &ipu3_uapi_ae_raw_buffer to hold full frame meta data.
167dc794d3dSSakari Ailus  */
168dc794d3dSSakari Ailus struct ipu3_uapi_ae_raw_buffer_aligned {
169dc794d3dSSakari Ailus 	struct ipu3_uapi_ae_raw_buffer buff __attribute__((aligned(32)));
170dc794d3dSSakari Ailus } __packed;
171dc794d3dSSakari Ailus 
172dc794d3dSSakari Ailus /**
173dc794d3dSSakari Ailus  * struct ipu3_uapi_ae_grid_config - AE weight grid
174dc794d3dSSakari Ailus  *
175dc794d3dSSakari Ailus  * @width: Grid horizontal dimensions. Value: [16, 32], default 16.
176dc794d3dSSakari Ailus  * @height: Grid vertical dimensions. Value: [16, 24], default 16.
177dc794d3dSSakari Ailus  * @block_width_log2: Log2 of the width of the grid cell, value: [3, 7].
178dc794d3dSSakari Ailus  * @block_height_log2: Log2 of the height of the grid cell, value: [3, 7].
179dc794d3dSSakari Ailus  *			default is 3 (cell size 8x8), 4 cell per grid.
180dc794d3dSSakari Ailus  * @reserved0: reserved
181dc794d3dSSakari Ailus  * @ae_en: 0: does not write to &ipu3_uapi_ae_raw_buffer_aligned array,
182dc794d3dSSakari Ailus  *		1: write normally.
183dc794d3dSSakari Ailus  * @rst_hist_array: write 1 to trigger histogram array reset.
184dc794d3dSSakari Ailus  * @done_rst_hist_array: flag for histogram array reset done.
185dc794d3dSSakari Ailus  * @x_start: X value of top left corner of ROI, default 0.
186dc794d3dSSakari Ailus  * @y_start: Y value of top left corner of ROI, default 0.
187dc794d3dSSakari Ailus  * @x_end: X value of bottom right corner of ROI
188dc794d3dSSakari Ailus  * @y_end: Y value of bottom right corner of ROI
189dc794d3dSSakari Ailus  *
190dc794d3dSSakari Ailus  * The AE block accumulates 4 global weighted histograms(R, G, B, Y) over
191dc794d3dSSakari Ailus  * a defined ROI within the frame. The contribution of each pixel into the
192dc794d3dSSakari Ailus  * histogram, defined by &ipu3_uapi_ae_weight_elem LUT, is indexed by a grid.
193dc794d3dSSakari Ailus  */
194dc794d3dSSakari Ailus struct ipu3_uapi_ae_grid_config {
195dc794d3dSSakari Ailus 	__u8 width;
196dc794d3dSSakari Ailus 	__u8 height;
197dc794d3dSSakari Ailus 	__u8 block_width_log2:4;
198dc794d3dSSakari Ailus 	__u8 block_height_log2:4;
199dc794d3dSSakari Ailus 	__u8 reserved0:5;
200dc794d3dSSakari Ailus 	__u8 ae_en:1;
201dc794d3dSSakari Ailus 	__u8 rst_hist_array:1;
202dc794d3dSSakari Ailus 	__u8 done_rst_hist_array:1;
203dc794d3dSSakari Ailus 	__u16 x_start;
204dc794d3dSSakari Ailus 	__u16 y_start;
205dc794d3dSSakari Ailus 	__u16 x_end;
206dc794d3dSSakari Ailus 	__u16 y_end;
207dc794d3dSSakari Ailus } __packed;
208dc794d3dSSakari Ailus 
209dc794d3dSSakari Ailus /**
210dc794d3dSSakari Ailus  * struct ipu3_uapi_ae_weight_elem - AE weights LUT
211dc794d3dSSakari Ailus  *
212dc794d3dSSakari Ailus  * @cell0: weighted histogram grid value.
213dc794d3dSSakari Ailus  * @cell1: weighted histogram grid value.
214dc794d3dSSakari Ailus  * @cell2: weighted histogram grid value.
215dc794d3dSSakari Ailus  * @cell3: weighted histogram grid value.
216dc794d3dSSakari Ailus  * @cell4: weighted histogram grid value.
217dc794d3dSSakari Ailus  * @cell5: weighted histogram grid value.
218dc794d3dSSakari Ailus  * @cell6: weighted histogram grid value.
219dc794d3dSSakari Ailus  * @cell7: weighted histogram grid value.
220dc794d3dSSakari Ailus  *
221dc794d3dSSakari Ailus  * Use weighted grid value to give a different contribution factor to each cell.
222dc794d3dSSakari Ailus  * Precision u4, range [0, 15].
223dc794d3dSSakari Ailus  */
224dc794d3dSSakari Ailus struct ipu3_uapi_ae_weight_elem {
225dc794d3dSSakari Ailus 	__u32 cell0:4;
226dc794d3dSSakari Ailus 	__u32 cell1:4;
227dc794d3dSSakari Ailus 	__u32 cell2:4;
228dc794d3dSSakari Ailus 	__u32 cell3:4;
229dc794d3dSSakari Ailus 	__u32 cell4:4;
230dc794d3dSSakari Ailus 	__u32 cell5:4;
231dc794d3dSSakari Ailus 	__u32 cell6:4;
232dc794d3dSSakari Ailus 	__u32 cell7:4;
233dc794d3dSSakari Ailus } __packed;
234dc794d3dSSakari Ailus 
235dc794d3dSSakari Ailus /**
236dc794d3dSSakari Ailus  * struct ipu3_uapi_ae_ccm - AE coefficients for WB and CCM
237dc794d3dSSakari Ailus  *
238dc794d3dSSakari Ailus  * @gain_gr: WB gain factor for the gr channels. Default 256.
239dc794d3dSSakari Ailus  * @gain_r: WB gain factor for the r channel. Default 256.
240dc794d3dSSakari Ailus  * @gain_b: WB gain factor for the b channel. Default 256.
241dc794d3dSSakari Ailus  * @gain_gb: WB gain factor for the gb channels. Default 256.
242dc794d3dSSakari Ailus  * @mat: 4x4 matrix that transforms Bayer quad output from WB to RGB+Y.
243dc794d3dSSakari Ailus  *
244dc794d3dSSakari Ailus  * Default:
245dc794d3dSSakari Ailus  *	128, 0, 0, 0,
246dc794d3dSSakari Ailus  *	0, 128, 0, 0,
247dc794d3dSSakari Ailus  *	0, 0, 128, 0,
248dc794d3dSSakari Ailus  *	0, 0, 0, 128,
249dc794d3dSSakari Ailus  *
250dc794d3dSSakari Ailus  * As part of the raw frame pre-process stage, the WB and color conversion need
251dc794d3dSSakari Ailus  * to be applied to expose the impact of these gain operations.
252dc794d3dSSakari Ailus  */
253dc794d3dSSakari Ailus struct ipu3_uapi_ae_ccm {
254dc794d3dSSakari Ailus 	__u16 gain_gr;
255dc794d3dSSakari Ailus 	__u16 gain_r;
256dc794d3dSSakari Ailus 	__u16 gain_b;
257dc794d3dSSakari Ailus 	__u16 gain_gb;
258dc794d3dSSakari Ailus 	__s16 mat[16];
259dc794d3dSSakari Ailus } __packed;
260dc794d3dSSakari Ailus 
261dc794d3dSSakari Ailus /**
262dc794d3dSSakari Ailus  * struct ipu3_uapi_ae_config - AE config
263dc794d3dSSakari Ailus  *
264dc794d3dSSakari Ailus  * @grid_cfg:	config for auto exposure statistics grid. See struct
2653a7438c8SBingbu Cao  *		&ipu3_uapi_ae_grid_config, as Imgu did not support output
2663a7438c8SBingbu Cao  *		auto exposure statistics, so user can ignore this configuration
2673a7438c8SBingbu Cao  *		and use the RGB table in auto-whitebalance statistics instead.
268dc794d3dSSakari Ailus  * @weights:	&IPU3_UAPI_AE_WEIGHTS is based on 32x24 blocks in the grid.
269dc794d3dSSakari Ailus  *		Each grid cell has a corresponding value in weights LUT called
270dc794d3dSSakari Ailus  *		grid value, global histogram is updated based on grid value and
271dc794d3dSSakari Ailus  *		pixel value.
272dc794d3dSSakari Ailus  * @ae_ccm:	Color convert matrix pre-processing block.
273dc794d3dSSakari Ailus  *
274dc794d3dSSakari Ailus  * Calculate AE grid from image resolution, resample ae weights.
275dc794d3dSSakari Ailus  */
276dc794d3dSSakari Ailus struct ipu3_uapi_ae_config {
277dc794d3dSSakari Ailus 	struct ipu3_uapi_ae_grid_config grid_cfg __attribute__((aligned(32)));
278dc794d3dSSakari Ailus 	struct ipu3_uapi_ae_weight_elem weights[IPU3_UAPI_AE_WEIGHTS]
279dc794d3dSSakari Ailus 						__attribute__((aligned(32)));
280dc794d3dSSakari Ailus 	struct ipu3_uapi_ae_ccm ae_ccm __attribute__((aligned(32)));
281dc794d3dSSakari Ailus } __packed;
282dc794d3dSSakari Ailus 
283dc794d3dSSakari Ailus /**
284dc794d3dSSakari Ailus  * struct ipu3_uapi_af_filter_config - AF 2D filter for contrast measurements
285dc794d3dSSakari Ailus  *
286dc794d3dSSakari Ailus  * @y1_coeff_0:	filter Y1, structure: 3x11, support both symmetry and
287dc794d3dSSakari Ailus  *		anti-symmetry type. A12 is center, A1-A11 are neighbours.
288dc794d3dSSakari Ailus  *		for analyzing low frequency content, used to calculate sum
289dc794d3dSSakari Ailus  *		of gradients in x direction.
290dc794d3dSSakari Ailus  * @y1_coeff_0.a1:	filter1 coefficients A1, u8, default 0.
291dc794d3dSSakari Ailus  * @y1_coeff_0.a2:	filter1 coefficients A2, u8, default 0.
292dc794d3dSSakari Ailus  * @y1_coeff_0.a3:	filter1 coefficients A3, u8, default 0.
293dc794d3dSSakari Ailus  * @y1_coeff_0.a4:	filter1 coefficients A4, u8, default 0.
294dc794d3dSSakari Ailus  * @y1_coeff_1:		Struct
295dc794d3dSSakari Ailus  * @y1_coeff_1.a5:	filter1 coefficients A5, u8, default 0.
296dc794d3dSSakari Ailus  * @y1_coeff_1.a6:	filter1 coefficients A6, u8, default 0.
297dc794d3dSSakari Ailus  * @y1_coeff_1.a7:	filter1 coefficients A7, u8, default 0.
298dc794d3dSSakari Ailus  * @y1_coeff_1.a8:	filter1 coefficients A8, u8, default 0.
299dc794d3dSSakari Ailus  * @y1_coeff_2:		Struct
300dc794d3dSSakari Ailus  * @y1_coeff_2.a9:	filter1 coefficients A9, u8, default 0.
301dc794d3dSSakari Ailus  * @y1_coeff_2.a10:	filter1 coefficients A10, u8, default 0.
302dc794d3dSSakari Ailus  * @y1_coeff_2.a11:	filter1 coefficients A11, u8, default 0.
303dc794d3dSSakari Ailus  * @y1_coeff_2.a12:	filter1 coefficients A12, u8, default 128.
304dc794d3dSSakari Ailus  * @y1_sign_vec:	Each bit corresponds to one coefficient sign bit,
305dc794d3dSSakari Ailus  *			0: positive, 1: negative, default 0.
306dc794d3dSSakari Ailus  * @y2_coeff_0:	Y2, same structure as Y1. For analyzing high frequency content.
307dc794d3dSSakari Ailus  * @y2_coeff_0.a1:	filter2 coefficients A1, u8, default 0.
308dc794d3dSSakari Ailus  * @y2_coeff_0.a2:	filter2 coefficients A2, u8, default 0.
309dc794d3dSSakari Ailus  * @y2_coeff_0.a3:	filter2 coefficients A3, u8, default 0.
310dc794d3dSSakari Ailus  * @y2_coeff_0.a4:	filter2 coefficients A4, u8, default 0.
311dc794d3dSSakari Ailus  * @y2_coeff_1:	Struct
312dc794d3dSSakari Ailus  * @y2_coeff_1.a5:	filter2 coefficients A5, u8, default 0.
313dc794d3dSSakari Ailus  * @y2_coeff_1.a6:	filter2 coefficients A6, u8, default 0.
314dc794d3dSSakari Ailus  * @y2_coeff_1.a7:	filter2 coefficients A7, u8, default 0.
315dc794d3dSSakari Ailus  * @y2_coeff_1.a8:	filter2 coefficients A8, u8, default 0.
316dc794d3dSSakari Ailus  * @y2_coeff_2:	Struct
317dc794d3dSSakari Ailus  * @y2_coeff_2.a9:	filter1 coefficients A9, u8, default 0.
318dc794d3dSSakari Ailus  * @y2_coeff_2.a10:	filter1 coefficients A10, u8, default 0.
319dc794d3dSSakari Ailus  * @y2_coeff_2.a11:	filter1 coefficients A11, u8, default 0.
320dc794d3dSSakari Ailus  * @y2_coeff_2.a12:	filter1 coefficients A12, u8, default 128.
321dc794d3dSSakari Ailus  * @y2_sign_vec:	Each bit corresponds to one coefficient sign bit,
322dc794d3dSSakari Ailus  *			0: positive, 1: negative, default 0.
323dc794d3dSSakari Ailus  * @y_calc:	Pre-processing that converts Bayer quad to RGB+Y values to be
324dc794d3dSSakari Ailus  *		used for building histogram. Range [0, 32], default 8.
325dc794d3dSSakari Ailus  * Rule:
326dc794d3dSSakari Ailus  *		y_gen_rate_gr + y_gen_rate_r + y_gen_rate_b + y_gen_rate_gb = 32
327dc794d3dSSakari Ailus  *		A single Y is calculated based on sum of Gr/R/B/Gb based on
328dc794d3dSSakari Ailus  *		their contribution ratio.
329dc794d3dSSakari Ailus  * @y_calc.y_gen_rate_gr:	Contribution ratio Gr for Y
330dc794d3dSSakari Ailus  * @y_calc.y_gen_rate_r:	Contribution ratio R for Y
331dc794d3dSSakari Ailus  * @y_calc.y_gen_rate_b:	Contribution ratio B for Y
332dc794d3dSSakari Ailus  * @y_calc.y_gen_rate_gb:	Contribution ratio Gb for Y
333dc794d3dSSakari Ailus  * @nf:	The shift right value that should be applied during the Y1/Y2 filter to
334dc794d3dSSakari Ailus  *	make sure the total memory needed is 2 bytes per grid cell.
335dc794d3dSSakari Ailus  * @nf.reserved0:	reserved
336dc794d3dSSakari Ailus  * @nf.y1_nf:	Normalization factor for the convolution coeffs of y1,
337dc794d3dSSakari Ailus  *		should be log2 of the sum of the abs values of the filter
338dc794d3dSSakari Ailus  *		coeffs, default 7 (2^7 = 128).
339dc794d3dSSakari Ailus  * @nf.reserved1:	reserved
340dc794d3dSSakari Ailus  * @nf.y2_nf:	Normalization factor for y2, should be log2 of the sum of the
341dc794d3dSSakari Ailus  *		abs values of the filter coeffs.
342dc794d3dSSakari Ailus  * @nf.reserved2:	reserved
343dc794d3dSSakari Ailus  */
344dc794d3dSSakari Ailus struct ipu3_uapi_af_filter_config {
345dc794d3dSSakari Ailus 	struct {
346dc794d3dSSakari Ailus 		__u8 a1;
347dc794d3dSSakari Ailus 		__u8 a2;
348dc794d3dSSakari Ailus 		__u8 a3;
349dc794d3dSSakari Ailus 		__u8 a4;
350dc794d3dSSakari Ailus 	} y1_coeff_0;
351dc794d3dSSakari Ailus 	struct {
352dc794d3dSSakari Ailus 		__u8 a5;
353dc794d3dSSakari Ailus 		__u8 a6;
354dc794d3dSSakari Ailus 		__u8 a7;
355dc794d3dSSakari Ailus 		__u8 a8;
356dc794d3dSSakari Ailus 	} y1_coeff_1;
357dc794d3dSSakari Ailus 	struct {
358dc794d3dSSakari Ailus 		__u8 a9;
359dc794d3dSSakari Ailus 		__u8 a10;
360dc794d3dSSakari Ailus 		__u8 a11;
361dc794d3dSSakari Ailus 		__u8 a12;
362dc794d3dSSakari Ailus 	} y1_coeff_2;
363dc794d3dSSakari Ailus 
364dc794d3dSSakari Ailus 	__u32 y1_sign_vec;
365dc794d3dSSakari Ailus 
366dc794d3dSSakari Ailus 	struct {
367dc794d3dSSakari Ailus 		__u8 a1;
368dc794d3dSSakari Ailus 		__u8 a2;
369dc794d3dSSakari Ailus 		__u8 a3;
370dc794d3dSSakari Ailus 		__u8 a4;
371dc794d3dSSakari Ailus 	} y2_coeff_0;
372dc794d3dSSakari Ailus 	struct {
373dc794d3dSSakari Ailus 		__u8 a5;
374dc794d3dSSakari Ailus 		__u8 a6;
375dc794d3dSSakari Ailus 		__u8 a7;
376dc794d3dSSakari Ailus 		__u8 a8;
377dc794d3dSSakari Ailus 	} y2_coeff_1;
378dc794d3dSSakari Ailus 	struct {
379dc794d3dSSakari Ailus 		__u8 a9;
380dc794d3dSSakari Ailus 		__u8 a10;
381dc794d3dSSakari Ailus 		__u8 a11;
382dc794d3dSSakari Ailus 		__u8 a12;
383dc794d3dSSakari Ailus 	} y2_coeff_2;
384dc794d3dSSakari Ailus 
385dc794d3dSSakari Ailus 	__u32 y2_sign_vec;
386dc794d3dSSakari Ailus 
387dc794d3dSSakari Ailus 	struct {
388dc794d3dSSakari Ailus 		__u8 y_gen_rate_gr;
389dc794d3dSSakari Ailus 		__u8 y_gen_rate_r;
390dc794d3dSSakari Ailus 		__u8 y_gen_rate_b;
391dc794d3dSSakari Ailus 		__u8 y_gen_rate_gb;
392dc794d3dSSakari Ailus 	} y_calc;
393dc794d3dSSakari Ailus 
394dc794d3dSSakari Ailus 	struct {
395dc794d3dSSakari Ailus 		__u32 reserved0:8;
396dc794d3dSSakari Ailus 		__u32 y1_nf:4;
397dc794d3dSSakari Ailus 		__u32 reserved1:4;
398dc794d3dSSakari Ailus 		__u32 y2_nf:4;
399dc794d3dSSakari Ailus 		__u32 reserved2:12;
400dc794d3dSSakari Ailus 	} nf;
401dc794d3dSSakari Ailus } __packed;
402dc794d3dSSakari Ailus 
403dc794d3dSSakari Ailus #define IPU3_UAPI_AF_MAX_SETS				24
404dc794d3dSSakari Ailus #define IPU3_UAPI_AF_MD_ITEM_SIZE			4
405dc794d3dSSakari Ailus #define IPU3_UAPI_AF_SPARE_FOR_BUBBLES \
406dc794d3dSSakari Ailus 	(IPU3_UAPI_MAX_BUBBLE_SIZE * IPU3_UAPI_MAX_STRIPES * \
407dc794d3dSSakari Ailus 	 IPU3_UAPI_AF_MD_ITEM_SIZE)
408dc794d3dSSakari Ailus #define IPU3_UAPI_AF_Y_TABLE_SET_SIZE			128
409dc794d3dSSakari Ailus #define IPU3_UAPI_AF_Y_TABLE_MAX_SIZE \
410dc794d3dSSakari Ailus 	(IPU3_UAPI_AF_MAX_SETS * \
411dc794d3dSSakari Ailus 	 (IPU3_UAPI_AF_Y_TABLE_SET_SIZE + IPU3_UAPI_AF_SPARE_FOR_BUBBLES) * \
412dc794d3dSSakari Ailus 	 IPU3_UAPI_MAX_STRIPES)
413dc794d3dSSakari Ailus 
414dc794d3dSSakari Ailus /**
415dc794d3dSSakari Ailus  * struct ipu3_uapi_af_raw_buffer - AF meta data
416dc794d3dSSakari Ailus  *
417dc794d3dSSakari Ailus  * @y_table:	Each color component will be convolved separately with filter1
418dc794d3dSSakari Ailus  *		and filter2 and the result will be summed out and averaged for
419dc794d3dSSakari Ailus  *		each cell.
420dc794d3dSSakari Ailus  */
421dc794d3dSSakari Ailus struct ipu3_uapi_af_raw_buffer {
422dc794d3dSSakari Ailus 	__u8 y_table[IPU3_UAPI_AF_Y_TABLE_MAX_SIZE] __attribute__((aligned(32)));
423dc794d3dSSakari Ailus } __packed;
424dc794d3dSSakari Ailus 
425dc794d3dSSakari Ailus /**
426dc794d3dSSakari Ailus  * struct ipu3_uapi_af_config_s - AF config
427dc794d3dSSakari Ailus  *
428dc794d3dSSakari Ailus  * @filter_config: AF uses Y1 and Y2 filters as configured in
429dc794d3dSSakari Ailus  *		   &ipu3_uapi_af_filter_config
430dc794d3dSSakari Ailus  * @padding: paddings
431dc794d3dSSakari Ailus  * @grid_cfg: See &ipu3_uapi_grid_config, default resolution 16x16. Use large
432dc794d3dSSakari Ailus  *	      grid size for large image and vice versa.
433dc794d3dSSakari Ailus  */
434dc794d3dSSakari Ailus struct ipu3_uapi_af_config_s {
435dc794d3dSSakari Ailus 	struct ipu3_uapi_af_filter_config filter_config __attribute__((aligned(32)));
436dc794d3dSSakari Ailus 	__u8 padding[4];
437dc794d3dSSakari Ailus 	struct ipu3_uapi_grid_config grid_cfg __attribute__((aligned(32)));
438dc794d3dSSakari Ailus } __packed;
439dc794d3dSSakari Ailus 
440dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_FR_MAX_SETS			24
441dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_FR_MD_ITEM_SIZE			8
442dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_FR_BAYER_TBL_SIZE			256
443dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_FR_SPARE_FOR_BUBBLES \
444dc794d3dSSakari Ailus 	(IPU3_UAPI_MAX_BUBBLE_SIZE * IPU3_UAPI_MAX_STRIPES * \
445dc794d3dSSakari Ailus 	 IPU3_UAPI_AWB_FR_MD_ITEM_SIZE)
446dc794d3dSSakari Ailus #define IPU3_UAPI_AWB_FR_BAYER_TABLE_MAX_SIZE \
447dc794d3dSSakari Ailus 	(IPU3_UAPI_AWB_FR_MAX_SETS * \
448dc794d3dSSakari Ailus 	(IPU3_UAPI_AWB_FR_BAYER_TBL_SIZE + \
449dc794d3dSSakari Ailus 	 IPU3_UAPI_AWB_FR_SPARE_FOR_BUBBLES) * IPU3_UAPI_MAX_STRIPES)
450dc794d3dSSakari Ailus 
451dc794d3dSSakari Ailus /**
452dc794d3dSSakari Ailus  * struct ipu3_uapi_awb_fr_raw_buffer - AWB filter response meta data
453dc794d3dSSakari Ailus  *
454dc794d3dSSakari Ailus  * @meta_data: Statistics output on the grid after convolving with 1D filter.
455dc794d3dSSakari Ailus  */
456dc794d3dSSakari Ailus struct ipu3_uapi_awb_fr_raw_buffer {
457dc794d3dSSakari Ailus 	__u8 meta_data[IPU3_UAPI_AWB_FR_BAYER_TABLE_MAX_SIZE]
458dc794d3dSSakari Ailus 		__attribute__((aligned(32)));
459dc794d3dSSakari Ailus } __packed;
460dc794d3dSSakari Ailus 
461dc794d3dSSakari Ailus /**
462dc794d3dSSakari Ailus  * struct ipu3_uapi_awb_fr_config_s - AWB filter response config
463dc794d3dSSakari Ailus  *
464dc794d3dSSakari Ailus  * @grid_cfg:	grid config, default 16x16.
465dc794d3dSSakari Ailus  * @bayer_coeff:	1D Filter 1x11 center symmetry/anti-symmetry.
466dc794d3dSSakari Ailus  *			coefficients defaults { 0, 0, 0, 0, 0, 128 }.
467dc794d3dSSakari Ailus  *			Applied on whole image for each Bayer channel separately
468dc794d3dSSakari Ailus  *			by a weighted sum of its 11x1 neighbors.
469dc794d3dSSakari Ailus  * @reserved1:	reserved
470dc794d3dSSakari Ailus  * @bayer_sign:	sign of filter coefficients, default 0.
471dc794d3dSSakari Ailus  * @bayer_nf:	normalization factor for the convolution coeffs, to make sure
472dc794d3dSSakari Ailus  *		total memory needed is within pre-determined range.
473dc794d3dSSakari Ailus  *		NF should be the log2 of the sum of the abs values of the
474dc794d3dSSakari Ailus  *		filter coeffs, range [7, 14], default 7.
475dc794d3dSSakari Ailus  * @reserved2:	reserved
476dc794d3dSSakari Ailus  */
477dc794d3dSSakari Ailus struct ipu3_uapi_awb_fr_config_s {
478dc794d3dSSakari Ailus 	struct ipu3_uapi_grid_config grid_cfg;
479dc794d3dSSakari Ailus 	__u8 bayer_coeff[6];
480dc794d3dSSakari Ailus 	__u16 reserved1;
481dc794d3dSSakari Ailus 	__u32 bayer_sign;
482dc794d3dSSakari Ailus 	__u8 bayer_nf;
483dc794d3dSSakari Ailus 	__u8 reserved2[7];
484dc794d3dSSakari Ailus } __packed;
485dc794d3dSSakari Ailus 
486dc794d3dSSakari Ailus /**
487dc794d3dSSakari Ailus  * struct ipu3_uapi_4a_config - 4A config
488dc794d3dSSakari Ailus  *
489dc794d3dSSakari Ailus  * @awb_config: &ipu3_uapi_awb_config_s, default resolution 16x16
490dc794d3dSSakari Ailus  * @ae_grd_config: auto exposure statistics &ipu3_uapi_ae_grid_config
491dc794d3dSSakari Ailus  * @padding: paddings
492dc794d3dSSakari Ailus  * @af_config: auto focus config &ipu3_uapi_af_config_s
493dc794d3dSSakari Ailus  * @awb_fr_config: &ipu3_uapi_awb_fr_config_s, default resolution 16x16
494dc794d3dSSakari Ailus  */
495dc794d3dSSakari Ailus struct ipu3_uapi_4a_config {
496dc794d3dSSakari Ailus 	struct ipu3_uapi_awb_config_s awb_config __attribute__((aligned(32)));
497dc794d3dSSakari Ailus 	struct ipu3_uapi_ae_grid_config ae_grd_config;
498dc794d3dSSakari Ailus 	__u8 padding[20];
499dc794d3dSSakari Ailus 	struct ipu3_uapi_af_config_s af_config;
500dc794d3dSSakari Ailus 	struct ipu3_uapi_awb_fr_config_s awb_fr_config
501dc794d3dSSakari Ailus 		__attribute__((aligned(32)));
502dc794d3dSSakari Ailus } __packed;
503dc794d3dSSakari Ailus 
504dc794d3dSSakari Ailus /**
505dc794d3dSSakari Ailus  * struct ipu3_uapi_bubble_info - Bubble info for host side debugging
506dc794d3dSSakari Ailus  *
507dc794d3dSSakari Ailus  * @num_of_stripes: A single frame is divided into several parts called stripes
508dc794d3dSSakari Ailus  *		    due to limitation on line buffer memory.
509dc794d3dSSakari Ailus  *		    The separation between the stripes is vertical. Each such
510dc794d3dSSakari Ailus  *		    stripe is processed as a single frame by the ISP pipe.
511dc794d3dSSakari Ailus  * @padding: padding bytes.
512dc794d3dSSakari Ailus  * @num_sets: number of sets.
513dc794d3dSSakari Ailus  * @padding1: padding bytes.
514dc794d3dSSakari Ailus  * @size_of_set: set size.
515dc794d3dSSakari Ailus  * @padding2: padding bytes.
516dc794d3dSSakari Ailus  * @bubble_size: is the amount of padding in the bubble expressed in "sets".
517dc794d3dSSakari Ailus  * @padding3: padding bytes.
518dc794d3dSSakari Ailus  */
519dc794d3dSSakari Ailus struct ipu3_uapi_bubble_info {
520dc794d3dSSakari Ailus 	__u32 num_of_stripes __attribute__((aligned(32)));
521dc794d3dSSakari Ailus 	__u8 padding[28];
522dc794d3dSSakari Ailus 	__u32 num_sets;
523dc794d3dSSakari Ailus 	__u8 padding1[28];
524dc794d3dSSakari Ailus 	__u32 size_of_set;
525dc794d3dSSakari Ailus 	__u8 padding2[28];
526dc794d3dSSakari Ailus 	__u32 bubble_size;
527dc794d3dSSakari Ailus 	__u8 padding3[28];
528dc794d3dSSakari Ailus } __packed;
529dc794d3dSSakari Ailus 
530dc794d3dSSakari Ailus /*
531dc794d3dSSakari Ailus  * struct ipu3_uapi_stats_3a_bubble_info_per_stripe
532dc794d3dSSakari Ailus  */
533dc794d3dSSakari Ailus struct ipu3_uapi_stats_3a_bubble_info_per_stripe {
534dc794d3dSSakari Ailus 	struct ipu3_uapi_bubble_info awb[IPU3_UAPI_MAX_STRIPES];
535dc794d3dSSakari Ailus 	struct ipu3_uapi_bubble_info af[IPU3_UAPI_MAX_STRIPES];
536dc794d3dSSakari Ailus 	struct ipu3_uapi_bubble_info awb_fr[IPU3_UAPI_MAX_STRIPES];
537dc794d3dSSakari Ailus } __packed;
538dc794d3dSSakari Ailus 
539dc794d3dSSakari Ailus /**
540dc794d3dSSakari Ailus  * struct ipu3_uapi_ff_status - Enable bits for each 3A fixed function
541dc794d3dSSakari Ailus  *
542dc794d3dSSakari Ailus  * @awb_en: auto white balance enable
543dc794d3dSSakari Ailus  * @padding: padding config
544dc794d3dSSakari Ailus  * @ae_en: auto exposure enable
545dc794d3dSSakari Ailus  * @padding1: padding config
546dc794d3dSSakari Ailus  * @af_en: auto focus enable
547dc794d3dSSakari Ailus  * @padding2: padding config
548dc794d3dSSakari Ailus  * @awb_fr_en: awb filter response enable bit
549dc794d3dSSakari Ailus  * @padding3: padding config
550dc794d3dSSakari Ailus  */
551dc794d3dSSakari Ailus struct ipu3_uapi_ff_status {
552dc794d3dSSakari Ailus 	__u32 awb_en __attribute__((aligned(32)));
553dc794d3dSSakari Ailus 	__u8 padding[28];
554dc794d3dSSakari Ailus 	__u32 ae_en;
555dc794d3dSSakari Ailus 	__u8 padding1[28];
556dc794d3dSSakari Ailus 	__u32 af_en;
557dc794d3dSSakari Ailus 	__u8 padding2[28];
558dc794d3dSSakari Ailus 	__u32 awb_fr_en;
559dc794d3dSSakari Ailus 	__u8 padding3[28];
560dc794d3dSSakari Ailus } __packed;
561dc794d3dSSakari Ailus 
562dc794d3dSSakari Ailus /**
563dc794d3dSSakari Ailus  * struct ipu3_uapi_stats_3a - 3A statistics
564dc794d3dSSakari Ailus  *
565dc794d3dSSakari Ailus  * @awb_raw_buffer: auto white balance meta data &ipu3_uapi_awb_raw_buffer
566dc794d3dSSakari Ailus  * @ae_raw_buffer: auto exposure raw data &ipu3_uapi_ae_raw_buffer_aligned
5673a7438c8SBingbu Cao  *                 current Imgu does not output the auto exposure statistics
5683a7438c8SBingbu Cao  *                 to ae_raw_buffer, the user such as 3A algorithm can use the
5693a7438c8SBingbu Cao  *                 RGB table in &ipu3_uapi_awb_raw_buffer to do auto-exposure.
570dc794d3dSSakari Ailus  * @af_raw_buffer: &ipu3_uapi_af_raw_buffer for auto focus meta data
571dc794d3dSSakari Ailus  * @awb_fr_raw_buffer: value as specified by &ipu3_uapi_awb_fr_raw_buffer
572dc794d3dSSakari Ailus  * @stats_4a_config: 4a statistics config as defined by &ipu3_uapi_4a_config.
573dc794d3dSSakari Ailus  * @ae_join_buffers: 1 to use ae_raw_buffer.
574dc794d3dSSakari Ailus  * @padding: padding config
575dc794d3dSSakari Ailus  * @stats_3a_bubble_per_stripe: a &ipu3_uapi_stats_3a_bubble_info_per_stripe
576dc794d3dSSakari Ailus  * @stats_3a_status: 3a statistics status set in &ipu3_uapi_ff_status
577dc794d3dSSakari Ailus  */
578dc794d3dSSakari Ailus struct ipu3_uapi_stats_3a {
579dc794d3dSSakari Ailus 	struct ipu3_uapi_awb_raw_buffer awb_raw_buffer;
580dc794d3dSSakari Ailus 	struct ipu3_uapi_ae_raw_buffer_aligned
581dc794d3dSSakari Ailus 			ae_raw_buffer[IPU3_UAPI_MAX_STRIPES];
582dc794d3dSSakari Ailus 	struct ipu3_uapi_af_raw_buffer af_raw_buffer;
583dc794d3dSSakari Ailus 	struct ipu3_uapi_awb_fr_raw_buffer awb_fr_raw_buffer;
584dc794d3dSSakari Ailus 	struct ipu3_uapi_4a_config stats_4a_config;
585dc794d3dSSakari Ailus 	__u32 ae_join_buffers;
586dc794d3dSSakari Ailus 	__u8 padding[28];
587dc794d3dSSakari Ailus 	struct ipu3_uapi_stats_3a_bubble_info_per_stripe
588dc794d3dSSakari Ailus 			stats_3a_bubble_per_stripe;
589dc794d3dSSakari Ailus 	struct ipu3_uapi_ff_status stats_3a_status;
590dc794d3dSSakari Ailus } __packed;
591dc794d3dSSakari Ailus 
592dc794d3dSSakari Ailus /******************* ipu3_uapi_acc_param *******************/
593dc794d3dSSakari Ailus 
594dc794d3dSSakari Ailus #define IPU3_UAPI_ISP_VEC_ELEMS				64
595dc794d3dSSakari Ailus #define IPU3_UAPI_ISP_TNR3_VMEM_LEN			9
596dc794d3dSSakari Ailus 
597dc794d3dSSakari Ailus #define IPU3_UAPI_BNR_LUT_SIZE				32
598dc794d3dSSakari Ailus 
599dc794d3dSSakari Ailus /* number of elements in gamma correction LUT */
600dc794d3dSSakari Ailus #define IPU3_UAPI_GAMMA_CORR_LUT_ENTRIES		256
601dc794d3dSSakari Ailus 
602dc794d3dSSakari Ailus /* largest grid is 73x56, for grid_height_per_slice of 2, 73x2 = 146 */
603dc794d3dSSakari Ailus #define IPU3_UAPI_SHD_MAX_CELLS_PER_SET			146
604dc794d3dSSakari Ailus #define IPU3_UAPI_SHD_MAX_CFG_SETS			28
605dc794d3dSSakari Ailus /* Normalization shift aka nf */
606dc794d3dSSakari Ailus #define IPU3_UAPI_SHD_BLGR_NF_SHIFT			13
607dc794d3dSSakari Ailus #define IPU3_UAPI_SHD_BLGR_NF_MASK			7
608dc794d3dSSakari Ailus 
609dc794d3dSSakari Ailus #define IPU3_UAPI_YUVP2_TCC_MACC_TABLE_ELEMENTS		16
610dc794d3dSSakari Ailus #define IPU3_UAPI_YUVP2_TCC_INV_Y_LUT_ELEMENTS		14
611dc794d3dSSakari Ailus #define IPU3_UAPI_YUVP2_TCC_GAIN_PCWL_LUT_ELEMENTS	258
612dc794d3dSSakari Ailus #define IPU3_UAPI_YUVP2_TCC_R_SQR_LUT_ELEMENTS		24
613dc794d3dSSakari Ailus 
614dc794d3dSSakari Ailus #define IPU3_UAPI_ANR_LUT_SIZE				26
615dc794d3dSSakari Ailus #define IPU3_UAPI_ANR_PYRAMID_SIZE			22
616dc794d3dSSakari Ailus 
617dc794d3dSSakari Ailus #define IPU3_UAPI_LIN_LUT_SIZE				64
618dc794d3dSSakari Ailus 
619dc794d3dSSakari Ailus /* Bayer Noise Reduction related structs */
620dc794d3dSSakari Ailus 
621dc794d3dSSakari Ailus /**
622dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_wb_gains_config - White balance gains
623dc794d3dSSakari Ailus  *
624dc794d3dSSakari Ailus  * @gr:	white balance gain for Gr channel.
625dc794d3dSSakari Ailus  * @r:	white balance gain for R channel.
626dc794d3dSSakari Ailus  * @b:	white balance gain for B channel.
627dc794d3dSSakari Ailus  * @gb:	white balance gain for Gb channel.
628dc794d3dSSakari Ailus  *
629*4b7444ffSJean-Michel Hautbois  * For BNR parameters WB gain factor for the three channels [Ggr, Ggb, Gb, Gr].
630*4b7444ffSJean-Michel Hautbois  * Their precision is U3.13 and the range is (0, 8) and the actual gain is
631*4b7444ffSJean-Michel Hautbois  * Gx + 1, it is typically Gx = 1.
632*4b7444ffSJean-Michel Hautbois  *
633*4b7444ffSJean-Michel Hautbois  * Pout = {Pin * (1 + Gx)}.
634dc794d3dSSakari Ailus  */
635dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_wb_gains_config {
636dc794d3dSSakari Ailus 	__u16 gr;
637dc794d3dSSakari Ailus 	__u16 r;
638dc794d3dSSakari Ailus 	__u16 b;
639dc794d3dSSakari Ailus 	__u16 gb;
640dc794d3dSSakari Ailus } __packed;
641dc794d3dSSakari Ailus 
642dc794d3dSSakari Ailus /**
643dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_wb_gains_thr_config - Threshold config
644dc794d3dSSakari Ailus  *
645dc794d3dSSakari Ailus  * @gr:	white balance threshold gain for Gr channel.
646dc794d3dSSakari Ailus  * @r:	white balance threshold gain for R channel.
647dc794d3dSSakari Ailus  * @b:	white balance threshold gain for B channel.
648dc794d3dSSakari Ailus  * @gb:	white balance threshold gain for Gb channel.
649dc794d3dSSakari Ailus  *
650dc794d3dSSakari Ailus  * Defines the threshold that specifies how different a defect pixel can be from
651dc794d3dSSakari Ailus  * its neighbors.(used by dynamic defect pixel correction sub block)
652dc794d3dSSakari Ailus  * Precision u4.4 range [0, 8].
653dc794d3dSSakari Ailus  */
654dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_wb_gains_thr_config {
655dc794d3dSSakari Ailus 	__u8 gr;
656dc794d3dSSakari Ailus 	__u8 r;
657dc794d3dSSakari Ailus 	__u8 b;
658dc794d3dSSakari Ailus 	__u8 gb;
659dc794d3dSSakari Ailus } __packed;
660dc794d3dSSakari Ailus 
661dc794d3dSSakari Ailus /**
662dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_thr_coeffs_config - Noise model
663dc794d3dSSakari Ailus  *				coefficients that controls noise threshold
664dc794d3dSSakari Ailus  *
665dc794d3dSSakari Ailus  * @cf:	Free coefficient for threshold calculation, range [0, 8191], default 0.
666dc794d3dSSakari Ailus  * @reserved0:	reserved
667dc794d3dSSakari Ailus  * @cg:	Gain coefficient for threshold calculation, [0, 31], default 8.
668dc794d3dSSakari Ailus  * @ci:	Intensity coefficient for threshold calculation. range [0, 0x1f]
669dc794d3dSSakari Ailus  *	default 6.
670dc794d3dSSakari Ailus  *	format: u3.2 (3 most significant bits represent whole number,
671dc794d3dSSakari Ailus  *	2 least significant bits represent the fractional part
672dc794d3dSSakari Ailus  *	with each count representing 0.25)
673dc794d3dSSakari Ailus  *	e.g. 6 in binary format is 00110, that translates to 1.5
674dc794d3dSSakari Ailus  * @reserved1:	reserved
675dc794d3dSSakari Ailus  * @r_nf:	Normalization shift value for r^2 calculation, range [12, 20]
676dc794d3dSSakari Ailus  *		where r is a radius of pixel [row, col] from centor of sensor.
677dc794d3dSSakari Ailus  *		default 14.
678dc794d3dSSakari Ailus  *
679dc794d3dSSakari Ailus  * Threshold used to distinguish between noise and details.
680dc794d3dSSakari Ailus  */
681dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_thr_coeffs_config {
682dc794d3dSSakari Ailus 	__u32 cf:13;
683dc794d3dSSakari Ailus 	__u32 reserved0:3;
684dc794d3dSSakari Ailus 	__u32 cg:5;
685dc794d3dSSakari Ailus 	__u32 ci:5;
686dc794d3dSSakari Ailus 	__u32 reserved1:1;
687dc794d3dSSakari Ailus 	__u32 r_nf:5;
688dc794d3dSSakari Ailus } __packed;
689dc794d3dSSakari Ailus 
690dc794d3dSSakari Ailus /**
691dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_thr_ctrl_shd_config - Shading config
692dc794d3dSSakari Ailus  *
693dc794d3dSSakari Ailus  * @gr:	Coefficient defines lens shading gain approximation for gr channel
694dc794d3dSSakari Ailus  * @r:	Coefficient defines lens shading gain approximation for r channel
695dc794d3dSSakari Ailus  * @b:	Coefficient defines lens shading gain approximation for b channel
696dc794d3dSSakari Ailus  * @gb:	Coefficient defines lens shading gain approximation for gb channel
697dc794d3dSSakari Ailus  *
698dc794d3dSSakari Ailus  * Parameters for noise model (NM) adaptation of BNR due to shading correction.
699dc794d3dSSakari Ailus  * All above have precision of u3.3, default to 0.
700dc794d3dSSakari Ailus  */
701dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_thr_ctrl_shd_config {
702dc794d3dSSakari Ailus 	__u8 gr;
703dc794d3dSSakari Ailus 	__u8 r;
704dc794d3dSSakari Ailus 	__u8 b;
705dc794d3dSSakari Ailus 	__u8 gb;
706dc794d3dSSakari Ailus } __packed;
707dc794d3dSSakari Ailus 
708dc794d3dSSakari Ailus /**
709dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_opt_center_config - Optical center config
710dc794d3dSSakari Ailus  *
711dc794d3dSSakari Ailus  * @x_reset:	Reset value of X (col start - X center). Precision s12.0.
712dc794d3dSSakari Ailus  * @reserved0:	reserved
713dc794d3dSSakari Ailus  * @y_reset:	Reset value of Y (row start - Y center). Precision s12.0.
714dc794d3dSSakari Ailus  * @reserved2:	reserved
715dc794d3dSSakari Ailus  *
716dc794d3dSSakari Ailus  * Distance from corner to optical center for NM adaptation due to shading
717dc794d3dSSakari Ailus  * correction (should be calculated based on shading tables)
718dc794d3dSSakari Ailus  */
719dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_opt_center_config {
720dc794d3dSSakari Ailus 	__s32 x_reset:13;
721dc794d3dSSakari Ailus 	__u32 reserved0:3;
722dc794d3dSSakari Ailus 	__s32 y_reset:13;
723dc794d3dSSakari Ailus 	__u32 reserved2:3;
724dc794d3dSSakari Ailus } __packed;
725dc794d3dSSakari Ailus 
726dc794d3dSSakari Ailus /**
727dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_lut_config - BNR square root lookup table
728dc794d3dSSakari Ailus  *
729dc794d3dSSakari Ailus  * @values: pre-calculated values of square root function.
730dc794d3dSSakari Ailus  *
731dc794d3dSSakari Ailus  * LUT implementation of square root operation.
732dc794d3dSSakari Ailus  */
733dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_lut_config {
734dc794d3dSSakari Ailus 	__u8 values[IPU3_UAPI_BNR_LUT_SIZE];
735dc794d3dSSakari Ailus } __packed;
736dc794d3dSSakari Ailus 
737dc794d3dSSakari Ailus /**
738dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_bp_ctrl_config - Detect bad pixels (bp)
739dc794d3dSSakari Ailus  *
740dc794d3dSSakari Ailus  * @bp_thr_gain:	Defines the threshold that specifies how different a
741dc794d3dSSakari Ailus  *			defect pixel can be from its neighbors. Threshold is
742dc794d3dSSakari Ailus  *			dependent on de-noise threshold calculated by algorithm.
743dc794d3dSSakari Ailus  *			Range [4, 31], default 4.
744dc794d3dSSakari Ailus  * @reserved0:	reserved
745dc794d3dSSakari Ailus  * @defect_mode:	Mode of addressed defect pixels,
746dc794d3dSSakari Ailus  *			0 - single defect pixel is expected,
747dc794d3dSSakari Ailus  *			1 - 2 adjacent defect pixels are expected, default 1.
748dc794d3dSSakari Ailus  * @bp_gain:	Defines how 2nd derivation that passes through a defect pixel
749dc794d3dSSakari Ailus  *		is different from 2nd derivations that pass through
750dc794d3dSSakari Ailus  *		neighbor pixels. u4.2, range [0, 256], default 8.
751dc794d3dSSakari Ailus  * @reserved1:	reserved
752dc794d3dSSakari Ailus  * @w0_coeff:	Blending coefficient of defect pixel correction.
753dc794d3dSSakari Ailus  *		Precision u4, range [0, 8], default 8.
754dc794d3dSSakari Ailus  * @reserved2:	reserved
755dc794d3dSSakari Ailus  * @w1_coeff:	Enable influence of incorrect defect pixel correction to be
756dc794d3dSSakari Ailus  *		avoided. Precision u4, range [1, 8], default 8.
757dc794d3dSSakari Ailus  * @reserved3:	reserved
758dc794d3dSSakari Ailus  */
759dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_bp_ctrl_config {
760dc794d3dSSakari Ailus 	__u32 bp_thr_gain:5;
761dc794d3dSSakari Ailus 	__u32 reserved0:2;
762dc794d3dSSakari Ailus 	__u32 defect_mode:1;
763dc794d3dSSakari Ailus 	__u32 bp_gain:6;
764dc794d3dSSakari Ailus 	__u32 reserved1:18;
765dc794d3dSSakari Ailus 	__u32 w0_coeff:4;
766dc794d3dSSakari Ailus 	__u32 reserved2:4;
767dc794d3dSSakari Ailus 	__u32 w1_coeff:4;
768dc794d3dSSakari Ailus 	__u32 reserved3:20;
769dc794d3dSSakari Ailus } __packed;
770dc794d3dSSakari Ailus 
771dc794d3dSSakari Ailus /**
772dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_dn_detect_ctrl_config - Denoising config
773dc794d3dSSakari Ailus  *
774dc794d3dSSakari Ailus  * @alpha:	Weight of central element of smoothing filter.
775dc794d3dSSakari Ailus  * @beta:	Weight of peripheral elements of smoothing filter, default 4.
776dc794d3dSSakari Ailus  * @gamma:	Weight of diagonal elements of smoothing filter, default 4.
777dc794d3dSSakari Ailus  *
778dc794d3dSSakari Ailus  * beta and gamma parameter define the strength of the noise removal filter.
779dc794d3dSSakari Ailus  *		All above has precision u0.4, range [0, 0xf]
780dc794d3dSSakari Ailus  *		format: u0.4 (no / zero bits represent whole number,
781dc794d3dSSakari Ailus  *		4 bits represent the fractional part
782dc794d3dSSakari Ailus  *		with each count representing 0.0625)
783dc794d3dSSakari Ailus  *		e.g. 0xf translates to 0.0625x15 = 0.9375
784dc794d3dSSakari Ailus  *
785dc794d3dSSakari Ailus  * @reserved0:	reserved
786dc794d3dSSakari Ailus  * @max_inf:	Maximum increase of peripheral or diagonal element influence
787dc794d3dSSakari Ailus  *		relative to the pre-defined value range: [0x5, 0xa]
788dc794d3dSSakari Ailus  * @reserved1:	reserved
789dc794d3dSSakari Ailus  * @gd_enable:	Green disparity enable control, 0 - disable, 1 - enable.
790dc794d3dSSakari Ailus  * @bpc_enable:	Bad pixel correction enable control, 0 - disable, 1 - enable.
791dc794d3dSSakari Ailus  * @bnr_enable:	Bayer noise removal enable control, 0 - disable, 1 - enable.
792dc794d3dSSakari Ailus  * @ff_enable:	Fixed function enable, 0 - disable, 1 - enable.
793dc794d3dSSakari Ailus  * @reserved2:	reserved
794dc794d3dSSakari Ailus  */
795dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_dn_detect_ctrl_config {
796dc794d3dSSakari Ailus 	__u32 alpha:4;
797dc794d3dSSakari Ailus 	__u32 beta:4;
798dc794d3dSSakari Ailus 	__u32 gamma:4;
799dc794d3dSSakari Ailus 	__u32 reserved0:4;
800dc794d3dSSakari Ailus 	__u32 max_inf:4;
801dc794d3dSSakari Ailus 	__u32 reserved1:7;
802dc794d3dSSakari Ailus 	__u32 gd_enable:1;
803dc794d3dSSakari Ailus 	__u32 bpc_enable:1;
804dc794d3dSSakari Ailus 	__u32 bnr_enable:1;
805dc794d3dSSakari Ailus 	__u32 ff_enable:1;
806dc794d3dSSakari Ailus 	__u32 reserved2:1;
807dc794d3dSSakari Ailus } __packed;
808dc794d3dSSakari Ailus 
809dc794d3dSSakari Ailus /**
810dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_opt_center_sqr_config - BNR optical square
811dc794d3dSSakari Ailus  *
812dc794d3dSSakari Ailus  * @x_sqr_reset: Reset value of X^2.
813dc794d3dSSakari Ailus  * @y_sqr_reset: Reset value of Y^2.
814dc794d3dSSakari Ailus  *
815dc794d3dSSakari Ailus  * Please note:
816dc794d3dSSakari Ailus  *
817dc794d3dSSakari Ailus  *    #. X and Y ref to
818dc794d3dSSakari Ailus  *       &ipu3_uapi_bnr_static_config_opt_center_config
819dc794d3dSSakari Ailus  *    #. Both structs are used in threshold formula to calculate r^2, where r
820dc794d3dSSakari Ailus  *       is a radius of pixel [row, col] from centor of sensor.
821dc794d3dSSakari Ailus  */
822dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_opt_center_sqr_config {
823dc794d3dSSakari Ailus 	__u32 x_sqr_reset;
824dc794d3dSSakari Ailus 	__u32 y_sqr_reset;
825dc794d3dSSakari Ailus } __packed;
826dc794d3dSSakari Ailus 
827dc794d3dSSakari Ailus /**
828dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config - BNR static config
829dc794d3dSSakari Ailus  *
830dc794d3dSSakari Ailus  * @wb_gains:	white balance gains &ipu3_uapi_bnr_static_config_wb_gains_config
831dc794d3dSSakari Ailus  * @wb_gains_thr:	white balance gains threshold as defined by
832dc794d3dSSakari Ailus  *			&ipu3_uapi_bnr_static_config_wb_gains_thr_config
833dc794d3dSSakari Ailus  * @thr_coeffs:	coefficients of threshold
834dc794d3dSSakari Ailus  *		&ipu3_uapi_bnr_static_config_thr_coeffs_config
835dc794d3dSSakari Ailus  * @thr_ctrl_shd:	control of shading threshold
836dc794d3dSSakari Ailus  *			&ipu3_uapi_bnr_static_config_thr_ctrl_shd_config
837dc794d3dSSakari Ailus  * @opt_center:	optical center &ipu3_uapi_bnr_static_config_opt_center_config
838dc794d3dSSakari Ailus  *
839dc794d3dSSakari Ailus  * Above parameters and opt_center_sqr are used for white balance and shading.
840dc794d3dSSakari Ailus  *
841dc794d3dSSakari Ailus  * @lut:	lookup table &ipu3_uapi_bnr_static_config_lut_config
842dc794d3dSSakari Ailus  * @bp_ctrl:	detect and remove bad pixels as defined in struct
843dc794d3dSSakari Ailus  *		&ipu3_uapi_bnr_static_config_bp_ctrl_config
844dc794d3dSSakari Ailus  * @dn_detect_ctrl:	detect and remove noise.
845dc794d3dSSakari Ailus  *			&ipu3_uapi_bnr_static_config_dn_detect_ctrl_config
846dc794d3dSSakari Ailus  * @column_size:	The number of pixels in column.
847dc794d3dSSakari Ailus  * @opt_center_sqr:	Reset value of r^2 to optical center, see
848dc794d3dSSakari Ailus  *			&ipu3_uapi_bnr_static_config_opt_center_sqr_config.
849dc794d3dSSakari Ailus  */
850dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config {
851dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_wb_gains_config wb_gains;
852dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_wb_gains_thr_config wb_gains_thr;
853dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_thr_coeffs_config thr_coeffs;
854dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_thr_ctrl_shd_config thr_ctrl_shd;
855dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_opt_center_config opt_center;
856dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_lut_config lut;
857dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_bp_ctrl_config bp_ctrl;
858dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_dn_detect_ctrl_config dn_detect_ctrl;
859dc794d3dSSakari Ailus 	__u32 column_size;
860dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_opt_center_sqr_config opt_center_sqr;
861dc794d3dSSakari Ailus } __packed;
862dc794d3dSSakari Ailus 
863dc794d3dSSakari Ailus /**
864dc794d3dSSakari Ailus  * struct ipu3_uapi_bnr_static_config_green_disparity - Correct green disparity
865dc794d3dSSakari Ailus  *
866dc794d3dSSakari Ailus  * @gd_red:	Shading gain coeff for gr disparity level in bright red region.
867dc794d3dSSakari Ailus  *		Precision u0.6, default 4(0.0625).
868dc794d3dSSakari Ailus  * @reserved0:	reserved
869dc794d3dSSakari Ailus  * @gd_green:	Shading gain coeff for gr disparity level in bright green
870dc794d3dSSakari Ailus  *		region. Precision u0.6, default 4(0.0625).
871dc794d3dSSakari Ailus  * @reserved1:	reserved
872dc794d3dSSakari Ailus  * @gd_blue:	Shading gain coeff for gr disparity level in bright blue region.
873dc794d3dSSakari Ailus  *		Precision u0.6, default 4(0.0625).
874dc794d3dSSakari Ailus  * @reserved2:	reserved
875dc794d3dSSakari Ailus  * @gd_black:	Maximal green disparity level in dark region (stronger disparity
876dc794d3dSSakari Ailus  *		assumed to be image detail). Precision u14, default 80.
877dc794d3dSSakari Ailus  * @reserved3:	reserved
878dc794d3dSSakari Ailus  * @gd_shading:	Change maximal green disparity level according to square
879dc794d3dSSakari Ailus  *		distance from image center.
880dc794d3dSSakari Ailus  * @reserved4:	reserved
881dc794d3dSSakari Ailus  * @gd_support:	Lower bound for the number of second green color pixels in
882dc794d3dSSakari Ailus  *		current pixel neighborhood with less than threshold difference
883dc794d3dSSakari Ailus  *		from it.
884dc794d3dSSakari Ailus  *
885dc794d3dSSakari Ailus  * The shading gain coeff of red, green, blue and black are used to calculate
886dc794d3dSSakari Ailus  * threshold given a pixel's color value and its coordinates in the image.
887dc794d3dSSakari Ailus  *
888dc794d3dSSakari Ailus  * @reserved5:	reserved
889dc794d3dSSakari Ailus  * @gd_clip:	Turn green disparity clip on/off, [0, 1], default 1.
890dc794d3dSSakari Ailus  * @gd_central_weight:	Central pixel weight in 9 pixels weighted sum.
891dc794d3dSSakari Ailus  */
892dc794d3dSSakari Ailus struct ipu3_uapi_bnr_static_config_green_disparity {
893dc794d3dSSakari Ailus 	__u32 gd_red:6;
894dc794d3dSSakari Ailus 	__u32 reserved0:2;
895dc794d3dSSakari Ailus 	__u32 gd_green:6;
896dc794d3dSSakari Ailus 	__u32 reserved1:2;
897dc794d3dSSakari Ailus 	__u32 gd_blue:6;
898dc794d3dSSakari Ailus 	__u32 reserved2:10;
899dc794d3dSSakari Ailus 	__u32 gd_black:14;
900dc794d3dSSakari Ailus 	__u32 reserved3:2;
901dc794d3dSSakari Ailus 	__u32 gd_shading:7;
902dc794d3dSSakari Ailus 	__u32 reserved4:1;
903dc794d3dSSakari Ailus 	__u32 gd_support:2;
904dc794d3dSSakari Ailus 	__u32 reserved5:1;
905dc794d3dSSakari Ailus 	__u32 gd_clip:1;
906dc794d3dSSakari Ailus 	__u32 gd_central_weight:4;
907dc794d3dSSakari Ailus } __packed;
908dc794d3dSSakari Ailus 
909dc794d3dSSakari Ailus /**
910dc794d3dSSakari Ailus  * struct ipu3_uapi_dm_config - De-mosaic parameters
911dc794d3dSSakari Ailus  *
912dc794d3dSSakari Ailus  * @dm_en:	de-mosaic enable.
913dc794d3dSSakari Ailus  * @ch_ar_en:	Checker artifacts removal enable flag. Default 0.
914dc794d3dSSakari Ailus  * @fcc_en:	False color correction (FCC) enable flag. Default 0.
915dc794d3dSSakari Ailus  * @reserved0:	reserved
916dc794d3dSSakari Ailus  * @frame_width:	do not care
917dc794d3dSSakari Ailus  * @gamma_sc:	Sharpening coefficient (coefficient of 2-d derivation of
918dc794d3dSSakari Ailus  *		complementary color in Hamilton-Adams interpolation).
919dc794d3dSSakari Ailus  *		u5, range [0, 31], default 8.
920dc794d3dSSakari Ailus  * @reserved1:	reserved
921dc794d3dSSakari Ailus  * @lc_ctrl:	Parameter that controls weights of Chroma Homogeneity metric
922dc794d3dSSakari Ailus  *		in calculation of final homogeneity metric.
923dc794d3dSSakari Ailus  *		u5, range [0, 31], default 7.
924dc794d3dSSakari Ailus  * @reserved2:	reserved
925dc794d3dSSakari Ailus  * @cr_param1:	First parameter that defines Checker artifact removal
926dc794d3dSSakari Ailus  *		feature gain. Precision u5, range [0, 31], default 8.
927dc794d3dSSakari Ailus  * @reserved3:	reserved
928dc794d3dSSakari Ailus  * @cr_param2:	Second parameter that defines Checker artifact removal
929dc794d3dSSakari Ailus  *		feature gain. Precision u5, range [0, 31], default 8.
930dc794d3dSSakari Ailus  * @reserved4:	reserved
931dc794d3dSSakari Ailus  * @coring_param:	Defines power of false color correction operation.
932dc794d3dSSakari Ailus  *			low for preserving edge colors, high for preserving gray
933dc794d3dSSakari Ailus  *			edge artifacts.
934dc794d3dSSakari Ailus  *			Precision u1.4, range [0, 1.9375], default 4 (0.25).
935dc794d3dSSakari Ailus  * @reserved5:	reserved
936dc794d3dSSakari Ailus  *
937dc794d3dSSakari Ailus  * The demosaic fixed function block is responsible to covert Bayer(mosaiced)
938dc794d3dSSakari Ailus  * images into color images based on demosaicing algorithm.
939dc794d3dSSakari Ailus  */
940dc794d3dSSakari Ailus struct ipu3_uapi_dm_config {
941dc794d3dSSakari Ailus 	__u32 dm_en:1;
942dc794d3dSSakari Ailus 	__u32 ch_ar_en:1;
943dc794d3dSSakari Ailus 	__u32 fcc_en:1;
944dc794d3dSSakari Ailus 	__u32 reserved0:13;
945dc794d3dSSakari Ailus 	__u32 frame_width:16;
946dc794d3dSSakari Ailus 
947dc794d3dSSakari Ailus 	__u32 gamma_sc:5;
948dc794d3dSSakari Ailus 	__u32 reserved1:3;
949dc794d3dSSakari Ailus 	__u32 lc_ctrl:5;
950dc794d3dSSakari Ailus 	__u32 reserved2:3;
951dc794d3dSSakari Ailus 	__u32 cr_param1:5;
952dc794d3dSSakari Ailus 	__u32 reserved3:3;
953dc794d3dSSakari Ailus 	__u32 cr_param2:5;
954dc794d3dSSakari Ailus 	__u32 reserved4:3;
955dc794d3dSSakari Ailus 
956dc794d3dSSakari Ailus 	__u32 coring_param:5;
957dc794d3dSSakari Ailus 	__u32 reserved5:27;
958dc794d3dSSakari Ailus } __packed;
959dc794d3dSSakari Ailus 
960dc794d3dSSakari Ailus /**
961dc794d3dSSakari Ailus  * struct ipu3_uapi_ccm_mat_config - Color correction matrix
962dc794d3dSSakari Ailus  *
963dc794d3dSSakari Ailus  * @coeff_m11: CCM 3x3 coefficient, range [-65536, 65535]
964dc794d3dSSakari Ailus  * @coeff_m12: CCM 3x3 coefficient, range [-8192, 8191]
965dc794d3dSSakari Ailus  * @coeff_m13: CCM 3x3 coefficient, range [-32768, 32767]
966dc794d3dSSakari Ailus  * @coeff_o_r: Bias 3x1 coefficient, range [-8191, 8181]
967dc794d3dSSakari Ailus  * @coeff_m21: CCM 3x3 coefficient, range [-32767, 32767]
968dc794d3dSSakari Ailus  * @coeff_m22: CCM 3x3 coefficient, range [-8192, 8191]
969dc794d3dSSakari Ailus  * @coeff_m23: CCM 3x3 coefficient, range [-32768, 32767]
970dc794d3dSSakari Ailus  * @coeff_o_g: Bias 3x1 coefficient, range [-8191, 8181]
971dc794d3dSSakari Ailus  * @coeff_m31: CCM 3x3 coefficient, range [-32768, 32767]
972dc794d3dSSakari Ailus  * @coeff_m32: CCM 3x3 coefficient, range [-8192, 8191]
973dc794d3dSSakari Ailus  * @coeff_m33: CCM 3x3 coefficient, range [-32768, 32767]
974dc794d3dSSakari Ailus  * @coeff_o_b: Bias 3x1 coefficient, range [-8191, 8181]
975dc794d3dSSakari Ailus  *
976dc794d3dSSakari Ailus  * Transform sensor specific color space to standard sRGB by applying 3x3 matrix
977dc794d3dSSakari Ailus  * and adding a bias vector O. The transformation is basically a rotation and
978dc794d3dSSakari Ailus  * translation in the 3-dimensional color spaces. Here are the defaults:
979dc794d3dSSakari Ailus  *
980dc794d3dSSakari Ailus  *	9775,	-2671,	1087,	0
981dc794d3dSSakari Ailus  *	-1071,	8303,	815,	0
982dc794d3dSSakari Ailus  *	-23,	-7887,	16103,	0
983dc794d3dSSakari Ailus  */
984dc794d3dSSakari Ailus struct ipu3_uapi_ccm_mat_config {
985dc794d3dSSakari Ailus 	__s16 coeff_m11;
986dc794d3dSSakari Ailus 	__s16 coeff_m12;
987dc794d3dSSakari Ailus 	__s16 coeff_m13;
988dc794d3dSSakari Ailus 	__s16 coeff_o_r;
989dc794d3dSSakari Ailus 	__s16 coeff_m21;
990dc794d3dSSakari Ailus 	__s16 coeff_m22;
991dc794d3dSSakari Ailus 	__s16 coeff_m23;
992dc794d3dSSakari Ailus 	__s16 coeff_o_g;
993dc794d3dSSakari Ailus 	__s16 coeff_m31;
994dc794d3dSSakari Ailus 	__s16 coeff_m32;
995dc794d3dSSakari Ailus 	__s16 coeff_m33;
996dc794d3dSSakari Ailus 	__s16 coeff_o_b;
997dc794d3dSSakari Ailus } __packed;
998dc794d3dSSakari Ailus 
999dc794d3dSSakari Ailus /**
1000dc794d3dSSakari Ailus  * struct ipu3_uapi_gamma_corr_ctrl - Gamma correction
1001dc794d3dSSakari Ailus  *
1002dc794d3dSSakari Ailus  * @enable: gamma correction enable.
1003dc794d3dSSakari Ailus  * @reserved: reserved
1004dc794d3dSSakari Ailus  */
1005dc794d3dSSakari Ailus struct ipu3_uapi_gamma_corr_ctrl {
1006dc794d3dSSakari Ailus 	__u32 enable:1;
1007dc794d3dSSakari Ailus 	__u32 reserved:31;
1008dc794d3dSSakari Ailus } __packed;
1009dc794d3dSSakari Ailus 
1010dc794d3dSSakari Ailus /**
1011dc794d3dSSakari Ailus  * struct ipu3_uapi_gamma_corr_lut - Per-pixel tone mapping implemented as LUT.
1012dc794d3dSSakari Ailus  *
1013dc794d3dSSakari Ailus  * @lut:	256 tabulated values of the gamma function. LUT[1].. LUT[256]
1014dc794d3dSSakari Ailus  *		format u13.0, range [0, 8191].
1015dc794d3dSSakari Ailus  *
1016dc794d3dSSakari Ailus  * The tone mapping operation is done by a Piece wise linear graph
1017dc794d3dSSakari Ailus  * that is implemented as a lookup table(LUT). The pixel component input
1018dc794d3dSSakari Ailus  * intensity is the X-axis of the graph which is the table entry.
1019dc794d3dSSakari Ailus  */
1020dc794d3dSSakari Ailus struct ipu3_uapi_gamma_corr_lut {
1021dc794d3dSSakari Ailus 	__u16 lut[IPU3_UAPI_GAMMA_CORR_LUT_ENTRIES];
1022dc794d3dSSakari Ailus } __packed;
1023dc794d3dSSakari Ailus 
1024dc794d3dSSakari Ailus /**
1025dc794d3dSSakari Ailus  * struct ipu3_uapi_gamma_config - Gamma config
1026dc794d3dSSakari Ailus  *
1027dc794d3dSSakari Ailus  * @gc_ctrl: control of gamma correction &ipu3_uapi_gamma_corr_ctrl
1028dc794d3dSSakari Ailus  * @gc_lut: lookup table of gamma correction &ipu3_uapi_gamma_corr_lut
1029dc794d3dSSakari Ailus  */
1030dc794d3dSSakari Ailus struct ipu3_uapi_gamma_config {
1031dc794d3dSSakari Ailus 	struct ipu3_uapi_gamma_corr_ctrl gc_ctrl __attribute__((aligned(32)));
1032dc794d3dSSakari Ailus 	struct ipu3_uapi_gamma_corr_lut gc_lut __attribute__((aligned(32)));
1033dc794d3dSSakari Ailus } __packed;
1034dc794d3dSSakari Ailus 
1035dc794d3dSSakari Ailus /**
1036dc794d3dSSakari Ailus  * struct ipu3_uapi_csc_mat_config - Color space conversion matrix config
1037dc794d3dSSakari Ailus  *
1038dc794d3dSSakari Ailus  * @coeff_c11:	Conversion matrix value, format s0.14, range [-16384, 16383].
1039dc794d3dSSakari Ailus  * @coeff_c12:	Conversion matrix value, format s0.14, range [-8192, 8191].
1040dc794d3dSSakari Ailus  * @coeff_c13:	Conversion matrix value, format s0.14, range [-16384, 16383].
1041dc794d3dSSakari Ailus  * @coeff_b1:	Bias 3x1 coefficient, s13.0 range [-8192, 8191].
1042dc794d3dSSakari Ailus  * @coeff_c21:	Conversion matrix value, format s0.14, range [-16384, 16383].
1043dc794d3dSSakari Ailus  * @coeff_c22:	Conversion matrix value, format s0.14, range [-8192, 8191].
1044dc794d3dSSakari Ailus  * @coeff_c23:	Conversion matrix value, format s0.14, range [-16384, 16383].
1045dc794d3dSSakari Ailus  * @coeff_b2:	Bias 3x1 coefficient, s13.0 range [-8192, 8191].
1046dc794d3dSSakari Ailus  * @coeff_c31:	Conversion matrix value, format s0.14, range [-16384, 16383].
1047dc794d3dSSakari Ailus  * @coeff_c32:	Conversion matrix value, format s0.14, range [-8192, 8191].
1048dc794d3dSSakari Ailus  * @coeff_c33:	Conversion matrix value, format s0.14, range [-16384, 16383].
1049dc794d3dSSakari Ailus  * @coeff_b3:	Bias 3x1 coefficient, s13.0 range [-8192, 8191].
1050dc794d3dSSakari Ailus  *
1051dc794d3dSSakari Ailus  * To transform each pixel from RGB to YUV (Y - brightness/luminance,
1052dc794d3dSSakari Ailus  * UV -chroma) by applying the pixel's values by a 3x3 matrix and adding an
1053dc794d3dSSakari Ailus  * optional bias 3x1 vector. Here are the default values for the matrix:
1054dc794d3dSSakari Ailus  *
1055dc794d3dSSakari Ailus  *	4898,   9617,  1867, 0,
1056dc794d3dSSakari Ailus  *	-2410, -4732,  7143, 0,
1057dc794d3dSSakari Ailus  *	10076, -8437, -1638, 0,
1058dc794d3dSSakari Ailus  *
1059dc794d3dSSakari Ailus  *	(i.e. for real number 0.299, 0.299 * 2^14 becomes 4898.)
1060dc794d3dSSakari Ailus  */
1061dc794d3dSSakari Ailus struct ipu3_uapi_csc_mat_config {
1062dc794d3dSSakari Ailus 	__s16 coeff_c11;
1063dc794d3dSSakari Ailus 	__s16 coeff_c12;
1064dc794d3dSSakari Ailus 	__s16 coeff_c13;
1065dc794d3dSSakari Ailus 	__s16 coeff_b1;
1066dc794d3dSSakari Ailus 	__s16 coeff_c21;
1067dc794d3dSSakari Ailus 	__s16 coeff_c22;
1068dc794d3dSSakari Ailus 	__s16 coeff_c23;
1069dc794d3dSSakari Ailus 	__s16 coeff_b2;
1070dc794d3dSSakari Ailus 	__s16 coeff_c31;
1071dc794d3dSSakari Ailus 	__s16 coeff_c32;
1072dc794d3dSSakari Ailus 	__s16 coeff_c33;
1073dc794d3dSSakari Ailus 	__s16 coeff_b3;
1074dc794d3dSSakari Ailus } __packed;
1075dc794d3dSSakari Ailus 
1076dc794d3dSSakari Ailus /**
1077dc794d3dSSakari Ailus  * struct ipu3_uapi_cds_params - Chroma down-scaling
1078dc794d3dSSakari Ailus  *
1079dc794d3dSSakari Ailus  * @ds_c00:	range [0, 3]
1080dc794d3dSSakari Ailus  * @ds_c01:	range [0, 3]
1081dc794d3dSSakari Ailus  * @ds_c02:	range [0, 3]
1082dc794d3dSSakari Ailus  * @ds_c03:	range [0, 3]
1083dc794d3dSSakari Ailus  * @ds_c10:	range [0, 3]
1084dc794d3dSSakari Ailus  * @ds_c11:	range [0, 3]
1085dc794d3dSSakari Ailus  * @ds_c12:	range [0, 3]
1086dc794d3dSSakari Ailus  * @ds_c13:	range [0, 3]
1087dc794d3dSSakari Ailus  *
1088dc794d3dSSakari Ailus  * In case user does not provide, above 4x2 filter will use following defaults:
1089dc794d3dSSakari Ailus  *	1, 3, 3, 1,
1090dc794d3dSSakari Ailus  *	1, 3, 3, 1,
1091dc794d3dSSakari Ailus  *
1092dc794d3dSSakari Ailus  * @ds_nf:	Normalization factor for Chroma output downscaling filter,
1093dc794d3dSSakari Ailus  *		range 0,4, default 2.
1094dc794d3dSSakari Ailus  * @reserved0:	reserved
1095dc794d3dSSakari Ailus  * @csc_en:	Color space conversion enable
1096dc794d3dSSakari Ailus  * @uv_bin_output:	0: output YUV 4.2.0, 1: output YUV 4.2.2(default).
1097dc794d3dSSakari Ailus  * @reserved1:	reserved
1098dc794d3dSSakari Ailus  */
1099dc794d3dSSakari Ailus struct ipu3_uapi_cds_params {
1100dc794d3dSSakari Ailus 	__u32 ds_c00:2;
1101dc794d3dSSakari Ailus 	__u32 ds_c01:2;
1102dc794d3dSSakari Ailus 	__u32 ds_c02:2;
1103dc794d3dSSakari Ailus 	__u32 ds_c03:2;
1104dc794d3dSSakari Ailus 	__u32 ds_c10:2;
1105dc794d3dSSakari Ailus 	__u32 ds_c11:2;
1106dc794d3dSSakari Ailus 	__u32 ds_c12:2;
1107dc794d3dSSakari Ailus 	__u32 ds_c13:2;
1108dc794d3dSSakari Ailus 	__u32 ds_nf:5;
1109dc794d3dSSakari Ailus 	__u32 reserved0:3;
1110dc794d3dSSakari Ailus 	__u32 csc_en:1;
1111dc794d3dSSakari Ailus 	__u32 uv_bin_output:1;
1112dc794d3dSSakari Ailus 	__u32 reserved1:6;
1113dc794d3dSSakari Ailus } __packed;
1114dc794d3dSSakari Ailus 
1115dc794d3dSSakari Ailus /**
1116dc794d3dSSakari Ailus  * struct ipu3_uapi_shd_grid_config - Bayer shading(darkening) correction
1117dc794d3dSSakari Ailus  *
1118dc794d3dSSakari Ailus  * @width:	Grid horizontal dimensions, u8, [8, 128], default 73
1119dc794d3dSSakari Ailus  * @height:	Grid vertical dimensions, u8, [8, 128], default 56
1120dc794d3dSSakari Ailus  * @block_width_log2:	Log2 of the width of the grid cell in pixel count
1121dc794d3dSSakari Ailus  *			u4, [0, 15], default value 5.
1122dc794d3dSSakari Ailus  * @reserved0:	reserved
1123dc794d3dSSakari Ailus  * @block_height_log2:	Log2 of the height of the grid cell in pixel count
1124dc794d3dSSakari Ailus  *			u4, [0, 15], default value 6.
1125dc794d3dSSakari Ailus  * @reserved1:	reserved
1126dc794d3dSSakari Ailus  * @grid_height_per_slice:	SHD_MAX_CELLS_PER_SET/width.
1127dc794d3dSSakari Ailus  *				(with SHD_MAX_CELLS_PER_SET = 146).
1128dc794d3dSSakari Ailus  * @x_start:	X value of top left corner of sensor relative to ROI
1129dc794d3dSSakari Ailus  *		s13, [-4096, 0], default 0, only negative values.
1130dc794d3dSSakari Ailus  * @y_start:	Y value of top left corner of sensor relative to ROI
1131dc794d3dSSakari Ailus  *		s13, [-4096, 0], default 0, only negative values.
1132dc794d3dSSakari Ailus  */
1133dc794d3dSSakari Ailus struct ipu3_uapi_shd_grid_config {
1134dc794d3dSSakari Ailus 	/* reg 0 */
1135dc794d3dSSakari Ailus 	__u8 width;
1136dc794d3dSSakari Ailus 	__u8 height;
1137dc794d3dSSakari Ailus 	__u8 block_width_log2:3;
1138dc794d3dSSakari Ailus 	__u8 reserved0:1;
1139dc794d3dSSakari Ailus 	__u8 block_height_log2:3;
1140dc794d3dSSakari Ailus 	__u8 reserved1:1;
1141dc794d3dSSakari Ailus 	__u8 grid_height_per_slice;
1142dc794d3dSSakari Ailus 	/* reg 1 */
1143dc794d3dSSakari Ailus 	__s16 x_start;
1144dc794d3dSSakari Ailus 	__s16 y_start;
1145dc794d3dSSakari Ailus } __packed;
1146dc794d3dSSakari Ailus 
1147dc794d3dSSakari Ailus /**
1148dc794d3dSSakari Ailus  * struct ipu3_uapi_shd_general_config - Shading general config
1149dc794d3dSSakari Ailus  *
1150dc794d3dSSakari Ailus  * @init_set_vrt_offst_ul: set vertical offset,
1151dc794d3dSSakari Ailus  *			y_start >> block_height_log2 % grid_height_per_slice.
1152dc794d3dSSakari Ailus  * @shd_enable: shading enable.
1153dc794d3dSSakari Ailus  * @gain_factor: Gain factor. Shift calculated anti shading value. Precision u2.
1154dc794d3dSSakari Ailus  *		0x0 - gain factor [1, 5], means no shift interpolated value.
1155dc794d3dSSakari Ailus  *		0x1 - gain factor [1, 9], means shift interpolated by 1.
1156dc794d3dSSakari Ailus  *		0x2 - gain factor [1, 17], means shift interpolated by 2.
1157dc794d3dSSakari Ailus  * @reserved: reserved
1158dc794d3dSSakari Ailus  *
1159dc794d3dSSakari Ailus  * Correction is performed by multiplying a gain factor for each of the 4 Bayer
1160dc794d3dSSakari Ailus  * channels as a function of the pixel location in the sensor.
1161dc794d3dSSakari Ailus  */
1162dc794d3dSSakari Ailus struct ipu3_uapi_shd_general_config {
1163dc794d3dSSakari Ailus 	__u32 init_set_vrt_offst_ul:8;
1164dc794d3dSSakari Ailus 	__u32 shd_enable:1;
1165dc794d3dSSakari Ailus 	__u32 gain_factor:2;
1166dc794d3dSSakari Ailus 	__u32 reserved:21;
1167dc794d3dSSakari Ailus } __packed;
1168dc794d3dSSakari Ailus 
1169dc794d3dSSakari Ailus /**
1170dc794d3dSSakari Ailus  * struct ipu3_uapi_shd_black_level_config - Black level correction
1171dc794d3dSSakari Ailus  *
1172dc794d3dSSakari Ailus  * @bl_r:	Bios values for green red. s11 range [-2048, 2047].
1173dc794d3dSSakari Ailus  * @bl_gr:	Bios values for green blue. s11 range [-2048, 2047].
1174dc794d3dSSakari Ailus  * @bl_gb:	Bios values for red. s11 range [-2048, 2047].
1175dc794d3dSSakari Ailus  * @bl_b:	Bios values for blue. s11 range [-2048, 2047].
1176dc794d3dSSakari Ailus  */
1177dc794d3dSSakari Ailus struct ipu3_uapi_shd_black_level_config {
1178dc794d3dSSakari Ailus 	__s16 bl_r;
1179dc794d3dSSakari Ailus 	__s16 bl_gr;
1180dc794d3dSSakari Ailus 	__s16 bl_gb;
1181dc794d3dSSakari Ailus 	__s16 bl_b;
1182dc794d3dSSakari Ailus } __packed;
1183dc794d3dSSakari Ailus 
1184dc794d3dSSakari Ailus /**
1185dc794d3dSSakari Ailus  * struct ipu3_uapi_shd_config_static - Shading config static
1186dc794d3dSSakari Ailus  *
1187dc794d3dSSakari Ailus  * @grid:	shading grid config &ipu3_uapi_shd_grid_config
1188dc794d3dSSakari Ailus  * @general:	shading general config &ipu3_uapi_shd_general_config
1189dc794d3dSSakari Ailus  * @black_level:	black level config for shading correction as defined by
1190dc794d3dSSakari Ailus  *			&ipu3_uapi_shd_black_level_config
1191dc794d3dSSakari Ailus  */
1192dc794d3dSSakari Ailus struct ipu3_uapi_shd_config_static {
1193dc794d3dSSakari Ailus 	struct ipu3_uapi_shd_grid_config grid;
1194dc794d3dSSakari Ailus 	struct ipu3_uapi_shd_general_config general;
1195dc794d3dSSakari Ailus 	struct ipu3_uapi_shd_black_level_config black_level;
1196dc794d3dSSakari Ailus } __packed;
1197dc794d3dSSakari Ailus 
1198dc794d3dSSakari Ailus /**
1199dc794d3dSSakari Ailus  * struct ipu3_uapi_shd_lut - Shading gain factor lookup table.
1200dc794d3dSSakari Ailus  *
1201dc794d3dSSakari Ailus  * @sets: array
1202dc794d3dSSakari Ailus  * @sets.r_and_gr: Red and GreenR Lookup table.
1203dc794d3dSSakari Ailus  * @sets.r_and_gr.r: Red shading factor.
1204dc794d3dSSakari Ailus  * @sets.r_and_gr.gr: GreenR shading factor.
1205dc794d3dSSakari Ailus  * @sets.reserved1: reserved
1206dc794d3dSSakari Ailus  * @sets.gb_and_b: GreenB and Blue Lookup table.
1207dc794d3dSSakari Ailus  * @sets.gb_and_b.gb: GreenB shading factor.
1208dc794d3dSSakari Ailus  * @sets.gb_and_b.b: Blue shading factor.
1209dc794d3dSSakari Ailus  * @sets.reserved2: reserved
1210dc794d3dSSakari Ailus  *
1211dc794d3dSSakari Ailus  * Map to shading correction LUT register set.
1212dc794d3dSSakari Ailus  */
1213dc794d3dSSakari Ailus struct ipu3_uapi_shd_lut {
1214dc794d3dSSakari Ailus 	struct {
1215dc794d3dSSakari Ailus 		struct {
1216dc794d3dSSakari Ailus 			__u16 r;
1217dc794d3dSSakari Ailus 			__u16 gr;
1218dc794d3dSSakari Ailus 		} r_and_gr[IPU3_UAPI_SHD_MAX_CELLS_PER_SET];
1219dc794d3dSSakari Ailus 		__u8 reserved1[24];
1220dc794d3dSSakari Ailus 		struct {
1221dc794d3dSSakari Ailus 			__u16 gb;
1222dc794d3dSSakari Ailus 			__u16 b;
1223dc794d3dSSakari Ailus 		} gb_and_b[IPU3_UAPI_SHD_MAX_CELLS_PER_SET];
1224dc794d3dSSakari Ailus 		__u8 reserved2[24];
1225dc794d3dSSakari Ailus 	} sets[IPU3_UAPI_SHD_MAX_CFG_SETS];
1226dc794d3dSSakari Ailus } __packed;
1227dc794d3dSSakari Ailus 
1228dc794d3dSSakari Ailus /**
1229dc794d3dSSakari Ailus  * struct ipu3_uapi_shd_config - Shading config
1230dc794d3dSSakari Ailus  *
1231dc794d3dSSakari Ailus  * @shd:	shading static config, see &ipu3_uapi_shd_config_static
1232dc794d3dSSakari Ailus  * @shd_lut:	shading lookup table &ipu3_uapi_shd_lut
1233dc794d3dSSakari Ailus  */
1234dc794d3dSSakari Ailus struct ipu3_uapi_shd_config {
1235dc794d3dSSakari Ailus 	struct ipu3_uapi_shd_config_static shd __attribute__((aligned(32)));
1236dc794d3dSSakari Ailus 	struct ipu3_uapi_shd_lut shd_lut __attribute__((aligned(32)));
1237dc794d3dSSakari Ailus } __packed;
1238dc794d3dSSakari Ailus 
1239dc794d3dSSakari Ailus /* Image Enhancement Filter directed */
1240dc794d3dSSakari Ailus 
1241dc794d3dSSakari Ailus /**
1242dc794d3dSSakari Ailus  * struct ipu3_uapi_iefd_cux2 - IEFd Config Unit 2 parameters
1243dc794d3dSSakari Ailus  *
1244dc794d3dSSakari Ailus  * @x0:		X0 point of Config Unit, u9.0, default 0.
1245dc794d3dSSakari Ailus  * @x1:		X1 point of Config Unit, u9.0, default 0.
1246dc794d3dSSakari Ailus  * @a01:	Slope A of Config Unit, s4.4, default 0.
1247dc794d3dSSakari Ailus  * @b01:	Slope B, always 0.
1248dc794d3dSSakari Ailus  *
1249dc794d3dSSakari Ailus  * Calculate weight for blending directed and non-directed denoise elements
1250dc794d3dSSakari Ailus  *
1251dc794d3dSSakari Ailus  * Note:
1252dc794d3dSSakari Ailus  * Each instance of Config Unit needs X coordinate of n points and
1253dc794d3dSSakari Ailus  * slope A factor between points calculated by driver based on calibration
1254dc794d3dSSakari Ailus  * parameters.
1255dc794d3dSSakari Ailus  *
1256dc794d3dSSakari Ailus  * All CU inputs are unsigned, they will be converted to signed when written
1257dc794d3dSSakari Ailus  * to register, i.e. a01 will be written to 9 bit register in s4.4 format.
1258dc794d3dSSakari Ailus  * The data precision s4.4 means 4 bits for integer parts and 4 bits for the
1259dc794d3dSSakari Ailus  * fractional part, the first bit indicates positive or negative value.
1260dc794d3dSSakari Ailus  * For userspace software (commonly the imaging library), the computation for
1261dc794d3dSSakari Ailus  * the CU slope values should be based on the slope resolution 1/16 (binary
1262dc794d3dSSakari Ailus  * 0.0001 - the minimal interval value), the slope value range is [-256, +255].
1263dc794d3dSSakari Ailus  * This applies to &ipu3_uapi_iefd_cux6_ed, &ipu3_uapi_iefd_cux2_1,
1264dc794d3dSSakari Ailus  * &ipu3_uapi_iefd_cux2_1, &ipu3_uapi_iefd_cux4 and &ipu3_uapi_iefd_cux6_rad.
1265dc794d3dSSakari Ailus  */
1266dc794d3dSSakari Ailus struct ipu3_uapi_iefd_cux2 {
1267dc794d3dSSakari Ailus 	__u32 x0:9;
1268dc794d3dSSakari Ailus 	__u32 x1:9;
1269dc794d3dSSakari Ailus 	__u32 a01:9;
1270dc794d3dSSakari Ailus 	__u32 b01:5;
1271dc794d3dSSakari Ailus } __packed;
1272dc794d3dSSakari Ailus 
1273dc794d3dSSakari Ailus /**
1274dc794d3dSSakari Ailus  * struct ipu3_uapi_iefd_cux6_ed - Calculate power of non-directed sharpening
1275dc794d3dSSakari Ailus  *				   element, Config Unit 6 for edge detail (ED).
1276dc794d3dSSakari Ailus  *
1277dc794d3dSSakari Ailus  * @x0:	X coordinate of point 0, u9.0, default 0.
1278dc794d3dSSakari Ailus  * @x1:	X coordinate of point 1, u9.0, default 0.
1279dc794d3dSSakari Ailus  * @x2:	X coordinate of point 2, u9.0, default 0.
1280dc794d3dSSakari Ailus  * @reserved0:	reserved
1281dc794d3dSSakari Ailus  * @x3:	X coordinate of point 3, u9.0, default 0.
1282dc794d3dSSakari Ailus  * @x4:	X coordinate of point 4, u9.0, default 0.
1283dc794d3dSSakari Ailus  * @x5:	X coordinate of point 5, u9.0, default 0.
1284dc794d3dSSakari Ailus  * @reserved1:	reserved
1285dc794d3dSSakari Ailus  * @a01:	slope A points 01, s4.4, default 0.
1286dc794d3dSSakari Ailus  * @a12:	slope A points 12, s4.4, default 0.
1287dc794d3dSSakari Ailus  * @a23:	slope A points 23, s4.4, default 0.
1288dc794d3dSSakari Ailus  * @reserved2:	reserved
1289dc794d3dSSakari Ailus  * @a34:	slope A points 34, s4.4, default 0.
1290dc794d3dSSakari Ailus  * @a45:	slope A points 45, s4.4, default 0.
1291dc794d3dSSakari Ailus  * @reserved3:	reserved
1292dc794d3dSSakari Ailus  * @b01:	slope B points 01, s4.4, default 0.
1293dc794d3dSSakari Ailus  * @b12:	slope B points 12, s4.4, default 0.
1294dc794d3dSSakari Ailus  * @b23:	slope B points 23, s4.4, default 0.
1295dc794d3dSSakari Ailus  * @reserved4:	reserved
1296dc794d3dSSakari Ailus  * @b34:	slope B points 34, s4.4, default 0.
1297dc794d3dSSakari Ailus  * @b45:	slope B points 45, s4.4, default 0.
1298dc794d3dSSakari Ailus  * @reserved5:	reserved.
1299dc794d3dSSakari Ailus  */
1300dc794d3dSSakari Ailus struct ipu3_uapi_iefd_cux6_ed {
1301dc794d3dSSakari Ailus 	__u32 x0:9;
1302dc794d3dSSakari Ailus 	__u32 x1:9;
1303dc794d3dSSakari Ailus 	__u32 x2:9;
1304dc794d3dSSakari Ailus 	__u32 reserved0:5;
1305dc794d3dSSakari Ailus 
1306dc794d3dSSakari Ailus 	__u32 x3:9;
1307dc794d3dSSakari Ailus 	__u32 x4:9;
1308dc794d3dSSakari Ailus 	__u32 x5:9;
1309dc794d3dSSakari Ailus 	__u32 reserved1:5;
1310dc794d3dSSakari Ailus 
1311dc794d3dSSakari Ailus 	__u32 a01:9;
1312dc794d3dSSakari Ailus 	__u32 a12:9;
1313dc794d3dSSakari Ailus 	__u32 a23:9;
1314dc794d3dSSakari Ailus 	__u32 reserved2:5;
1315dc794d3dSSakari Ailus 
1316dc794d3dSSakari Ailus 	__u32 a34:9;
1317dc794d3dSSakari Ailus 	__u32 a45:9;
1318dc794d3dSSakari Ailus 	__u32 reserved3:14;
1319dc794d3dSSakari Ailus 
1320dc794d3dSSakari Ailus 	__u32 b01:9;
1321dc794d3dSSakari Ailus 	__u32 b12:9;
1322dc794d3dSSakari Ailus 	__u32 b23:9;
1323dc794d3dSSakari Ailus 	__u32 reserved4:5;
1324dc794d3dSSakari Ailus 
1325dc794d3dSSakari Ailus 	__u32 b34:9;
1326dc794d3dSSakari Ailus 	__u32 b45:9;
1327dc794d3dSSakari Ailus 	__u32 reserved5:14;
1328dc794d3dSSakari Ailus } __packed;
1329dc794d3dSSakari Ailus 
1330dc794d3dSSakari Ailus /**
1331dc794d3dSSakari Ailus  * struct ipu3_uapi_iefd_cux2_1 - Calculate power of non-directed denoise
1332dc794d3dSSakari Ailus  *				  element apply.
1333dc794d3dSSakari Ailus  * @x0: X0 point of Config Unit, u9.0, default 0.
1334dc794d3dSSakari Ailus  * @x1: X1 point of Config Unit, u9.0, default 0.
1335dc794d3dSSakari Ailus  * @a01: Slope A of Config Unit, s4.4, default 0.
1336dc794d3dSSakari Ailus  * @reserved1: reserved
1337dc794d3dSSakari Ailus  * @b01: offset B0 of Config Unit, u7.0, default 0.
1338dc794d3dSSakari Ailus  * @reserved2: reserved
1339dc794d3dSSakari Ailus  */
1340dc794d3dSSakari Ailus struct ipu3_uapi_iefd_cux2_1 {
1341dc794d3dSSakari Ailus 	__u32 x0:9;
1342dc794d3dSSakari Ailus 	__u32 x1:9;
1343dc794d3dSSakari Ailus 	__u32 a01:9;
1344dc794d3dSSakari Ailus 	__u32 reserved1:5;
1345dc794d3dSSakari Ailus 
1346dc794d3dSSakari Ailus 	__u32 b01:8;
1347dc794d3dSSakari Ailus 	__u32 reserved2:24;
1348dc794d3dSSakari Ailus } __packed;
1349dc794d3dSSakari Ailus 
1350dc794d3dSSakari Ailus /**
1351dc794d3dSSakari Ailus  * struct ipu3_uapi_iefd_cux4 - Calculate power of non-directed sharpening
1352dc794d3dSSakari Ailus  *				element.
1353dc794d3dSSakari Ailus  *
1354dc794d3dSSakari Ailus  * @x0:	X0 point of Config Unit, u9.0, default 0.
1355dc794d3dSSakari Ailus  * @x1:	X1 point of Config Unit, u9.0, default 0.
1356dc794d3dSSakari Ailus  * @x2:	X2 point of Config Unit, u9.0, default 0.
1357dc794d3dSSakari Ailus  * @reserved0:	reserved
1358dc794d3dSSakari Ailus  * @x3:	X3 point of Config Unit, u9.0, default 0.
1359dc794d3dSSakari Ailus  * @a01:	Slope A0 of Config Unit, s4.4, default 0.
1360dc794d3dSSakari Ailus  * @a12:	Slope A1 of Config Unit, s4.4, default 0.
1361dc794d3dSSakari Ailus  * @reserved1:	reserved
1362dc794d3dSSakari Ailus  * @a23:	Slope A2 of Config Unit, s4.4, default 0.
1363dc794d3dSSakari Ailus  * @b01:	Offset B0 of Config Unit, s7.0, default 0.
1364dc794d3dSSakari Ailus  * @b12:	Offset B1 of Config Unit, s7.0, default 0.
1365dc794d3dSSakari Ailus  * @reserved2:	reserved
1366dc794d3dSSakari Ailus  * @b23:	Offset B2 of Config Unit, s7.0, default 0.
1367dc794d3dSSakari Ailus  * @reserved3: reserved
1368dc794d3dSSakari Ailus  */
1369dc794d3dSSakari Ailus struct ipu3_uapi_iefd_cux4 {
1370dc794d3dSSakari Ailus 	__u32 x0:9;
1371dc794d3dSSakari Ailus 	__u32 x1:9;
1372dc794d3dSSakari Ailus 	__u32 x2:9;
1373dc794d3dSSakari Ailus 	__u32 reserved0:5;
1374dc794d3dSSakari Ailus 
1375dc794d3dSSakari Ailus 	__u32 x3:9;
1376dc794d3dSSakari Ailus 	__u32 a01:9;
1377dc794d3dSSakari Ailus 	__u32 a12:9;
1378dc794d3dSSakari Ailus 	__u32 reserved1:5;
1379dc794d3dSSakari Ailus 
1380dc794d3dSSakari Ailus 	__u32 a23:9;
1381dc794d3dSSakari Ailus 	__u32 b01:8;
1382dc794d3dSSakari Ailus 	__u32 b12:8;
1383dc794d3dSSakari Ailus 	__u32 reserved2:7;
1384dc794d3dSSakari Ailus 
1385dc794d3dSSakari Ailus 	__u32 b23:8;
1386dc794d3dSSakari Ailus 	__u32 reserved3:24;
1387dc794d3dSSakari Ailus } __packed;
1388dc794d3dSSakari Ailus 
1389dc794d3dSSakari Ailus /**
1390dc794d3dSSakari Ailus  * struct ipu3_uapi_iefd_cux6_rad - Radial Config Unit (CU)
1391dc794d3dSSakari Ailus  *
1392dc794d3dSSakari Ailus  * @x0:	x0 points of Config Unit radial, u8.0
1393dc794d3dSSakari Ailus  * @x1:	x1 points of Config Unit radial, u8.0
1394dc794d3dSSakari Ailus  * @x2:	x2 points of Config Unit radial, u8.0
1395dc794d3dSSakari Ailus  * @x3:	x3 points of Config Unit radial, u8.0
1396dc794d3dSSakari Ailus  * @x4:	x4 points of Config Unit radial, u8.0
1397dc794d3dSSakari Ailus  * @x5:	x5 points of Config Unit radial, u8.0
1398dc794d3dSSakari Ailus  * @reserved1: reserved
1399dc794d3dSSakari Ailus  * @a01:	Slope A of Config Unit radial, s7.8
1400dc794d3dSSakari Ailus  * @a12:	Slope A of Config Unit radial, s7.8
1401dc794d3dSSakari Ailus  * @a23:	Slope A of Config Unit radial, s7.8
1402dc794d3dSSakari Ailus  * @a34:	Slope A of Config Unit radial, s7.8
1403dc794d3dSSakari Ailus  * @a45:	Slope A of Config Unit radial, s7.8
1404dc794d3dSSakari Ailus  * @reserved2: reserved
1405dc794d3dSSakari Ailus  * @b01:	Slope B of Config Unit radial, s9.0
1406dc794d3dSSakari Ailus  * @b12:	Slope B of Config Unit radial, s9.0
1407dc794d3dSSakari Ailus  * @b23:	Slope B of Config Unit radial, s9.0
1408dc794d3dSSakari Ailus  * @reserved4: reserved
1409dc794d3dSSakari Ailus  * @b34:	Slope B of Config Unit radial, s9.0
1410dc794d3dSSakari Ailus  * @b45:	Slope B of Config Unit radial, s9.0
1411dc794d3dSSakari Ailus  * @reserved5: reserved
1412dc794d3dSSakari Ailus  */
1413dc794d3dSSakari Ailus struct ipu3_uapi_iefd_cux6_rad {
1414dc794d3dSSakari Ailus 	__u32 x0:8;
1415dc794d3dSSakari Ailus 	__u32 x1:8;
1416dc794d3dSSakari Ailus 	__u32 x2:8;
1417dc794d3dSSakari Ailus 	__u32 x3:8;
1418dc794d3dSSakari Ailus 
1419dc794d3dSSakari Ailus 	__u32 x4:8;
1420dc794d3dSSakari Ailus 	__u32 x5:8;
1421dc794d3dSSakari Ailus 	__u32 reserved1:16;
1422dc794d3dSSakari Ailus 
1423dc794d3dSSakari Ailus 	__u32 a01:16;
1424dc794d3dSSakari Ailus 	__u32 a12:16;
1425dc794d3dSSakari Ailus 
1426dc794d3dSSakari Ailus 	__u32 a23:16;
1427dc794d3dSSakari Ailus 	__u32 a34:16;
1428dc794d3dSSakari Ailus 
1429dc794d3dSSakari Ailus 	__u32 a45:16;
1430dc794d3dSSakari Ailus 	__u32 reserved2:16;
1431dc794d3dSSakari Ailus 
1432dc794d3dSSakari Ailus 	__u32 b01:10;
1433dc794d3dSSakari Ailus 	__u32 b12:10;
1434dc794d3dSSakari Ailus 	__u32 b23:10;
1435dc794d3dSSakari Ailus 	__u32 reserved4:2;
1436dc794d3dSSakari Ailus 
1437dc794d3dSSakari Ailus 	__u32 b34:10;
1438dc794d3dSSakari Ailus 	__u32 b45:10;
1439dc794d3dSSakari Ailus 	__u32 reserved5:12;
1440dc794d3dSSakari Ailus } __packed;
1441dc794d3dSSakari Ailus 
1442dc794d3dSSakari Ailus /**
1443dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_iefd_cfg_units - IEFd Config Units parameters
1444dc794d3dSSakari Ailus  *
1445dc794d3dSSakari Ailus  * @cu_1: calculate weight for blending directed and
1446dc794d3dSSakari Ailus  *	  non-directed denoise elements. See &ipu3_uapi_iefd_cux2
1447dc794d3dSSakari Ailus  * @cu_ed: calculate power of non-directed sharpening element, see
1448dc794d3dSSakari Ailus  *	   &ipu3_uapi_iefd_cux6_ed
1449dc794d3dSSakari Ailus  * @cu_3: calculate weight for blending directed and
1450dc794d3dSSakari Ailus  *	  non-directed denoise elements. A &ipu3_uapi_iefd_cux2
1451dc794d3dSSakari Ailus  * @cu_5: calculate power of non-directed denoise element apply, use
1452dc794d3dSSakari Ailus  *	  &ipu3_uapi_iefd_cux2_1
1453dc794d3dSSakari Ailus  * @cu_6: calculate power of non-directed sharpening element. See
1454dc794d3dSSakari Ailus  *	  &ipu3_uapi_iefd_cux4
1455dc794d3dSSakari Ailus  * @cu_7: calculate weight for blending directed and
1456dc794d3dSSakari Ailus  *	  non-directed denoise elements. Use &ipu3_uapi_iefd_cux2
1457dc794d3dSSakari Ailus  * @cu_unsharp: Config Unit of unsharp &ipu3_uapi_iefd_cux4
1458dc794d3dSSakari Ailus  * @cu_radial: Config Unit of radial &ipu3_uapi_iefd_cux6_rad
1459dc794d3dSSakari Ailus  * @cu_vssnlm: Config Unit of vssnlm &ipu3_uapi_iefd_cux2
1460dc794d3dSSakari Ailus  */
1461dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_iefd_cfg_units {
1462dc794d3dSSakari Ailus 	struct ipu3_uapi_iefd_cux2 cu_1;
1463dc794d3dSSakari Ailus 	struct ipu3_uapi_iefd_cux6_ed cu_ed;
1464dc794d3dSSakari Ailus 	struct ipu3_uapi_iefd_cux2 cu_3;
1465dc794d3dSSakari Ailus 	struct ipu3_uapi_iefd_cux2_1 cu_5;
1466dc794d3dSSakari Ailus 	struct ipu3_uapi_iefd_cux4 cu_6;
1467dc794d3dSSakari Ailus 	struct ipu3_uapi_iefd_cux2 cu_7;
1468dc794d3dSSakari Ailus 	struct ipu3_uapi_iefd_cux4 cu_unsharp;
1469dc794d3dSSakari Ailus 	struct ipu3_uapi_iefd_cux6_rad cu_radial;
1470dc794d3dSSakari Ailus 	struct ipu3_uapi_iefd_cux2 cu_vssnlm;
1471dc794d3dSSakari Ailus } __packed;
1472dc794d3dSSakari Ailus 
1473dc794d3dSSakari Ailus /**
1474dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_iefd_config_s - IEFd config
1475dc794d3dSSakari Ailus  *
1476dc794d3dSSakari Ailus  * @horver_diag_coeff: Gradient compensation. Compared with vertical /
1477dc794d3dSSakari Ailus  *		       horizontal (0 / 90 degree), coefficient of diagonal (45 /
1478dc794d3dSSakari Ailus  *		       135 degree) direction should be corrected by approx.
1479dc794d3dSSakari Ailus  *		       1/sqrt(2).
1480dc794d3dSSakari Ailus  * @reserved0: reserved
1481dc794d3dSSakari Ailus  * @clamp_stitch: Slope to stitch between clamped and unclamped edge values
1482dc794d3dSSakari Ailus  * @reserved1: reserved
1483dc794d3dSSakari Ailus  * @direct_metric_update: Update coeff for direction metric
1484dc794d3dSSakari Ailus  * @reserved2: reserved
1485dc794d3dSSakari Ailus  * @ed_horver_diag_coeff: Radial Coefficient that compensates for
1486dc794d3dSSakari Ailus  *			  different distance for vertical/horizontal and
1487dc794d3dSSakari Ailus  *			  diagonal gradient calculation (approx. 1/sqrt(2))
1488dc794d3dSSakari Ailus  * @reserved3: reserved
1489dc794d3dSSakari Ailus  */
1490dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_iefd_config_s {
1491dc794d3dSSakari Ailus 	__u32 horver_diag_coeff:7;
1492dc794d3dSSakari Ailus 	__u32 reserved0:1;
1493dc794d3dSSakari Ailus 	__u32 clamp_stitch:6;
1494dc794d3dSSakari Ailus 	__u32 reserved1:2;
1495dc794d3dSSakari Ailus 	__u32 direct_metric_update:5;
1496dc794d3dSSakari Ailus 	__u32 reserved2:3;
1497dc794d3dSSakari Ailus 	__u32 ed_horver_diag_coeff:7;
1498dc794d3dSSakari Ailus 	__u32 reserved3:1;
1499dc794d3dSSakari Ailus } __packed;
1500dc794d3dSSakari Ailus 
1501dc794d3dSSakari Ailus /**
1502dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_iefd_control - IEFd control
1503dc794d3dSSakari Ailus  *
1504dc794d3dSSakari Ailus  * @iefd_en:	Enable IEFd
1505dc794d3dSSakari Ailus  * @denoise_en:	Enable denoise
1506dc794d3dSSakari Ailus  * @direct_smooth_en:	Enable directional smooth
1507dc794d3dSSakari Ailus  * @rad_en:	Enable radial update
1508dc794d3dSSakari Ailus  * @vssnlm_en:	Enable VSSNLM output filter
1509dc794d3dSSakari Ailus  * @reserved:	reserved
1510dc794d3dSSakari Ailus  */
1511dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_iefd_control {
1512dc794d3dSSakari Ailus 	__u32 iefd_en:1;
1513dc794d3dSSakari Ailus 	__u32 denoise_en:1;
1514dc794d3dSSakari Ailus 	__u32 direct_smooth_en:1;
1515dc794d3dSSakari Ailus 	__u32 rad_en:1;
1516dc794d3dSSakari Ailus 	__u32 vssnlm_en:1;
1517dc794d3dSSakari Ailus 	__u32 reserved:27;
1518dc794d3dSSakari Ailus } __packed;
1519dc794d3dSSakari Ailus 
1520dc794d3dSSakari Ailus /**
1521dc794d3dSSakari Ailus  * struct ipu3_uapi_sharp_cfg - Sharpening config
1522dc794d3dSSakari Ailus  *
1523dc794d3dSSakari Ailus  * @nega_lmt_txt: Sharpening limit for negative overshoots for texture.
1524dc794d3dSSakari Ailus  * @reserved0: reserved
1525dc794d3dSSakari Ailus  * @posi_lmt_txt: Sharpening limit for positive overshoots for texture.
1526dc794d3dSSakari Ailus  * @reserved1: reserved
1527dc794d3dSSakari Ailus  * @nega_lmt_dir: Sharpening limit for negative overshoots for direction (edge).
1528dc794d3dSSakari Ailus  * @reserved2: reserved
1529dc794d3dSSakari Ailus  * @posi_lmt_dir: Sharpening limit for positive overshoots for direction (edge).
1530dc794d3dSSakari Ailus  * @reserved3: reserved
1531dc794d3dSSakari Ailus  *
1532dc794d3dSSakari Ailus  * Fixed point type u13.0, range [0, 8191].
1533dc794d3dSSakari Ailus  */
1534dc794d3dSSakari Ailus struct ipu3_uapi_sharp_cfg {
1535dc794d3dSSakari Ailus 	__u32 nega_lmt_txt:13;
1536dc794d3dSSakari Ailus 	__u32 reserved0:19;
1537dc794d3dSSakari Ailus 	__u32 posi_lmt_txt:13;
1538dc794d3dSSakari Ailus 	__u32 reserved1:19;
1539dc794d3dSSakari Ailus 	__u32 nega_lmt_dir:13;
1540dc794d3dSSakari Ailus 	__u32 reserved2:19;
1541dc794d3dSSakari Ailus 	__u32 posi_lmt_dir:13;
1542dc794d3dSSakari Ailus 	__u32 reserved3:19;
1543dc794d3dSSakari Ailus } __packed;
1544dc794d3dSSakari Ailus 
1545dc794d3dSSakari Ailus /**
1546dc794d3dSSakari Ailus  * struct ipu3_uapi_far_w - Sharpening config for far sub-group
1547dc794d3dSSakari Ailus  *
1548dc794d3dSSakari Ailus  * @dir_shrp:	Weight of wide direct sharpening, u1.6, range [0, 64], default 64.
1549dc794d3dSSakari Ailus  * @reserved0:	reserved
1550dc794d3dSSakari Ailus  * @dir_dns:	Weight of wide direct denoising, u1.6, range [0, 64], default 0.
1551dc794d3dSSakari Ailus  * @reserved1:	reserved
1552dc794d3dSSakari Ailus  * @ndir_dns_powr:	Power of non-direct denoising,
1553dc794d3dSSakari Ailus  *			Precision u1.6, range [0, 64], default 64.
1554dc794d3dSSakari Ailus  * @reserved2:	reserved
1555dc794d3dSSakari Ailus  */
1556dc794d3dSSakari Ailus struct ipu3_uapi_far_w {
1557dc794d3dSSakari Ailus 	__u32 dir_shrp:7;
1558dc794d3dSSakari Ailus 	__u32 reserved0:1;
1559dc794d3dSSakari Ailus 	__u32 dir_dns:7;
1560dc794d3dSSakari Ailus 	__u32 reserved1:1;
1561dc794d3dSSakari Ailus 	__u32 ndir_dns_powr:7;
1562dc794d3dSSakari Ailus 	__u32 reserved2:9;
1563dc794d3dSSakari Ailus } __packed;
1564dc794d3dSSakari Ailus 
1565dc794d3dSSakari Ailus /**
1566dc794d3dSSakari Ailus  * struct ipu3_uapi_unsharp_cfg - Unsharp config
1567dc794d3dSSakari Ailus  *
1568dc794d3dSSakari Ailus  * @unsharp_weight: Unsharp mask blending weight.
1569dc794d3dSSakari Ailus  *		    u1.6, range [0, 64], default 16.
1570dc794d3dSSakari Ailus  *		    0 - disabled, 64 - use only unsharp.
1571dc794d3dSSakari Ailus  * @reserved0: reserved
1572dc794d3dSSakari Ailus  * @unsharp_amount: Unsharp mask amount, u4.5, range [0, 511], default 0.
1573dc794d3dSSakari Ailus  * @reserved1: reserved
1574dc794d3dSSakari Ailus  */
1575dc794d3dSSakari Ailus struct ipu3_uapi_unsharp_cfg {
1576dc794d3dSSakari Ailus 	__u32 unsharp_weight:7;
1577dc794d3dSSakari Ailus 	__u32 reserved0:1;
1578dc794d3dSSakari Ailus 	__u32 unsharp_amount:9;
1579dc794d3dSSakari Ailus 	__u32 reserved1:15;
1580dc794d3dSSakari Ailus } __packed;
1581dc794d3dSSakari Ailus 
1582dc794d3dSSakari Ailus /**
1583dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_iefd_shrp_cfg - IEFd sharpness config
1584dc794d3dSSakari Ailus  *
1585dc794d3dSSakari Ailus  * @cfg: sharpness config &ipu3_uapi_sharp_cfg
1586dc794d3dSSakari Ailus  * @far_w: wide range config, value as specified by &ipu3_uapi_far_w:
1587dc794d3dSSakari Ailus  *	The 5x5 environment is separated into 2 sub-groups, the 3x3 nearest
1588dc794d3dSSakari Ailus  *	neighbors (8 pixels called Near), and the second order neighborhood
1589dc794d3dSSakari Ailus  *	around them (16 pixels called Far).
1590dc794d3dSSakari Ailus  * @unshrp_cfg: unsharpness config. &ipu3_uapi_unsharp_cfg
1591dc794d3dSSakari Ailus  */
1592dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_iefd_shrp_cfg {
1593dc794d3dSSakari Ailus 	struct ipu3_uapi_sharp_cfg cfg;
1594dc794d3dSSakari Ailus 	struct ipu3_uapi_far_w far_w;
1595dc794d3dSSakari Ailus 	struct ipu3_uapi_unsharp_cfg unshrp_cfg;
1596dc794d3dSSakari Ailus } __packed;
1597dc794d3dSSakari Ailus 
1598dc794d3dSSakari Ailus /**
1599dc794d3dSSakari Ailus  * struct ipu3_uapi_unsharp_coef0 - Unsharp mask coefficients
1600dc794d3dSSakari Ailus  *
1601dc794d3dSSakari Ailus  * @c00: Coeff11, s0.8, range [-255, 255], default 1.
1602dc794d3dSSakari Ailus  * @c01: Coeff12, s0.8, range [-255, 255], default 5.
1603dc794d3dSSakari Ailus  * @c02: Coeff13, s0.8, range [-255, 255], default 9.
1604dc794d3dSSakari Ailus  * @reserved: reserved
1605dc794d3dSSakari Ailus  *
1606dc794d3dSSakari Ailus  * Configurable registers for common sharpening support.
1607dc794d3dSSakari Ailus  */
1608dc794d3dSSakari Ailus struct ipu3_uapi_unsharp_coef0 {
1609dc794d3dSSakari Ailus 	__u32 c00:9;
1610dc794d3dSSakari Ailus 	__u32 c01:9;
1611dc794d3dSSakari Ailus 	__u32 c02:9;
1612dc794d3dSSakari Ailus 	__u32 reserved:5;
1613dc794d3dSSakari Ailus } __packed;
1614dc794d3dSSakari Ailus 
1615dc794d3dSSakari Ailus /**
1616dc794d3dSSakari Ailus  * struct ipu3_uapi_unsharp_coef1 - Unsharp mask coefficients
1617dc794d3dSSakari Ailus  *
1618dc794d3dSSakari Ailus  * @c11: Coeff22, s0.8, range [-255, 255], default 29.
1619dc794d3dSSakari Ailus  * @c12: Coeff23, s0.8, range [-255, 255], default 55.
1620dc794d3dSSakari Ailus  * @c22: Coeff33, s0.8, range [-255, 255], default 96.
1621dc794d3dSSakari Ailus  * @reserved: reserved
1622dc794d3dSSakari Ailus  */
1623dc794d3dSSakari Ailus struct ipu3_uapi_unsharp_coef1 {
1624dc794d3dSSakari Ailus 	__u32 c11:9;
1625dc794d3dSSakari Ailus 	__u32 c12:9;
1626dc794d3dSSakari Ailus 	__u32 c22:9;
1627dc794d3dSSakari Ailus 	__u32 reserved:5;
1628dc794d3dSSakari Ailus } __packed;
1629dc794d3dSSakari Ailus 
1630dc794d3dSSakari Ailus /**
1631dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_iefd_unshrp_cfg - Unsharp mask config
1632dc794d3dSSakari Ailus  *
1633dc794d3dSSakari Ailus  * @unsharp_coef0: unsharp coefficient 0 config. See &ipu3_uapi_unsharp_coef0
1634dc794d3dSSakari Ailus  * @unsharp_coef1: unsharp coefficient 1 config. See &ipu3_uapi_unsharp_coef1
1635dc794d3dSSakari Ailus  */
1636dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_iefd_unshrp_cfg {
1637dc794d3dSSakari Ailus 	struct ipu3_uapi_unsharp_coef0 unsharp_coef0;
1638dc794d3dSSakari Ailus 	struct ipu3_uapi_unsharp_coef1 unsharp_coef1;
1639dc794d3dSSakari Ailus } __packed;
1640dc794d3dSSakari Ailus 
1641dc794d3dSSakari Ailus /**
1642dc794d3dSSakari Ailus  * struct ipu3_uapi_radial_reset_xy - Radial coordinate reset
1643dc794d3dSSakari Ailus  *
1644dc794d3dSSakari Ailus  * @x:	Radial reset of x coordinate. Precision s12, [-4095, 4095], default 0.
1645dc794d3dSSakari Ailus  * @reserved0:	reserved
1646dc794d3dSSakari Ailus  * @y:	Radial center y coordinate. Precision s12, [-4095, 4095], default 0.
1647dc794d3dSSakari Ailus  * @reserved1:	reserved
1648dc794d3dSSakari Ailus  */
1649dc794d3dSSakari Ailus struct ipu3_uapi_radial_reset_xy {
1650dc794d3dSSakari Ailus 	__s32 x:13;
1651dc794d3dSSakari Ailus 	__u32 reserved0:3;
1652dc794d3dSSakari Ailus 	__s32 y:13;
1653dc794d3dSSakari Ailus 	__u32 reserved1:3;
1654dc794d3dSSakari Ailus } __packed;
1655dc794d3dSSakari Ailus 
1656dc794d3dSSakari Ailus /**
1657dc794d3dSSakari Ailus  * struct ipu3_uapi_radial_reset_x2 - Radial X^2 reset
1658dc794d3dSSakari Ailus  *
1659dc794d3dSSakari Ailus  * @x2:	Radial reset of x^2 coordinate. Precision u24, default 0.
1660dc794d3dSSakari Ailus  * @reserved:	reserved
1661dc794d3dSSakari Ailus  */
1662dc794d3dSSakari Ailus struct ipu3_uapi_radial_reset_x2 {
1663dc794d3dSSakari Ailus 	__u32 x2:24;
1664dc794d3dSSakari Ailus 	__u32 reserved:8;
1665dc794d3dSSakari Ailus } __packed;
1666dc794d3dSSakari Ailus 
1667dc794d3dSSakari Ailus /**
1668dc794d3dSSakari Ailus  * struct ipu3_uapi_radial_reset_y2 - Radial Y^2 reset
1669dc794d3dSSakari Ailus  *
1670dc794d3dSSakari Ailus  * @y2:	Radial reset of y^2 coordinate. Precision u24, default 0.
1671dc794d3dSSakari Ailus  * @reserved:	reserved
1672dc794d3dSSakari Ailus  */
1673dc794d3dSSakari Ailus struct ipu3_uapi_radial_reset_y2 {
1674dc794d3dSSakari Ailus 	__u32 y2:24;
1675dc794d3dSSakari Ailus 	__u32 reserved:8;
1676dc794d3dSSakari Ailus } __packed;
1677dc794d3dSSakari Ailus 
1678dc794d3dSSakari Ailus /**
1679dc794d3dSSakari Ailus  * struct ipu3_uapi_radial_cfg - Radial config
1680dc794d3dSSakari Ailus  *
1681dc794d3dSSakari Ailus  * @rad_nf: Radial. R^2 normalization factor is scale down by 2^ - (15 + scale)
1682dc794d3dSSakari Ailus  * @reserved0: reserved
1683dc794d3dSSakari Ailus  * @rad_inv_r2: Radial R^-2 normelized to (0.5..1).
1684dc794d3dSSakari Ailus  *		Precision u7, range [0, 127].
1685dc794d3dSSakari Ailus  * @reserved1: reserved
1686dc794d3dSSakari Ailus  */
1687dc794d3dSSakari Ailus struct ipu3_uapi_radial_cfg {
1688dc794d3dSSakari Ailus 	__u32 rad_nf:4;
1689dc794d3dSSakari Ailus 	__u32 reserved0:4;
1690dc794d3dSSakari Ailus 	__u32 rad_inv_r2:7;
1691dc794d3dSSakari Ailus 	__u32 reserved1:17;
1692dc794d3dSSakari Ailus } __packed;
1693dc794d3dSSakari Ailus 
1694dc794d3dSSakari Ailus /**
1695dc794d3dSSakari Ailus  * struct ipu3_uapi_rad_far_w - Radial FAR sub-group
1696dc794d3dSSakari Ailus  *
1697dc794d3dSSakari Ailus  * @rad_dir_far_sharp_w: Weight of wide direct sharpening, u1.6, range [0, 64],
1698dc794d3dSSakari Ailus  *			 default 64.
1699dc794d3dSSakari Ailus  * @rad_dir_far_dns_w: Weight of wide direct denoising, u1.6, range [0, 64],
1700dc794d3dSSakari Ailus  *			 default 0.
1701dc794d3dSSakari Ailus  * @rad_ndir_far_dns_power: power of non-direct sharpening, u1.6, range [0, 64],
1702dc794d3dSSakari Ailus  *			 default 0.
1703dc794d3dSSakari Ailus  * @reserved: reserved
1704dc794d3dSSakari Ailus  */
1705dc794d3dSSakari Ailus struct ipu3_uapi_rad_far_w {
1706dc794d3dSSakari Ailus 	__u32 rad_dir_far_sharp_w:8;
1707dc794d3dSSakari Ailus 	__u32 rad_dir_far_dns_w:8;
1708dc794d3dSSakari Ailus 	__u32 rad_ndir_far_dns_power:8;
1709dc794d3dSSakari Ailus 	__u32 reserved:8;
1710dc794d3dSSakari Ailus } __packed;
1711dc794d3dSSakari Ailus 
1712dc794d3dSSakari Ailus /**
1713dc794d3dSSakari Ailus  * struct ipu3_uapi_cu_cfg0 - Radius Config Unit cfg0 register
1714dc794d3dSSakari Ailus  *
1715dc794d3dSSakari Ailus  * @cu6_pow: Power of CU6. Power of non-direct sharpening, u3.4.
1716dc794d3dSSakari Ailus  * @reserved0: reserved
1717dc794d3dSSakari Ailus  * @cu_unsharp_pow: Power of unsharp mask, u2.4.
1718dc794d3dSSakari Ailus  * @reserved1: reserved
1719dc794d3dSSakari Ailus  * @rad_cu6_pow: Radial/corner CU6. Directed sharpening power, u3.4.
1720dc794d3dSSakari Ailus  * @reserved2: reserved
1721dc794d3dSSakari Ailus  * @rad_cu_unsharp_pow: Radial power of unsharp mask, u2.4.
1722dc794d3dSSakari Ailus  * @reserved3: reserved
1723dc794d3dSSakari Ailus  */
1724dc794d3dSSakari Ailus struct ipu3_uapi_cu_cfg0 {
1725dc794d3dSSakari Ailus 	__u32 cu6_pow:7;
1726dc794d3dSSakari Ailus 	__u32 reserved0:1;
1727dc794d3dSSakari Ailus 	__u32 cu_unsharp_pow:7;
1728dc794d3dSSakari Ailus 	__u32 reserved1:1;
1729dc794d3dSSakari Ailus 	__u32 rad_cu6_pow:7;
1730dc794d3dSSakari Ailus 	__u32 reserved2:1;
1731dc794d3dSSakari Ailus 	__u32 rad_cu_unsharp_pow:6;
1732dc794d3dSSakari Ailus 	__u32 reserved3:2;
1733dc794d3dSSakari Ailus } __packed;
1734dc794d3dSSakari Ailus 
1735dc794d3dSSakari Ailus /**
1736dc794d3dSSakari Ailus  * struct ipu3_uapi_cu_cfg1 - Radius Config Unit cfg1 register
1737dc794d3dSSakari Ailus  *
1738dc794d3dSSakari Ailus  * @rad_cu6_x1: X1 point of Config Unit 6, precision u9.0.
1739dc794d3dSSakari Ailus  * @reserved0: reserved
1740dc794d3dSSakari Ailus  * @rad_cu_unsharp_x1: X1 point for Config Unit unsharp for radial/corner point
1741dc794d3dSSakari Ailus  *			precision u9.0.
1742dc794d3dSSakari Ailus  * @reserved1: reserved
1743dc794d3dSSakari Ailus  */
1744dc794d3dSSakari Ailus struct ipu3_uapi_cu_cfg1 {
1745dc794d3dSSakari Ailus 	__u32 rad_cu6_x1:9;
1746dc794d3dSSakari Ailus 	__u32 reserved0:1;
1747dc794d3dSSakari Ailus 	__u32 rad_cu_unsharp_x1:9;
1748dc794d3dSSakari Ailus 	__u32 reserved1:13;
1749dc794d3dSSakari Ailus } __packed;
1750dc794d3dSSakari Ailus 
1751dc794d3dSSakari Ailus /**
1752dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_iefd_rad_cfg - IEFd parameters changed radially over
1753dc794d3dSSakari Ailus  *					 the picture plane.
1754dc794d3dSSakari Ailus  *
1755dc794d3dSSakari Ailus  * @reset_xy: reset xy value in radial calculation. &ipu3_uapi_radial_reset_xy
1756dc794d3dSSakari Ailus  * @reset_x2: reset x square value in radial calculation. See struct
1757dc794d3dSSakari Ailus  *	      &ipu3_uapi_radial_reset_x2
1758dc794d3dSSakari Ailus  * @reset_y2: reset y square value in radial calculation. See struct
1759dc794d3dSSakari Ailus  *	      &ipu3_uapi_radial_reset_y2
1760dc794d3dSSakari Ailus  * @cfg: radial config defined in &ipu3_uapi_radial_cfg
1761dc794d3dSSakari Ailus  * @rad_far_w: weight for wide range radial. &ipu3_uapi_rad_far_w
1762dc794d3dSSakari Ailus  * @cu_cfg0: configuration unit 0. See &ipu3_uapi_cu_cfg0
1763dc794d3dSSakari Ailus  * @cu_cfg1: configuration unit 1. See &ipu3_uapi_cu_cfg1
1764dc794d3dSSakari Ailus  */
1765dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_iefd_rad_cfg {
1766dc794d3dSSakari Ailus 	struct ipu3_uapi_radial_reset_xy reset_xy;
1767dc794d3dSSakari Ailus 	struct ipu3_uapi_radial_reset_x2 reset_x2;
1768dc794d3dSSakari Ailus 	struct ipu3_uapi_radial_reset_y2 reset_y2;
1769dc794d3dSSakari Ailus 	struct ipu3_uapi_radial_cfg cfg;
1770dc794d3dSSakari Ailus 	struct ipu3_uapi_rad_far_w rad_far_w;
1771dc794d3dSSakari Ailus 	struct ipu3_uapi_cu_cfg0 cu_cfg0;
1772dc794d3dSSakari Ailus 	struct ipu3_uapi_cu_cfg1 cu_cfg1;
1773dc794d3dSSakari Ailus } __packed;
1774dc794d3dSSakari Ailus 
1775dc794d3dSSakari Ailus /* Vssnlm - Very small scale non-local mean algorithm */
1776dc794d3dSSakari Ailus 
1777dc794d3dSSakari Ailus /**
1778dc794d3dSSakari Ailus  * struct ipu3_uapi_vss_lut_x - Vssnlm LUT x0/x1/x2
1779dc794d3dSSakari Ailus  *
1780dc794d3dSSakari Ailus  * @vs_x0: Vssnlm LUT x0, precision u8, range [0, 255], default 16.
1781dc794d3dSSakari Ailus  * @vs_x1: Vssnlm LUT x1, precision u8, range [0, 255], default 32.
1782dc794d3dSSakari Ailus  * @vs_x2: Vssnlm LUT x2, precision u8, range [0, 255], default 64.
1783dc794d3dSSakari Ailus  * @reserved2: reserved
1784dc794d3dSSakari Ailus  */
1785dc794d3dSSakari Ailus struct ipu3_uapi_vss_lut_x {
1786dc794d3dSSakari Ailus 	__u32 vs_x0:8;
1787dc794d3dSSakari Ailus 	__u32 vs_x1:8;
1788dc794d3dSSakari Ailus 	__u32 vs_x2:8;
1789dc794d3dSSakari Ailus 	__u32 reserved2:8;
1790dc794d3dSSakari Ailus } __packed;
1791dc794d3dSSakari Ailus 
1792dc794d3dSSakari Ailus /**
1793dc794d3dSSakari Ailus  * struct ipu3_uapi_vss_lut_y - Vssnlm LUT y0/y1/y2
1794dc794d3dSSakari Ailus  *
1795dc794d3dSSakari Ailus  * @vs_y1: Vssnlm LUT y1, precision u4, range [0, 8], default 1.
1796dc794d3dSSakari Ailus  * @reserved0: reserved
1797dc794d3dSSakari Ailus  * @vs_y2: Vssnlm LUT y2, precision u4, range [0, 8], default 3.
1798dc794d3dSSakari Ailus  * @reserved1: reserved
1799dc794d3dSSakari Ailus  * @vs_y3: Vssnlm LUT y3, precision u4, range [0, 8], default 8.
1800dc794d3dSSakari Ailus  * @reserved2: reserved
1801dc794d3dSSakari Ailus  */
1802dc794d3dSSakari Ailus struct ipu3_uapi_vss_lut_y {
1803dc794d3dSSakari Ailus 	__u32 vs_y1:4;
1804dc794d3dSSakari Ailus 	__u32 reserved0:4;
1805dc794d3dSSakari Ailus 	__u32 vs_y2:4;
1806dc794d3dSSakari Ailus 	__u32 reserved1:4;
1807dc794d3dSSakari Ailus 	__u32 vs_y3:4;
1808dc794d3dSSakari Ailus 	__u32 reserved2:12;
1809dc794d3dSSakari Ailus } __packed;
1810dc794d3dSSakari Ailus 
1811dc794d3dSSakari Ailus /**
1812dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_iefd_vssnlm_cfg - IEFd Vssnlm Lookup table
1813dc794d3dSSakari Ailus  *
1814dc794d3dSSakari Ailus  * @vss_lut_x: vss lookup table. See &ipu3_uapi_vss_lut_x description
1815dc794d3dSSakari Ailus  * @vss_lut_y: vss lookup table. See &ipu3_uapi_vss_lut_y description
1816dc794d3dSSakari Ailus  */
1817dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_iefd_vssnlm_cfg {
1818dc794d3dSSakari Ailus 	struct ipu3_uapi_vss_lut_x vss_lut_x;
1819dc794d3dSSakari Ailus 	struct ipu3_uapi_vss_lut_y vss_lut_y;
1820dc794d3dSSakari Ailus } __packed;
1821dc794d3dSSakari Ailus 
1822dc794d3dSSakari Ailus /**
1823dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_iefd_config - IEFd config
1824dc794d3dSSakari Ailus  *
1825dc794d3dSSakari Ailus  * @units: configuration unit setting, &ipu3_uapi_yuvp1_iefd_cfg_units
1826dc794d3dSSakari Ailus  * @config: configuration, as defined by &ipu3_uapi_yuvp1_iefd_config_s
1827dc794d3dSSakari Ailus  * @control: control setting, as defined by &ipu3_uapi_yuvp1_iefd_control
1828dc794d3dSSakari Ailus  * @sharp: sharpness setting, as defined by &ipu3_uapi_yuvp1_iefd_shrp_cfg
1829dc794d3dSSakari Ailus  * @unsharp: unsharpness setting, as defined by &ipu3_uapi_yuvp1_iefd_unshrp_cfg
1830dc794d3dSSakari Ailus  * @rad: radial setting, as defined by &ipu3_uapi_yuvp1_iefd_rad_cfg
1831dc794d3dSSakari Ailus  * @vsslnm: vsslnm setting, as defined by &ipu3_uapi_yuvp1_iefd_vssnlm_cfg
1832dc794d3dSSakari Ailus  */
1833dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_iefd_config {
1834dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_iefd_cfg_units units;
1835dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_iefd_config_s config;
1836dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_iefd_control control;
1837dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_iefd_shrp_cfg sharp;
1838dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_iefd_unshrp_cfg unsharp;
1839dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_iefd_rad_cfg rad;
1840dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_iefd_vssnlm_cfg vsslnm;
1841dc794d3dSSakari Ailus } __packed;
1842dc794d3dSSakari Ailus 
1843dc794d3dSSakari Ailus /**
1844dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_yds_config - Y Down-Sampling config
1845dc794d3dSSakari Ailus  *
1846dc794d3dSSakari Ailus  * @c00: range [0, 3], default 0x0
1847dc794d3dSSakari Ailus  * @c01: range [0, 3], default 0x1
1848dc794d3dSSakari Ailus  * @c02: range [0, 3], default 0x1
1849dc794d3dSSakari Ailus  * @c03: range [0, 3], default 0x0
1850dc794d3dSSakari Ailus  * @c10: range [0, 3], default 0x0
1851dc794d3dSSakari Ailus  * @c11: range [0, 3], default 0x1
1852dc794d3dSSakari Ailus  * @c12: range [0, 3], default 0x1
1853dc794d3dSSakari Ailus  * @c13: range [0, 3], default 0x0
1854dc794d3dSSakari Ailus  *
1855dc794d3dSSakari Ailus  * Above are 4x2 filter coefficients for chroma output downscaling.
1856dc794d3dSSakari Ailus  *
1857dc794d3dSSakari Ailus  * @norm_factor: Normalization factor, range [0, 4], default 2
1858dc794d3dSSakari Ailus  *		0 - divide by 1
1859dc794d3dSSakari Ailus  *		1 - divide by 2
1860dc794d3dSSakari Ailus  *		2 - divide by 4
1861dc794d3dSSakari Ailus  *		3 - divide by 8
1862dc794d3dSSakari Ailus  *		4 - divide by 16
1863dc794d3dSSakari Ailus  * @reserved0: reserved
1864dc794d3dSSakari Ailus  * @bin_output: Down sampling on Luma channel in two optional modes
1865dc794d3dSSakari Ailus  *		0 - Bin output 4.2.0 (default), 1 output 4.2.2.
1866dc794d3dSSakari Ailus  * @reserved1: reserved
1867dc794d3dSSakari Ailus  */
1868dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_yds_config {
1869dc794d3dSSakari Ailus 	__u32 c00:2;
1870dc794d3dSSakari Ailus 	__u32 c01:2;
1871dc794d3dSSakari Ailus 	__u32 c02:2;
1872dc794d3dSSakari Ailus 	__u32 c03:2;
1873dc794d3dSSakari Ailus 	__u32 c10:2;
1874dc794d3dSSakari Ailus 	__u32 c11:2;
1875dc794d3dSSakari Ailus 	__u32 c12:2;
1876dc794d3dSSakari Ailus 	__u32 c13:2;
1877dc794d3dSSakari Ailus 	__u32 norm_factor:5;
1878dc794d3dSSakari Ailus 	__u32 reserved0:4;
1879dc794d3dSSakari Ailus 	__u32 bin_output:1;
1880dc794d3dSSakari Ailus 	__u32 reserved1:6;
1881dc794d3dSSakari Ailus } __packed;
1882dc794d3dSSakari Ailus 
1883dc794d3dSSakari Ailus /* Chroma Noise Reduction */
1884dc794d3dSSakari Ailus 
1885dc794d3dSSakari Ailus /**
1886dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_chnr_enable_config - Chroma noise reduction enable
1887dc794d3dSSakari Ailus  *
1888dc794d3dSSakari Ailus  * @enable: enable/disable chroma noise reduction
1889dc794d3dSSakari Ailus  * @yuv_mode: 0 - YUV420, 1 - YUV422
1890dc794d3dSSakari Ailus  * @reserved0: reserved
1891dc794d3dSSakari Ailus  * @col_size: number of columns in the frame, max width is 2560
1892dc794d3dSSakari Ailus  * @reserved1: reserved
1893dc794d3dSSakari Ailus  */
1894dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_chnr_enable_config {
1895dc794d3dSSakari Ailus 	__u32 enable:1;
1896dc794d3dSSakari Ailus 	__u32 yuv_mode:1;
1897dc794d3dSSakari Ailus 	__u32 reserved0:14;
1898dc794d3dSSakari Ailus 	__u32 col_size:12;
1899dc794d3dSSakari Ailus 	__u32 reserved1:4;
1900dc794d3dSSakari Ailus } __packed;
1901dc794d3dSSakari Ailus 
1902dc794d3dSSakari Ailus /**
1903dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_chnr_coring_config - Coring thresholds for UV
1904dc794d3dSSakari Ailus  *
1905dc794d3dSSakari Ailus  * @u: U coring level, u0.13, range [0.0, 1.0], default 0.0
1906dc794d3dSSakari Ailus  * @reserved0: reserved
1907dc794d3dSSakari Ailus  * @v: V coring level, u0.13, range [0.0, 1.0], default 0.0
1908dc794d3dSSakari Ailus  * @reserved1: reserved
1909dc794d3dSSakari Ailus  */
1910dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_chnr_coring_config {
1911dc794d3dSSakari Ailus 	__u32 u:13;
1912dc794d3dSSakari Ailus 	__u32 reserved0:3;
1913dc794d3dSSakari Ailus 	__u32 v:13;
1914dc794d3dSSakari Ailus 	__u32 reserved1:3;
1915dc794d3dSSakari Ailus } __packed;
1916dc794d3dSSakari Ailus 
1917dc794d3dSSakari Ailus /**
1918dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_chnr_sense_gain_config - Chroma noise reduction gains
1919dc794d3dSSakari Ailus  *
1920dc794d3dSSakari Ailus  * All sensitivity gain parameters have precision u13.0, range [0, 8191].
1921dc794d3dSSakari Ailus  *
1922dc794d3dSSakari Ailus  * @vy: Sensitivity of horizontal edge of Y, default 100
1923dc794d3dSSakari Ailus  * @vu: Sensitivity of horizontal edge of U, default 100
1924dc794d3dSSakari Ailus  * @vv: Sensitivity of horizontal edge of V, default 100
1925dc794d3dSSakari Ailus  * @reserved0: reserved
1926dc794d3dSSakari Ailus  * @hy: Sensitivity of vertical edge of Y, default 50
1927dc794d3dSSakari Ailus  * @hu: Sensitivity of vertical edge of U, default 50
1928dc794d3dSSakari Ailus  * @hv: Sensitivity of vertical edge of V, default 50
1929dc794d3dSSakari Ailus  * @reserved1: reserved
1930dc794d3dSSakari Ailus  */
1931dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_chnr_sense_gain_config {
1932dc794d3dSSakari Ailus 	__u32 vy:8;
1933dc794d3dSSakari Ailus 	__u32 vu:8;
1934dc794d3dSSakari Ailus 	__u32 vv:8;
1935dc794d3dSSakari Ailus 	__u32 reserved0:8;
1936dc794d3dSSakari Ailus 
1937dc794d3dSSakari Ailus 	__u32 hy:8;
1938dc794d3dSSakari Ailus 	__u32 hu:8;
1939dc794d3dSSakari Ailus 	__u32 hv:8;
1940dc794d3dSSakari Ailus 	__u32 reserved1:8;
1941dc794d3dSSakari Ailus } __packed;
1942dc794d3dSSakari Ailus 
1943dc794d3dSSakari Ailus /**
1944dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_chnr_iir_fir_config - Chroma IIR/FIR filter config
1945dc794d3dSSakari Ailus  *
1946dc794d3dSSakari Ailus  * @fir_0h: Value of center tap in horizontal FIR, range [0, 32], default 8.
1947dc794d3dSSakari Ailus  * @reserved0: reserved
1948dc794d3dSSakari Ailus  * @fir_1h: Value of distance 1 in horizontal FIR, range [0, 32], default 12.
1949dc794d3dSSakari Ailus  * @reserved1: reserved
1950dc794d3dSSakari Ailus  * @fir_2h: Value of distance 2 tap in horizontal FIR, range [0, 32], default 0.
1951dc794d3dSSakari Ailus  * @dalpha_clip_val: weight for previous row in IIR, range [1, 256], default 0.
1952dc794d3dSSakari Ailus  * @reserved2: reserved
1953dc794d3dSSakari Ailus  */
1954dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_chnr_iir_fir_config {
1955dc794d3dSSakari Ailus 	__u32 fir_0h:6;
1956dc794d3dSSakari Ailus 	__u32 reserved0:2;
1957dc794d3dSSakari Ailus 	__u32 fir_1h:6;
1958dc794d3dSSakari Ailus 	__u32 reserved1:2;
1959dc794d3dSSakari Ailus 	__u32 fir_2h:6;
1960dc794d3dSSakari Ailus 	__u32 dalpha_clip_val:9;
1961dc794d3dSSakari Ailus 	__u32 reserved2:1;
1962dc794d3dSSakari Ailus } __packed;
1963dc794d3dSSakari Ailus 
1964dc794d3dSSakari Ailus /**
1965dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_chnr_config - Chroma noise reduction config
1966dc794d3dSSakari Ailus  *
1967dc794d3dSSakari Ailus  * @enable: chroma noise reduction enable, see
1968dc794d3dSSakari Ailus  *	    &ipu3_uapi_yuvp1_chnr_enable_config
1969dc794d3dSSakari Ailus  * @coring: coring config for chroma noise reduction, see
1970dc794d3dSSakari Ailus  *	    &ipu3_uapi_yuvp1_chnr_coring_config
1971dc794d3dSSakari Ailus  * @sense_gain: sensitivity config for chroma noise reduction, see
1972dc794d3dSSakari Ailus  *		ipu3_uapi_yuvp1_chnr_sense_gain_config
1973dc794d3dSSakari Ailus  * @iir_fir: iir and fir config for chroma noise reduction, see
1974dc794d3dSSakari Ailus  *	     ipu3_uapi_yuvp1_chnr_iir_fir_config
1975dc794d3dSSakari Ailus  */
1976dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_chnr_config {
1977dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_chnr_enable_config enable;
1978dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_chnr_coring_config coring;
1979dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_chnr_sense_gain_config sense_gain;
1980dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_chnr_iir_fir_config iir_fir;
1981dc794d3dSSakari Ailus } __packed;
1982dc794d3dSSakari Ailus 
1983dc794d3dSSakari Ailus /* Edge Enhancement and Noise Reduction */
1984dc794d3dSSakari Ailus 
1985dc794d3dSSakari Ailus /**
1986dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_y_ee_nr_lpf_config - Luma(Y) edge enhancement low-pass
1987dc794d3dSSakari Ailus  *					       filter coefficients
1988dc794d3dSSakari Ailus  *
1989dc794d3dSSakari Ailus  * @a_diag: Smoothing diagonal coefficient, u5.0.
1990dc794d3dSSakari Ailus  * @reserved0: reserved
1991dc794d3dSSakari Ailus  * @a_periph: Image smoothing perpherial, u5.0.
1992dc794d3dSSakari Ailus  * @reserved1: reserved
1993dc794d3dSSakari Ailus  * @a_cent: Image Smoothing center coefficient, u5.0.
1994dc794d3dSSakari Ailus  * @reserved2: reserved
1995dc794d3dSSakari Ailus  * @enable: 0: Y_EE_NR disabled, output = input; 1: Y_EE_NR enabled.
1996dc794d3dSSakari Ailus  */
1997dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_y_ee_nr_lpf_config {
1998dc794d3dSSakari Ailus 	__u32 a_diag:5;
1999dc794d3dSSakari Ailus 	__u32 reserved0:3;
2000dc794d3dSSakari Ailus 	__u32 a_periph:5;
2001dc794d3dSSakari Ailus 	__u32 reserved1:3;
2002dc794d3dSSakari Ailus 	__u32 a_cent:5;
2003dc794d3dSSakari Ailus 	__u32 reserved2:9;
2004dc794d3dSSakari Ailus 	__u32 enable:1;
2005dc794d3dSSakari Ailus } __packed;
2006dc794d3dSSakari Ailus 
2007dc794d3dSSakari Ailus /**
2008dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_y_ee_nr_sense_config - Luma(Y) edge enhancement
2009dc794d3dSSakari Ailus  *					noise reduction sensitivity gains
2010dc794d3dSSakari Ailus  *
2011dc794d3dSSakari Ailus  * @edge_sense_0: Sensitivity of edge in dark area. u13.0, default 8191.
2012dc794d3dSSakari Ailus  * @reserved0: reserved
2013dc794d3dSSakari Ailus  * @delta_edge_sense: Difference in the sensitivity of edges between
2014dc794d3dSSakari Ailus  *		      the bright and dark areas. u13.0, default 0.
2015dc794d3dSSakari Ailus  * @reserved1: reserved
2016dc794d3dSSakari Ailus  * @corner_sense_0: Sensitivity of corner in dark area. u13.0, default 0.
2017dc794d3dSSakari Ailus  * @reserved2: reserved
2018dc794d3dSSakari Ailus  * @delta_corner_sense: Difference in the sensitivity of corners between
2019dc794d3dSSakari Ailus  *			the bright and dark areas. u13.0, default 8191.
2020dc794d3dSSakari Ailus  * @reserved3: reserved
2021dc794d3dSSakari Ailus  */
2022dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_y_ee_nr_sense_config {
2023dc794d3dSSakari Ailus 	__u32 edge_sense_0:13;
2024dc794d3dSSakari Ailus 	__u32 reserved0:3;
2025dc794d3dSSakari Ailus 	__u32 delta_edge_sense:13;
2026dc794d3dSSakari Ailus 	__u32 reserved1:3;
2027dc794d3dSSakari Ailus 	__u32 corner_sense_0:13;
2028dc794d3dSSakari Ailus 	__u32 reserved2:3;
2029dc794d3dSSakari Ailus 	__u32 delta_corner_sense:13;
2030dc794d3dSSakari Ailus 	__u32 reserved3:3;
2031dc794d3dSSakari Ailus } __packed;
2032dc794d3dSSakari Ailus 
2033dc794d3dSSakari Ailus /**
2034dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_y_ee_nr_gain_config - Luma(Y) edge enhancement
2035dc794d3dSSakari Ailus  *						noise reduction gain config
2036dc794d3dSSakari Ailus  *
2037dc794d3dSSakari Ailus  * @gain_pos_0: Gain for positive edge in dark area. u5.0, [0, 16], default 2.
2038dc794d3dSSakari Ailus  * @reserved0: reserved
2039dc794d3dSSakari Ailus  * @delta_gain_posi: Difference in the gain of edges between the bright and
2040dc794d3dSSakari Ailus  *		     dark areas for positive edges. u5.0, [0, 16], default 0.
2041dc794d3dSSakari Ailus  * @reserved1: reserved
2042dc794d3dSSakari Ailus  * @gain_neg_0: Gain for negative edge in dark area. u5.0, [0, 16], default 8.
2043dc794d3dSSakari Ailus  * @reserved2: reserved
2044dc794d3dSSakari Ailus  * @delta_gain_neg: Difference in the gain of edges between the bright and
2045dc794d3dSSakari Ailus  *		    dark areas for negative edges. u5.0, [0, 16], default 0.
2046dc794d3dSSakari Ailus  * @reserved3: reserved
2047dc794d3dSSakari Ailus  */
2048dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_y_ee_nr_gain_config {
2049dc794d3dSSakari Ailus 	__u32 gain_pos_0:5;
2050dc794d3dSSakari Ailus 	__u32 reserved0:3;
2051dc794d3dSSakari Ailus 	__u32 delta_gain_posi:5;
2052dc794d3dSSakari Ailus 	__u32 reserved1:3;
2053dc794d3dSSakari Ailus 	__u32 gain_neg_0:5;
2054dc794d3dSSakari Ailus 	__u32 reserved2:3;
2055dc794d3dSSakari Ailus 	__u32 delta_gain_neg:5;
2056dc794d3dSSakari Ailus 	__u32 reserved3:3;
2057dc794d3dSSakari Ailus } __packed;
2058dc794d3dSSakari Ailus 
2059dc794d3dSSakari Ailus /**
2060dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_y_ee_nr_clip_config - Luma(Y) edge enhancement
2061dc794d3dSSakari Ailus  *					noise reduction clipping config
2062dc794d3dSSakari Ailus  *
2063dc794d3dSSakari Ailus  * @clip_pos_0: Limit of positive edge in dark area
2064dc794d3dSSakari Ailus  *		u5, value [0, 16], default 8.
2065dc794d3dSSakari Ailus  * @reserved0: reserved
2066dc794d3dSSakari Ailus  * @delta_clip_posi: Difference in the limit of edges between the bright
2067dc794d3dSSakari Ailus  *		     and dark areas for positive edges.
2068dc794d3dSSakari Ailus  *		     u5, value [0, 16], default 8.
2069dc794d3dSSakari Ailus  * @reserved1: reserved
2070dc794d3dSSakari Ailus  * @clip_neg_0: Limit of negative edge in dark area
2071dc794d3dSSakari Ailus  *		u5, value [0, 16], default 8.
2072dc794d3dSSakari Ailus  * @reserved2: reserved
2073dc794d3dSSakari Ailus  * @delta_clip_neg: Difference in the limit of edges between the bright
2074dc794d3dSSakari Ailus  *		    and dark areas for negative edges.
2075dc794d3dSSakari Ailus  *		    u5, value [0, 16], default 8.
2076dc794d3dSSakari Ailus  * @reserved3: reserved
2077dc794d3dSSakari Ailus  */
2078dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_y_ee_nr_clip_config {
2079dc794d3dSSakari Ailus 	__u32 clip_pos_0:5;
2080dc794d3dSSakari Ailus 	__u32 reserved0:3;
2081dc794d3dSSakari Ailus 	__u32 delta_clip_posi:5;
2082dc794d3dSSakari Ailus 	__u32 reserved1:3;
2083dc794d3dSSakari Ailus 	__u32 clip_neg_0:5;
2084dc794d3dSSakari Ailus 	__u32 reserved2:3;
2085dc794d3dSSakari Ailus 	__u32 delta_clip_neg:5;
2086dc794d3dSSakari Ailus 	__u32 reserved3:3;
2087dc794d3dSSakari Ailus } __packed;
2088dc794d3dSSakari Ailus 
2089dc794d3dSSakari Ailus /**
2090dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_y_ee_nr_frng_config - Luma(Y) edge enhancement
2091dc794d3dSSakari Ailus  *						noise reduction fringe config
2092dc794d3dSSakari Ailus  *
2093dc794d3dSSakari Ailus  * @gain_exp: Common exponent of gains, u4, [0, 8], default 2.
2094dc794d3dSSakari Ailus  * @reserved0: reserved
2095dc794d3dSSakari Ailus  * @min_edge: Threshold for edge and smooth stitching, u13.
2096dc794d3dSSakari Ailus  * @reserved1: reserved
2097dc794d3dSSakari Ailus  * @lin_seg_param: Power of LinSeg, u4.
2098dc794d3dSSakari Ailus  * @reserved2: reserved
2099dc794d3dSSakari Ailus  * @t1: Parameter for enabling/disabling the edge enhancement, u1.0, [0, 1],
2100dc794d3dSSakari Ailus  *	default 1.
2101dc794d3dSSakari Ailus  * @t2: Parameter for enabling/disabling the smoothing, u1.0, [0, 1],
2102dc794d3dSSakari Ailus  *	default 1.
2103dc794d3dSSakari Ailus  * @reserved3: reserved
2104dc794d3dSSakari Ailus  */
2105dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_y_ee_nr_frng_config {
2106dc794d3dSSakari Ailus 	__u32 gain_exp:4;
2107dc794d3dSSakari Ailus 	__u32 reserved0:28;
2108dc794d3dSSakari Ailus 	__u32 min_edge:13;
2109dc794d3dSSakari Ailus 	__u32 reserved1:3;
2110dc794d3dSSakari Ailus 	__u32 lin_seg_param:4;
2111dc794d3dSSakari Ailus 	__u32 reserved2:4;
2112dc794d3dSSakari Ailus 	__u32 t1:1;
2113dc794d3dSSakari Ailus 	__u32 t2:1;
2114dc794d3dSSakari Ailus 	__u32 reserved3:6;
2115dc794d3dSSakari Ailus } __packed;
2116dc794d3dSSakari Ailus 
2117dc794d3dSSakari Ailus /**
2118dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_y_ee_nr_diag_config - Luma(Y) edge enhancement
2119dc794d3dSSakari Ailus  *					noise reduction diagonal config
2120dc794d3dSSakari Ailus  *
2121dc794d3dSSakari Ailus  * @diag_disc_g: Coefficient that prioritize diagonal edge direction on
2122dc794d3dSSakari Ailus  *		 horizontal or vertical for final enhancement.
2123dc794d3dSSakari Ailus  *		 u4.0, [1, 15], default 1.
2124dc794d3dSSakari Ailus  * @reserved0: reserved
2125dc794d3dSSakari Ailus  * @hvw_hor: Weight of horizontal/vertical edge enhancement for hv edge.
2126dc794d3dSSakari Ailus  *		u2.2, [1, 15], default 4.
2127dc794d3dSSakari Ailus  * @dw_hor: Weight of diagonal edge enhancement for hv edge.
2128dc794d3dSSakari Ailus  *		u2.2, [1, 15], default 1.
2129dc794d3dSSakari Ailus  * @hvw_diag: Weight of horizontal/vertical edge enhancement for diagonal edge.
2130dc794d3dSSakari Ailus  *		u2.2, [1, 15], default 1.
2131dc794d3dSSakari Ailus  * @dw_diag: Weight of diagonal edge enhancement for diagonal edge.
2132dc794d3dSSakari Ailus  *		u2.2, [1, 15], default 4.
2133dc794d3dSSakari Ailus  * @reserved1: reserved
2134dc794d3dSSakari Ailus  */
2135dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_y_ee_nr_diag_config {
2136dc794d3dSSakari Ailus 	__u32 diag_disc_g:4;
2137dc794d3dSSakari Ailus 	__u32 reserved0:4;
2138dc794d3dSSakari Ailus 	__u32 hvw_hor:4;
2139dc794d3dSSakari Ailus 	__u32 dw_hor:4;
2140dc794d3dSSakari Ailus 	__u32 hvw_diag:4;
2141dc794d3dSSakari Ailus 	__u32 dw_diag:4;
2142dc794d3dSSakari Ailus 	__u32 reserved1:8;
2143dc794d3dSSakari Ailus } __packed;
2144dc794d3dSSakari Ailus 
2145dc794d3dSSakari Ailus /**
2146dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_y_ee_nr_fc_coring_config - Luma(Y) edge enhancement
2147dc794d3dSSakari Ailus  *		noise reduction false color correction (FCC) coring config
2148dc794d3dSSakari Ailus  *
2149dc794d3dSSakari Ailus  * @pos_0: Gain for positive edge in dark, u13.0, [0, 16], default 0.
2150dc794d3dSSakari Ailus  * @reserved0: reserved
2151dc794d3dSSakari Ailus  * @pos_delta: Gain for positive edge in bright, value: pos_0 + pos_delta <=16
2152dc794d3dSSakari Ailus  *		u13.0, default 0.
2153dc794d3dSSakari Ailus  * @reserved1: reserved
2154dc794d3dSSakari Ailus  * @neg_0: Gain for negative edge in dark area, u13.0, range [0, 16], default 0.
2155dc794d3dSSakari Ailus  * @reserved2: reserved
2156dc794d3dSSakari Ailus  * @neg_delta: Gain for negative edge in bright area. neg_0 + neg_delta <=16
2157dc794d3dSSakari Ailus  *		u13.0, default 0.
2158dc794d3dSSakari Ailus  * @reserved3: reserved
2159dc794d3dSSakari Ailus  *
2160dc794d3dSSakari Ailus  * Coring is a simple soft thresholding technique.
2161dc794d3dSSakari Ailus  */
2162dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_y_ee_nr_fc_coring_config {
2163dc794d3dSSakari Ailus 	__u32 pos_0:13;
2164dc794d3dSSakari Ailus 	__u32 reserved0:3;
2165dc794d3dSSakari Ailus 	__u32 pos_delta:13;
2166dc794d3dSSakari Ailus 	__u32 reserved1:3;
2167dc794d3dSSakari Ailus 	__u32 neg_0:13;
2168dc794d3dSSakari Ailus 	__u32 reserved2:3;
2169dc794d3dSSakari Ailus 	__u32 neg_delta:13;
2170dc794d3dSSakari Ailus 	__u32 reserved3:3;
2171dc794d3dSSakari Ailus } __packed;
2172dc794d3dSSakari Ailus 
2173dc794d3dSSakari Ailus /**
2174dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp1_y_ee_nr_config - Edge enhancement and noise reduction
2175dc794d3dSSakari Ailus  *
2176dc794d3dSSakari Ailus  * @lpf: low-pass filter config. See &ipu3_uapi_yuvp1_y_ee_nr_lpf_config
2177dc794d3dSSakari Ailus  * @sense: sensitivity config. See &ipu3_uapi_yuvp1_y_ee_nr_sense_config
2178dc794d3dSSakari Ailus  * @gain: gain config as defined in &ipu3_uapi_yuvp1_y_ee_nr_gain_config
2179dc794d3dSSakari Ailus  * @clip: clip config as defined in &ipu3_uapi_yuvp1_y_ee_nr_clip_config
2180dc794d3dSSakari Ailus  * @frng: fringe config as defined in &ipu3_uapi_yuvp1_y_ee_nr_frng_config
2181dc794d3dSSakari Ailus  * @diag: diagonal edge config. See &ipu3_uapi_yuvp1_y_ee_nr_diag_config
2182dc794d3dSSakari Ailus  * @fc_coring: coring config for fringe control. See
2183dc794d3dSSakari Ailus  *	       &ipu3_uapi_yuvp1_y_ee_nr_fc_coring_config
2184dc794d3dSSakari Ailus  */
2185dc794d3dSSakari Ailus struct ipu3_uapi_yuvp1_y_ee_nr_config {
2186dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_y_ee_nr_lpf_config lpf;
2187dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_y_ee_nr_sense_config sense;
2188dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_y_ee_nr_gain_config gain;
2189dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_y_ee_nr_clip_config clip;
2190dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_y_ee_nr_frng_config frng;
2191dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_y_ee_nr_diag_config diag;
2192dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_y_ee_nr_fc_coring_config fc_coring;
2193dc794d3dSSakari Ailus } __packed;
2194dc794d3dSSakari Ailus 
2195dc794d3dSSakari Ailus /* Total Color Correction */
2196dc794d3dSSakari Ailus 
2197dc794d3dSSakari Ailus /**
2198dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp2_tcc_gen_control_static_config - Total color correction
2199dc794d3dSSakari Ailus  *				general control config
2200dc794d3dSSakari Ailus  *
2201dc794d3dSSakari Ailus  * @en:	0 - TCC disabled. Output = input 1 - TCC enabled.
2202dc794d3dSSakari Ailus  * @blend_shift:	blend shift, Range[3, 4], default NA.
2203dc794d3dSSakari Ailus  * @gain_according_to_y_only:	0: Gain is calculated according to YUV,
2204dc794d3dSSakari Ailus  *				1: Gain is calculated according to Y only
2205dc794d3dSSakari Ailus  * @reserved0: reserved
2206dc794d3dSSakari Ailus  * @gamma:	Final blending coefficients. Values[-16, 16], default NA.
2207dc794d3dSSakari Ailus  * @reserved1: reserved
2208dc794d3dSSakari Ailus  * @delta:	Final blending coefficients. Values[-16, 16], default NA.
2209dc794d3dSSakari Ailus  * @reserved2: reserved
2210dc794d3dSSakari Ailus  */
2211dc794d3dSSakari Ailus struct ipu3_uapi_yuvp2_tcc_gen_control_static_config {
2212dc794d3dSSakari Ailus 	__u32 en:1;
2213dc794d3dSSakari Ailus 	__u32 blend_shift:3;
2214dc794d3dSSakari Ailus 	__u32 gain_according_to_y_only:1;
2215dc794d3dSSakari Ailus 	__u32 reserved0:11;
2216dc794d3dSSakari Ailus 	__s32 gamma:5;
2217dc794d3dSSakari Ailus 	__u32 reserved1:3;
2218dc794d3dSSakari Ailus 	__s32 delta:5;
2219dc794d3dSSakari Ailus 	__u32 reserved2:3;
2220dc794d3dSSakari Ailus } __packed;
2221dc794d3dSSakari Ailus 
2222dc794d3dSSakari Ailus /**
2223dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp2_tcc_macc_elem_static_config - Total color correction
2224dc794d3dSSakari Ailus  *				multi-axis color control (MACC) config
2225dc794d3dSSakari Ailus  *
2226dc794d3dSSakari Ailus  * @a: a coefficient for 2x2 MACC conversion matrix.
2227dc794d3dSSakari Ailus  * @reserved0: reserved
2228dc794d3dSSakari Ailus  * @b: b coefficient  2x2 MACC conversion matrix.
2229dc794d3dSSakari Ailus  * @reserved1: reserved
2230dc794d3dSSakari Ailus  * @c: c coefficient for 2x2 MACC conversion matrix.
2231dc794d3dSSakari Ailus  * @reserved2: reserved
2232dc794d3dSSakari Ailus  * @d: d coefficient for 2x2 MACC conversion matrix.
2233dc794d3dSSakari Ailus  * @reserved3: reserved
2234dc794d3dSSakari Ailus  */
2235dc794d3dSSakari Ailus struct ipu3_uapi_yuvp2_tcc_macc_elem_static_config {
2236dc794d3dSSakari Ailus 	__s32 a:12;
2237dc794d3dSSakari Ailus 	__u32 reserved0:4;
2238dc794d3dSSakari Ailus 	__s32 b:12;
2239dc794d3dSSakari Ailus 	__u32 reserved1:4;
2240dc794d3dSSakari Ailus 	__s32 c:12;
2241dc794d3dSSakari Ailus 	__u32 reserved2:4;
2242dc794d3dSSakari Ailus 	__s32 d:12;
2243dc794d3dSSakari Ailus 	__u32 reserved3:4;
2244dc794d3dSSakari Ailus } __packed;
2245dc794d3dSSakari Ailus 
2246dc794d3dSSakari Ailus /**
2247dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp2_tcc_macc_table_static_config - Total color correction
2248dc794d3dSSakari Ailus  *				multi-axis color control (MACC) table array
2249dc794d3dSSakari Ailus  *
2250dc794d3dSSakari Ailus  * @entries: config for multi axis color correction, as specified by
2251dc794d3dSSakari Ailus  *	     &ipu3_uapi_yuvp2_tcc_macc_elem_static_config
2252dc794d3dSSakari Ailus  */
2253dc794d3dSSakari Ailus struct ipu3_uapi_yuvp2_tcc_macc_table_static_config {
2254dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp2_tcc_macc_elem_static_config
2255dc794d3dSSakari Ailus 		entries[IPU3_UAPI_YUVP2_TCC_MACC_TABLE_ELEMENTS];
2256dc794d3dSSakari Ailus } __packed;
2257dc794d3dSSakari Ailus 
2258dc794d3dSSakari Ailus /**
2259dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp2_tcc_inv_y_lut_static_config - Total color correction
2260dc794d3dSSakari Ailus  *				inverse y lookup table
2261dc794d3dSSakari Ailus  *
2262dc794d3dSSakari Ailus  * @entries: lookup table for inverse y estimation, and use it to estimate the
2263dc794d3dSSakari Ailus  *	     ratio between luma and chroma. Chroma by approximate the absolute
2264dc794d3dSSakari Ailus  *	     value of the radius on the chroma plane (R = sqrt(u^2+v^2) ) and
2265dc794d3dSSakari Ailus  *	     luma by approximate by 1/Y.
2266dc794d3dSSakari Ailus  */
2267dc794d3dSSakari Ailus struct ipu3_uapi_yuvp2_tcc_inv_y_lut_static_config {
2268dc794d3dSSakari Ailus 	__u16 entries[IPU3_UAPI_YUVP2_TCC_INV_Y_LUT_ELEMENTS];
2269dc794d3dSSakari Ailus } __packed;
2270dc794d3dSSakari Ailus 
2271dc794d3dSSakari Ailus /**
2272dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp2_tcc_gain_pcwl_lut_static_config - Total color
2273dc794d3dSSakari Ailus  *					correction lookup table for PCWL
2274dc794d3dSSakari Ailus  *
2275dc794d3dSSakari Ailus  * @entries: lookup table for gain piece wise linear transformation (PCWL)
2276dc794d3dSSakari Ailus  */
2277dc794d3dSSakari Ailus struct ipu3_uapi_yuvp2_tcc_gain_pcwl_lut_static_config {
2278dc794d3dSSakari Ailus 	__u16 entries[IPU3_UAPI_YUVP2_TCC_GAIN_PCWL_LUT_ELEMENTS];
2279dc794d3dSSakari Ailus } __packed;
2280dc794d3dSSakari Ailus 
2281dc794d3dSSakari Ailus /**
2282dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp2_tcc_r_sqr_lut_static_config - Total color correction
2283dc794d3dSSakari Ailus  *				lookup table for r square root
2284dc794d3dSSakari Ailus  *
2285dc794d3dSSakari Ailus  * @entries: lookup table for r square root estimation
2286dc794d3dSSakari Ailus  */
2287dc794d3dSSakari Ailus struct ipu3_uapi_yuvp2_tcc_r_sqr_lut_static_config {
2288dc794d3dSSakari Ailus 	__s16 entries[IPU3_UAPI_YUVP2_TCC_R_SQR_LUT_ELEMENTS];
2289dc794d3dSSakari Ailus } __packed;
2290dc794d3dSSakari Ailus 
2291dc794d3dSSakari Ailus /**
2292dc794d3dSSakari Ailus  * struct ipu3_uapi_yuvp2_tcc_static_config- Total color correction static
2293dc794d3dSSakari Ailus  *
2294dc794d3dSSakari Ailus  * @gen_control: general config for Total Color Correction
2295dc794d3dSSakari Ailus  * @macc_table: config for multi axis color correction
2296dc794d3dSSakari Ailus  * @inv_y_lut: lookup table for inverse y estimation
2297dc794d3dSSakari Ailus  * @gain_pcwl: lookup table for gain PCWL
2298dc794d3dSSakari Ailus  * @r_sqr_lut: lookup table for r square root estimation.
2299dc794d3dSSakari Ailus  */
2300dc794d3dSSakari Ailus struct ipu3_uapi_yuvp2_tcc_static_config {
2301dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp2_tcc_gen_control_static_config gen_control;
2302dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp2_tcc_macc_table_static_config macc_table;
2303dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp2_tcc_inv_y_lut_static_config inv_y_lut;
2304dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp2_tcc_gain_pcwl_lut_static_config gain_pcwl;
2305dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp2_tcc_r_sqr_lut_static_config r_sqr_lut;
2306dc794d3dSSakari Ailus } __packed;
2307dc794d3dSSakari Ailus 
2308dc794d3dSSakari Ailus /* Advanced Noise Reduction related structs */
2309dc794d3dSSakari Ailus 
2310dc794d3dSSakari Ailus /*
2311dc794d3dSSakari Ailus  * struct ipu3_uapi_anr_alpha - Advanced noise reduction alpha
2312dc794d3dSSakari Ailus  *
2313dc794d3dSSakari Ailus  * Tunable parameters that are subject to modification according to the
2314dc794d3dSSakari Ailus  * total gain used.
2315dc794d3dSSakari Ailus  */
2316dc794d3dSSakari Ailus struct ipu3_uapi_anr_alpha {
2317dc794d3dSSakari Ailus 	__u16 gr;
2318dc794d3dSSakari Ailus 	__u16 r;
2319dc794d3dSSakari Ailus 	__u16 b;
2320dc794d3dSSakari Ailus 	__u16 gb;
2321dc794d3dSSakari Ailus 	__u16 dc_gr;
2322dc794d3dSSakari Ailus 	__u16 dc_r;
2323dc794d3dSSakari Ailus 	__u16 dc_b;
2324dc794d3dSSakari Ailus 	__u16 dc_gb;
2325dc794d3dSSakari Ailus } __packed;
2326dc794d3dSSakari Ailus 
2327dc794d3dSSakari Ailus /*
2328dc794d3dSSakari Ailus  * struct ipu3_uapi_anr_beta - Advanced noise reduction beta
2329dc794d3dSSakari Ailus  *
2330dc794d3dSSakari Ailus  * Tunable parameters that are subject to modification according to the
2331dc794d3dSSakari Ailus  * total gain used.
2332dc794d3dSSakari Ailus  */
2333dc794d3dSSakari Ailus struct ipu3_uapi_anr_beta {
2334dc794d3dSSakari Ailus 	__u16 beta_gr;
2335dc794d3dSSakari Ailus 	__u16 beta_r;
2336dc794d3dSSakari Ailus 	__u16 beta_b;
2337dc794d3dSSakari Ailus 	__u16 beta_gb;
2338dc794d3dSSakari Ailus } __packed;
2339dc794d3dSSakari Ailus 
2340dc794d3dSSakari Ailus /*
2341dc794d3dSSakari Ailus  * struct ipu3_uapi_anr_plane_color - Advanced noise reduction per plane R, Gr,
2342dc794d3dSSakari Ailus  *				      Gb and B register settings
2343dc794d3dSSakari Ailus  *
2344dc794d3dSSakari Ailus  * Tunable parameters that are subject to modification according to the
2345dc794d3dSSakari Ailus  * total gain used.
2346dc794d3dSSakari Ailus  */
2347dc794d3dSSakari Ailus struct ipu3_uapi_anr_plane_color {
2348dc794d3dSSakari Ailus 	__u16 reg_w_gr[16];
2349dc794d3dSSakari Ailus 	__u16 reg_w_r[16];
2350dc794d3dSSakari Ailus 	__u16 reg_w_b[16];
2351dc794d3dSSakari Ailus 	__u16 reg_w_gb[16];
2352dc794d3dSSakari Ailus } __packed;
2353dc794d3dSSakari Ailus 
2354dc794d3dSSakari Ailus /**
2355dc794d3dSSakari Ailus  * struct ipu3_uapi_anr_transform_config - Advanced noise reduction transform
2356dc794d3dSSakari Ailus  *
2357dc794d3dSSakari Ailus  * @enable: advanced noise reduction enabled.
2358dc794d3dSSakari Ailus  * @adaptive_treshhold_en: On IPU3, adaptive threshold is always enabled.
2359dc794d3dSSakari Ailus  * @reserved1: reserved
2360dc794d3dSSakari Ailus  * @reserved2: reserved
2361dc794d3dSSakari Ailus  * @alpha: using following defaults:
2362dc794d3dSSakari Ailus  *		13, 13, 13, 13, 0, 0, 0, 0
2363dc794d3dSSakari Ailus  *		11, 11, 11, 11, 0, 0, 0, 0
2364dc794d3dSSakari Ailus  *		14,  14, 14, 14, 0, 0, 0, 0
2365dc794d3dSSakari Ailus  * @beta: use following defaults:
2366dc794d3dSSakari Ailus  *		24, 24, 24, 24
2367dc794d3dSSakari Ailus  *		21, 20, 20, 21
2368dc794d3dSSakari Ailus  *		25, 25, 25, 25
2369dc794d3dSSakari Ailus  * @color: use defaults defined in driver/media/pci/intel/ipu3-tables.c
2370dc794d3dSSakari Ailus  * @sqrt_lut: 11 bits per element, values =
2371dc794d3dSSakari Ailus  *					[724 768 810 849 887
2372dc794d3dSSakari Ailus  *					923 958 991 1024 1056
2373dc794d3dSSakari Ailus  *					1116 1145 1173 1201 1086
2374dc794d3dSSakari Ailus  *					1228 1254 1280 1305 1330
2375dc794d3dSSakari Ailus  *					1355 1379 1402 1425 1448]
2376dc794d3dSSakari Ailus  * @xreset: Reset value of X for r^2 calculation Value: col_start-X_center
2377dc794d3dSSakari Ailus  *	Constraint: Xreset + FrameWdith=4095 Xreset= -4095, default -1632.
2378dc794d3dSSakari Ailus  * @reserved3: reserved
2379dc794d3dSSakari Ailus  * @yreset: Reset value of Y for r^2 calculation Value: row_start-Y_center
2380dc794d3dSSakari Ailus  *	 Constraint: Yreset + FrameHeight=4095 Yreset= -4095, default -1224.
2381dc794d3dSSakari Ailus  * @reserved4: reserved
2382dc794d3dSSakari Ailus  * @x_sqr_reset: Reset value of X^2 for r^2 calculation Value = (Xreset)^2
2383dc794d3dSSakari Ailus  * @r_normfactor: Normalization factor for R. Default 14.
2384dc794d3dSSakari Ailus  * @reserved5: reserved
2385dc794d3dSSakari Ailus  * @y_sqr_reset: Reset value of Y^2 for r^2 calculation Value = (Yreset)^2
2386dc794d3dSSakari Ailus  * @gain_scale: Parameter describing shading gain as a function of distance
2387dc794d3dSSakari Ailus  *		from the image center.
2388dc794d3dSSakari Ailus  *		A single value per frame, loaded by the driver. Default 115.
2389dc794d3dSSakari Ailus  */
2390dc794d3dSSakari Ailus struct ipu3_uapi_anr_transform_config {
2391dc794d3dSSakari Ailus 	__u32 enable:1;			/* 0 or 1, disabled or enabled */
2392dc794d3dSSakari Ailus 	__u32 adaptive_treshhold_en:1;	/* On IPU3, always enabled */
2393dc794d3dSSakari Ailus 
2394dc794d3dSSakari Ailus 	__u32 reserved1:30;
2395dc794d3dSSakari Ailus 	__u8 reserved2[44];
2396dc794d3dSSakari Ailus 
2397dc794d3dSSakari Ailus 	struct ipu3_uapi_anr_alpha alpha[3];
2398dc794d3dSSakari Ailus 	struct ipu3_uapi_anr_beta beta[3];
2399dc794d3dSSakari Ailus 	struct ipu3_uapi_anr_plane_color color[3];
2400dc794d3dSSakari Ailus 
2401dc794d3dSSakari Ailus 	__u16 sqrt_lut[IPU3_UAPI_ANR_LUT_SIZE];	/* 11 bits per element */
2402dc794d3dSSakari Ailus 
2403dc794d3dSSakari Ailus 	__s16 xreset:13;
2404dc794d3dSSakari Ailus 	__u16 reserved3:3;
2405dc794d3dSSakari Ailus 	__s16 yreset:13;
2406dc794d3dSSakari Ailus 	__u16 reserved4:3;
2407dc794d3dSSakari Ailus 
2408dc794d3dSSakari Ailus 	__u32 x_sqr_reset:24;
2409dc794d3dSSakari Ailus 	__u32 r_normfactor:5;
2410dc794d3dSSakari Ailus 	__u32 reserved5:3;
2411dc794d3dSSakari Ailus 
2412dc794d3dSSakari Ailus 	__u32 y_sqr_reset:24;
2413dc794d3dSSakari Ailus 	__u32 gain_scale:8;
2414dc794d3dSSakari Ailus } __packed;
2415dc794d3dSSakari Ailus 
2416dc794d3dSSakari Ailus /**
2417dc794d3dSSakari Ailus  * struct ipu3_uapi_anr_stitch_pyramid - ANR stitch pyramid
2418dc794d3dSSakari Ailus  *
2419dc794d3dSSakari Ailus  * @entry0: pyramid LUT entry0, range [0x0, 0x3f]
2420dc794d3dSSakari Ailus  * @entry1: pyramid LUT entry1, range [0x0, 0x3f]
2421dc794d3dSSakari Ailus  * @entry2: pyramid LUT entry2, range [0x0, 0x3f]
2422dc794d3dSSakari Ailus  * @reserved: reserved
2423dc794d3dSSakari Ailus  */
2424dc794d3dSSakari Ailus struct ipu3_uapi_anr_stitch_pyramid {
2425dc794d3dSSakari Ailus 	__u32 entry0:6;
2426dc794d3dSSakari Ailus 	__u32 entry1:6;
2427dc794d3dSSakari Ailus 	__u32 entry2:6;
2428dc794d3dSSakari Ailus 	__u32 reserved:14;
2429dc794d3dSSakari Ailus } __packed;
2430dc794d3dSSakari Ailus 
2431dc794d3dSSakari Ailus /**
2432dc794d3dSSakari Ailus  * struct ipu3_uapi_anr_stitch_config - ANR stitch config
2433dc794d3dSSakari Ailus  *
2434dc794d3dSSakari Ailus  * @anr_stitch_en: enable stitch. Enabled with 1.
2435dc794d3dSSakari Ailus  * @reserved: reserved
2436dc794d3dSSakari Ailus  * @pyramid: pyramid table as defined by &ipu3_uapi_anr_stitch_pyramid
2437dc794d3dSSakari Ailus  *		default values:
2438dc794d3dSSakari Ailus  *		{ 1, 3, 5 }, { 7, 7, 5 }, { 3, 1, 3 },
2439dc794d3dSSakari Ailus  *		{ 9, 15, 21 }, { 21, 15, 9 }, { 3, 5, 15 },
2440dc794d3dSSakari Ailus  *		{ 25, 35, 35 }, { 25, 15, 5 }, { 7, 21, 35 },
2441dc794d3dSSakari Ailus  *		{ 49, 49, 35 }, { 21, 7, 7 }, { 21, 35, 49 },
2442dc794d3dSSakari Ailus  *		{ 49, 35, 21 }, { 7, 5, 15 }, { 25, 35, 35 },
2443dc794d3dSSakari Ailus  *		{ 25, 15, 5 }, { 3, 9, 15 }, { 21, 21, 15 },
2444dc794d3dSSakari Ailus  *		{ 9, 3, 1 }, { 3, 5, 7 }, { 7, 5, 3}, { 1 }
2445dc794d3dSSakari Ailus  */
2446dc794d3dSSakari Ailus struct ipu3_uapi_anr_stitch_config {
2447dc794d3dSSakari Ailus 	__u32 anr_stitch_en;
2448dc794d3dSSakari Ailus 	__u8 reserved[44];
2449dc794d3dSSakari Ailus 	struct ipu3_uapi_anr_stitch_pyramid pyramid[IPU3_UAPI_ANR_PYRAMID_SIZE];
2450dc794d3dSSakari Ailus } __packed;
2451dc794d3dSSakari Ailus 
2452dc794d3dSSakari Ailus /**
2453dc794d3dSSakari Ailus  * struct ipu3_uapi_anr_config - ANR config
2454dc794d3dSSakari Ailus  *
2455dc794d3dSSakari Ailus  * @transform:	advanced noise reduction transform config as specified by
2456dc794d3dSSakari Ailus  *		&ipu3_uapi_anr_transform_config
2457dc794d3dSSakari Ailus  * @stitch: create 4x4 patch from 4 surrounding 8x8 patches.
2458dc794d3dSSakari Ailus  */
2459dc794d3dSSakari Ailus struct ipu3_uapi_anr_config {
2460dc794d3dSSakari Ailus 	struct ipu3_uapi_anr_transform_config transform __attribute__((aligned(32)));
2461dc794d3dSSakari Ailus 	struct ipu3_uapi_anr_stitch_config stitch __attribute__((aligned(32)));
2462dc794d3dSSakari Ailus } __packed;
2463dc794d3dSSakari Ailus 
2464dc794d3dSSakari Ailus /**
2465dc794d3dSSakari Ailus  * struct ipu3_uapi_acc_param - Accelerator cluster parameters
2466dc794d3dSSakari Ailus  *
2467dc794d3dSSakari Ailus  * ACC refers to the HW cluster containing all Fixed Functions (FFs). Each FF
2468dc794d3dSSakari Ailus  * implements a specific algorithm.
2469dc794d3dSSakari Ailus  *
2470dc794d3dSSakari Ailus  * @bnr:	parameters for bayer noise reduction static config. See
2471dc794d3dSSakari Ailus  *		&ipu3_uapi_bnr_static_config
2472dc794d3dSSakari Ailus  * @green_disparity:	disparity static config between gr and gb channel.
2473dc794d3dSSakari Ailus  *			See &ipu3_uapi_bnr_static_config_green_disparity
2474dc794d3dSSakari Ailus  * @dm:	de-mosaic config. See &ipu3_uapi_dm_config
2475dc794d3dSSakari Ailus  * @ccm:	color correction matrix. See &ipu3_uapi_ccm_mat_config
2476dc794d3dSSakari Ailus  * @gamma:	gamma correction config. See &ipu3_uapi_gamma_config
2477dc794d3dSSakari Ailus  * @csc:	color space conversion matrix. See &ipu3_uapi_csc_mat_config
2478dc794d3dSSakari Ailus  * @cds:	color down sample config. See &ipu3_uapi_cds_params
2479dc794d3dSSakari Ailus  * @shd:	lens shading correction config. See &ipu3_uapi_shd_config
2480dc794d3dSSakari Ailus  * @iefd:	Image enhancement filter and denoise config.
2481dc794d3dSSakari Ailus  *		&ipu3_uapi_yuvp1_iefd_config
2482dc794d3dSSakari Ailus  * @yds_c0:	y down scaler config. &ipu3_uapi_yuvp1_yds_config
2483dc794d3dSSakari Ailus  * @chnr_c0:	chroma noise reduction config. &ipu3_uapi_yuvp1_chnr_config
2484dc794d3dSSakari Ailus  * @y_ee_nr:	y edge enhancement and noise reduction config.
2485dc794d3dSSakari Ailus  *		&ipu3_uapi_yuvp1_y_ee_nr_config
2486dc794d3dSSakari Ailus  * @yds:	y down scaler config. See &ipu3_uapi_yuvp1_yds_config
2487dc794d3dSSakari Ailus  * @chnr:	chroma noise reduction config. See &ipu3_uapi_yuvp1_chnr_config
2488dc794d3dSSakari Ailus  * @reserved1: reserved
2489dc794d3dSSakari Ailus  * @yds2:	y channel down scaler config. See &ipu3_uapi_yuvp1_yds_config
2490dc794d3dSSakari Ailus  * @tcc:	total color correction config as defined in struct
2491dc794d3dSSakari Ailus  *		&ipu3_uapi_yuvp2_tcc_static_config
2492dc794d3dSSakari Ailus  * @reserved2: reserved
2493dc794d3dSSakari Ailus  * @anr:	advanced noise reduction config.See &ipu3_uapi_anr_config
2494dc794d3dSSakari Ailus  * @awb_fr:	AWB filter response config. See ipu3_uapi_awb_fr_config
2495dc794d3dSSakari Ailus  * @ae:	auto exposure config  As specified by &ipu3_uapi_ae_config
2496dc794d3dSSakari Ailus  * @af:	auto focus config. As specified by &ipu3_uapi_af_config
2497dc794d3dSSakari Ailus  * @awb:	auto white balance config. As specified by &ipu3_uapi_awb_config
2498dc794d3dSSakari Ailus  */
2499dc794d3dSSakari Ailus struct ipu3_uapi_acc_param {
2500dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config bnr;
2501dc794d3dSSakari Ailus 	struct ipu3_uapi_bnr_static_config_green_disparity
2502dc794d3dSSakari Ailus 				green_disparity __attribute__((aligned(32)));
2503dc794d3dSSakari Ailus 	struct ipu3_uapi_dm_config dm __attribute__((aligned(32)));
2504dc794d3dSSakari Ailus 	struct ipu3_uapi_ccm_mat_config ccm __attribute__((aligned(32)));
2505dc794d3dSSakari Ailus 	struct ipu3_uapi_gamma_config gamma __attribute__((aligned(32)));
2506dc794d3dSSakari Ailus 	struct ipu3_uapi_csc_mat_config csc __attribute__((aligned(32)));
2507dc794d3dSSakari Ailus 	struct ipu3_uapi_cds_params cds __attribute__((aligned(32)));
2508dc794d3dSSakari Ailus 	struct ipu3_uapi_shd_config shd __attribute__((aligned(32)));
2509dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_iefd_config iefd __attribute__((aligned(32)));
2510dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_yds_config yds_c0 __attribute__((aligned(32)));
2511dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_chnr_config chnr_c0 __attribute__((aligned(32)));
2512dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_y_ee_nr_config y_ee_nr __attribute__((aligned(32)));
2513dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_yds_config yds __attribute__((aligned(32)));
2514dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_chnr_config chnr __attribute__((aligned(32)));
2515dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp1_yds_config yds2 __attribute__((aligned(32)));
2516dc794d3dSSakari Ailus 	struct ipu3_uapi_yuvp2_tcc_static_config tcc __attribute__((aligned(32)));
2517dc794d3dSSakari Ailus 	struct ipu3_uapi_anr_config anr;
2518dc794d3dSSakari Ailus 	struct ipu3_uapi_awb_fr_config_s awb_fr;
2519dc794d3dSSakari Ailus 	struct ipu3_uapi_ae_config ae;
2520dc794d3dSSakari Ailus 	struct ipu3_uapi_af_config_s af;
2521dc794d3dSSakari Ailus 	struct ipu3_uapi_awb_config awb;
2522dc794d3dSSakari Ailus } __packed;
2523dc794d3dSSakari Ailus 
2524dc794d3dSSakari Ailus /**
2525dc794d3dSSakari Ailus  * struct ipu3_uapi_isp_lin_vmem_params - Linearization parameters
2526dc794d3dSSakari Ailus  *
2527dc794d3dSSakari Ailus  * @lin_lutlow_gr: linearization look-up table for GR channel interpolation.
2528dc794d3dSSakari Ailus  * @lin_lutlow_r: linearization look-up table for R channel interpolation.
2529dc794d3dSSakari Ailus  * @lin_lutlow_b: linearization look-up table for B channel interpolation.
2530dc794d3dSSakari Ailus  * @lin_lutlow_gb: linearization look-up table for GB channel interpolation.
2531dc794d3dSSakari Ailus  *			lin_lutlow_gr / lin_lutlow_r / lin_lutlow_b /
2532dc794d3dSSakari Ailus  *			lin_lutlow_gb <= LIN_MAX_VALUE - 1.
2533dc794d3dSSakari Ailus  * @lin_lutdif_gr:	lin_lutlow_gr[i+1] - lin_lutlow_gr[i].
2534dc794d3dSSakari Ailus  * @lin_lutdif_r:	lin_lutlow_r[i+1] - lin_lutlow_r[i].
2535dc794d3dSSakari Ailus  * @lin_lutdif_b:	lin_lutlow_b[i+1] - lin_lutlow_b[i].
2536dc794d3dSSakari Ailus  * @lin_lutdif_gb:	lin_lutlow_gb[i+1] - lin_lutlow_gb[i].
2537dc794d3dSSakari Ailus  */
2538dc794d3dSSakari Ailus struct ipu3_uapi_isp_lin_vmem_params {
2539dc794d3dSSakari Ailus 	__s16 lin_lutlow_gr[IPU3_UAPI_LIN_LUT_SIZE];
2540dc794d3dSSakari Ailus 	__s16 lin_lutlow_r[IPU3_UAPI_LIN_LUT_SIZE];
2541dc794d3dSSakari Ailus 	__s16 lin_lutlow_b[IPU3_UAPI_LIN_LUT_SIZE];
2542dc794d3dSSakari Ailus 	__s16 lin_lutlow_gb[IPU3_UAPI_LIN_LUT_SIZE];
2543dc794d3dSSakari Ailus 	__s16 lin_lutdif_gr[IPU3_UAPI_LIN_LUT_SIZE];
2544dc794d3dSSakari Ailus 	__s16 lin_lutdif_r[IPU3_UAPI_LIN_LUT_SIZE];
2545dc794d3dSSakari Ailus 	__s16 lin_lutdif_b[IPU3_UAPI_LIN_LUT_SIZE];
2546dc794d3dSSakari Ailus 	__s16 lin_lutdif_gb[IPU3_UAPI_LIN_LUT_SIZE];
2547dc794d3dSSakari Ailus } __packed;
2548dc794d3dSSakari Ailus 
2549dc794d3dSSakari Ailus /* Temporal Noise Reduction */
2550dc794d3dSSakari Ailus 
2551dc794d3dSSakari Ailus /**
2552dc794d3dSSakari Ailus  * struct ipu3_uapi_isp_tnr3_vmem_params - Temporal noise reduction vector
2553dc794d3dSSakari Ailus  *					   memory parameters
2554dc794d3dSSakari Ailus  *
2555dc794d3dSSakari Ailus  * @slope: slope setting in interpolation curve for temporal noise reduction.
2556dc794d3dSSakari Ailus  * @reserved1: reserved
2557dc794d3dSSakari Ailus  * @sigma: knee point setting in interpolation curve for temporal
2558dc794d3dSSakari Ailus  *	   noise reduction.
2559dc794d3dSSakari Ailus  * @reserved2: reserved
2560dc794d3dSSakari Ailus  */
2561dc794d3dSSakari Ailus struct ipu3_uapi_isp_tnr3_vmem_params {
2562dc794d3dSSakari Ailus 	__u16 slope[IPU3_UAPI_ISP_TNR3_VMEM_LEN];
2563dc794d3dSSakari Ailus 	__u16 reserved1[IPU3_UAPI_ISP_VEC_ELEMS
2564dc794d3dSSakari Ailus 						- IPU3_UAPI_ISP_TNR3_VMEM_LEN];
2565dc794d3dSSakari Ailus 	__u16 sigma[IPU3_UAPI_ISP_TNR3_VMEM_LEN];
2566dc794d3dSSakari Ailus 	__u16 reserved2[IPU3_UAPI_ISP_VEC_ELEMS
2567dc794d3dSSakari Ailus 						- IPU3_UAPI_ISP_TNR3_VMEM_LEN];
2568dc794d3dSSakari Ailus } __packed;
2569dc794d3dSSakari Ailus 
2570dc794d3dSSakari Ailus /**
2571dc794d3dSSakari Ailus  * struct ipu3_uapi_isp_tnr3_params - Temporal noise reduction v3 parameters
2572dc794d3dSSakari Ailus  *
2573dc794d3dSSakari Ailus  * @knee_y1: Knee point TNR3 assumes standard deviation of Y,U and
2574dc794d3dSSakari Ailus  *	V at Y1 are TnrY1_Sigma_Y, U and V.
2575dc794d3dSSakari Ailus  * @knee_y2: Knee point TNR3 assumes standard deviation of Y,U and
2576dc794d3dSSakari Ailus  *		V at Y2 are TnrY2_Sigma_Y, U and V.
2577dc794d3dSSakari Ailus  * @maxfb_y: Max feedback gain for Y
2578dc794d3dSSakari Ailus  * @maxfb_u: Max feedback gain for U
2579dc794d3dSSakari Ailus  * @maxfb_v: Max feedback gain for V
2580dc794d3dSSakari Ailus  * @round_adj_y: rounding Adjust for Y
2581dc794d3dSSakari Ailus  * @round_adj_u: rounding Adjust for U
2582dc794d3dSSakari Ailus  * @round_adj_v: rounding Adjust for V
2583dc794d3dSSakari Ailus  * @ref_buf_select: selection of the reference frame buffer to be used.
2584dc794d3dSSakari Ailus  */
2585dc794d3dSSakari Ailus struct ipu3_uapi_isp_tnr3_params {
2586dc794d3dSSakari Ailus 	__u32 knee_y1;
2587dc794d3dSSakari Ailus 	__u32 knee_y2;
2588dc794d3dSSakari Ailus 	__u32 maxfb_y;
2589dc794d3dSSakari Ailus 	__u32 maxfb_u;
2590dc794d3dSSakari Ailus 	__u32 maxfb_v;
2591dc794d3dSSakari Ailus 	__u32 round_adj_y;
2592dc794d3dSSakari Ailus 	__u32 round_adj_u;
2593dc794d3dSSakari Ailus 	__u32 round_adj_v;
2594dc794d3dSSakari Ailus 	__u32 ref_buf_select;
2595dc794d3dSSakari Ailus } __packed;
2596dc794d3dSSakari Ailus 
2597dc794d3dSSakari Ailus /* Extreme Noise Reduction version 3 */
2598dc794d3dSSakari Ailus 
2599dc794d3dSSakari Ailus /**
2600dc794d3dSSakari Ailus  * struct ipu3_uapi_isp_xnr3_vmem_params - Extreme noise reduction v3
2601dc794d3dSSakari Ailus  *					   vector memory parameters
2602dc794d3dSSakari Ailus  *
2603dc794d3dSSakari Ailus  * @x: xnr3 parameters.
2604dc794d3dSSakari Ailus  * @a: xnr3 parameters.
2605dc794d3dSSakari Ailus  * @b: xnr3 parameters.
2606dc794d3dSSakari Ailus  * @c: xnr3 parameters.
2607dc794d3dSSakari Ailus  */
2608dc794d3dSSakari Ailus struct ipu3_uapi_isp_xnr3_vmem_params {
2609dc794d3dSSakari Ailus 	__u16 x[IPU3_UAPI_ISP_VEC_ELEMS];
2610dc794d3dSSakari Ailus 	__u16 a[IPU3_UAPI_ISP_VEC_ELEMS];
2611dc794d3dSSakari Ailus 	__u16 b[IPU3_UAPI_ISP_VEC_ELEMS];
2612dc794d3dSSakari Ailus 	__u16 c[IPU3_UAPI_ISP_VEC_ELEMS];
2613dc794d3dSSakari Ailus } __packed;
2614dc794d3dSSakari Ailus 
2615dc794d3dSSakari Ailus /**
2616dc794d3dSSakari Ailus  * struct ipu3_uapi_xnr3_alpha_params - Extreme noise reduction v3
2617dc794d3dSSakari Ailus  *					alpha tuning parameters
2618dc794d3dSSakari Ailus  *
2619dc794d3dSSakari Ailus  * @y0: Sigma for Y range similarity in dark area.
2620dc794d3dSSakari Ailus  * @u0: Sigma for U range similarity in dark area.
2621dc794d3dSSakari Ailus  * @v0: Sigma for V range similarity in dark area.
2622dc794d3dSSakari Ailus  * @ydiff: Sigma difference for Y between bright area and dark area.
2623dc794d3dSSakari Ailus  * @udiff: Sigma difference for U between bright area and dark area.
2624dc794d3dSSakari Ailus  * @vdiff: Sigma difference for V between bright area and dark area.
2625dc794d3dSSakari Ailus  */
2626dc794d3dSSakari Ailus struct ipu3_uapi_xnr3_alpha_params {
2627dc794d3dSSakari Ailus 	__u32 y0;
2628dc794d3dSSakari Ailus 	__u32 u0;
2629dc794d3dSSakari Ailus 	__u32 v0;
2630dc794d3dSSakari Ailus 	__u32 ydiff;
2631dc794d3dSSakari Ailus 	__u32 udiff;
2632dc794d3dSSakari Ailus 	__u32 vdiff;
2633dc794d3dSSakari Ailus } __packed;
2634dc794d3dSSakari Ailus 
2635dc794d3dSSakari Ailus /**
2636dc794d3dSSakari Ailus  * struct ipu3_uapi_xnr3_coring_params - Extreme noise reduction v3
2637dc794d3dSSakari Ailus  *					 coring parameters
2638dc794d3dSSakari Ailus  *
2639dc794d3dSSakari Ailus  * @u0: Coring Threshold of U channel in dark area.
2640dc794d3dSSakari Ailus  * @v0: Coring Threshold of V channel in dark area.
2641dc794d3dSSakari Ailus  * @udiff: Threshold difference of U channel between bright and dark area.
2642dc794d3dSSakari Ailus  * @vdiff: Threshold difference of V channel between bright and dark area.
2643dc794d3dSSakari Ailus  */
2644dc794d3dSSakari Ailus struct ipu3_uapi_xnr3_coring_params {
2645dc794d3dSSakari Ailus 	__u32 u0;
2646dc794d3dSSakari Ailus 	__u32 v0;
2647dc794d3dSSakari Ailus 	__u32 udiff;
2648dc794d3dSSakari Ailus 	__u32 vdiff;
2649dc794d3dSSakari Ailus } __packed;
2650dc794d3dSSakari Ailus 
2651dc794d3dSSakari Ailus /**
2652dc794d3dSSakari Ailus  * struct ipu3_uapi_xnr3_blending_params - Blending factor
2653dc794d3dSSakari Ailus  *
2654dc794d3dSSakari Ailus  * @strength: The factor for blending output with input. This is tuning
2655dc794d3dSSakari Ailus  *	      parameterHigher values lead to more aggressive XNR operation.
2656dc794d3dSSakari Ailus  */
2657dc794d3dSSakari Ailus struct ipu3_uapi_xnr3_blending_params {
2658dc794d3dSSakari Ailus 	__u32 strength;
2659dc794d3dSSakari Ailus } __packed;
2660dc794d3dSSakari Ailus 
2661dc794d3dSSakari Ailus /**
2662dc794d3dSSakari Ailus  * struct ipu3_uapi_isp_xnr3_params - Extreme noise reduction v3 parameters
2663dc794d3dSSakari Ailus  *
2664dc794d3dSSakari Ailus  * @alpha: parameters for xnr3 alpha. See &ipu3_uapi_xnr3_alpha_params
2665dc794d3dSSakari Ailus  * @coring: parameters for xnr3 coring. See &ipu3_uapi_xnr3_coring_params
2666dc794d3dSSakari Ailus  * @blending: parameters for xnr3 blending. See &ipu3_uapi_xnr3_blending_params
2667dc794d3dSSakari Ailus  */
2668dc794d3dSSakari Ailus struct ipu3_uapi_isp_xnr3_params {
2669dc794d3dSSakari Ailus 	struct ipu3_uapi_xnr3_alpha_params alpha;
2670dc794d3dSSakari Ailus 	struct ipu3_uapi_xnr3_coring_params coring;
2671dc794d3dSSakari Ailus 	struct ipu3_uapi_xnr3_blending_params blending;
2672dc794d3dSSakari Ailus } __packed;
2673dc794d3dSSakari Ailus 
2674dc794d3dSSakari Ailus /***** Obgrid (optical black level compensation) table entry *****/
2675dc794d3dSSakari Ailus 
2676dc794d3dSSakari Ailus /**
2677dc794d3dSSakari Ailus  * struct ipu3_uapi_obgrid_param - Optical black level compensation parameters
2678dc794d3dSSakari Ailus  *
2679dc794d3dSSakari Ailus  * @gr: Grid table values for color GR
2680dc794d3dSSakari Ailus  * @r: Grid table values for color R
2681dc794d3dSSakari Ailus  * @b: Grid table values for color B
2682dc794d3dSSakari Ailus  * @gb: Grid table values for color GB
2683dc794d3dSSakari Ailus  *
2684dc794d3dSSakari Ailus  * Black level is different for red, green, and blue channels. So black level
2685dc794d3dSSakari Ailus  * compensation is different per channel.
2686dc794d3dSSakari Ailus  */
2687dc794d3dSSakari Ailus struct ipu3_uapi_obgrid_param {
2688dc794d3dSSakari Ailus 	__u16 gr;
2689dc794d3dSSakari Ailus 	__u16 r;
2690dc794d3dSSakari Ailus 	__u16 b;
2691dc794d3dSSakari Ailus 	__u16 gb;
2692dc794d3dSSakari Ailus } __packed;
2693dc794d3dSSakari Ailus 
2694dc794d3dSSakari Ailus /******************* V4L2_META_FMT_IPU3_PARAMS *******************/
2695dc794d3dSSakari Ailus 
2696dc794d3dSSakari Ailus /**
2697dc794d3dSSakari Ailus  * struct ipu3_uapi_flags - bits to indicate which pipeline needs update
2698dc794d3dSSakari Ailus  *
2699dc794d3dSSakari Ailus  * @gdc: 0 = no update, 1 = update.
2700dc794d3dSSakari Ailus  * @obgrid: 0 = no update, 1 = update.
2701dc794d3dSSakari Ailus  * @reserved1: Not used.
2702dc794d3dSSakari Ailus  * @acc_bnr: 0 = no update, 1 = update.
2703dc794d3dSSakari Ailus  * @acc_green_disparity: 0 = no update, 1 = update.
2704dc794d3dSSakari Ailus  * @acc_dm: 0 = no update, 1 = update.
2705dc794d3dSSakari Ailus  * @acc_ccm: 0 = no update, 1 = update.
2706dc794d3dSSakari Ailus  * @acc_gamma: 0 = no update, 1 = update.
2707dc794d3dSSakari Ailus  * @acc_csc: 0 = no update, 1 = update.
2708dc794d3dSSakari Ailus  * @acc_cds: 0 = no update, 1 = update.
2709dc794d3dSSakari Ailus  * @acc_shd: 0 = no update, 1 = update.
2710dc794d3dSSakari Ailus  * @reserved2: Not used.
2711dc794d3dSSakari Ailus  * @acc_iefd: 0 = no update, 1 = update.
2712dc794d3dSSakari Ailus  * @acc_yds_c0: 0 = no update, 1 = update.
2713dc794d3dSSakari Ailus  * @acc_chnr_c0: 0 = no update, 1 = update.
2714dc794d3dSSakari Ailus  * @acc_y_ee_nr: 0 = no update, 1 = update.
2715dc794d3dSSakari Ailus  * @acc_yds: 0 = no update, 1 = update.
2716dc794d3dSSakari Ailus  * @acc_chnr: 0 = no update, 1 = update.
2717dc794d3dSSakari Ailus  * @acc_ytm: 0 = no update, 1 = update.
2718dc794d3dSSakari Ailus  * @acc_yds2: 0 = no update, 1 = update.
2719dc794d3dSSakari Ailus  * @acc_tcc: 0 = no update, 1 = update.
2720dc794d3dSSakari Ailus  * @acc_dpc: 0 = no update, 1 = update.
2721dc794d3dSSakari Ailus  * @acc_bds: 0 = no update, 1 = update.
2722dc794d3dSSakari Ailus  * @acc_anr: 0 = no update, 1 = update.
2723dc794d3dSSakari Ailus  * @acc_awb_fr: 0 = no update, 1 = update.
2724dc794d3dSSakari Ailus  * @acc_ae: 0 = no update, 1 = update.
2725dc794d3dSSakari Ailus  * @acc_af: 0 = no update, 1 = update.
2726dc794d3dSSakari Ailus  * @acc_awb: 0 = no update, 1 = update.
2727dc794d3dSSakari Ailus  * @__acc_osys: 0 = no update, 1 = update.
2728dc794d3dSSakari Ailus  * @reserved3: Not used.
2729dc794d3dSSakari Ailus  * @lin_vmem_params: 0 = no update, 1 = update.
2730dc794d3dSSakari Ailus  * @tnr3_vmem_params: 0 = no update, 1 = update.
2731dc794d3dSSakari Ailus  * @xnr3_vmem_params: 0 = no update, 1 = update.
2732dc794d3dSSakari Ailus  * @tnr3_dmem_params: 0 = no update, 1 = update.
2733dc794d3dSSakari Ailus  * @xnr3_dmem_params: 0 = no update, 1 = update.
2734dc794d3dSSakari Ailus  * @reserved4: Not used.
2735dc794d3dSSakari Ailus  * @obgrid_param: 0 = no update, 1 = update.
2736dc794d3dSSakari Ailus  * @reserved5: Not used.
2737dc794d3dSSakari Ailus  */
2738dc794d3dSSakari Ailus struct ipu3_uapi_flags {
2739dc794d3dSSakari Ailus 	__u32 gdc:1;
2740dc794d3dSSakari Ailus 	__u32 obgrid:1;
2741dc794d3dSSakari Ailus 	__u32 reserved1:30;
2742dc794d3dSSakari Ailus 
2743dc794d3dSSakari Ailus 	__u32 acc_bnr:1;
2744dc794d3dSSakari Ailus 	__u32 acc_green_disparity:1;
2745dc794d3dSSakari Ailus 	__u32 acc_dm:1;
2746dc794d3dSSakari Ailus 	__u32 acc_ccm:1;
2747dc794d3dSSakari Ailus 	__u32 acc_gamma:1;
2748dc794d3dSSakari Ailus 	__u32 acc_csc:1;
2749dc794d3dSSakari Ailus 	__u32 acc_cds:1;
2750dc794d3dSSakari Ailus 	__u32 acc_shd:1;
2751dc794d3dSSakari Ailus 	__u32 reserved2:2;
2752dc794d3dSSakari Ailus 	__u32 acc_iefd:1;
2753dc794d3dSSakari Ailus 	__u32 acc_yds_c0:1;
2754dc794d3dSSakari Ailus 	__u32 acc_chnr_c0:1;
2755dc794d3dSSakari Ailus 	__u32 acc_y_ee_nr:1;
2756dc794d3dSSakari Ailus 	__u32 acc_yds:1;
2757dc794d3dSSakari Ailus 	__u32 acc_chnr:1;
2758dc794d3dSSakari Ailus 	__u32 acc_ytm:1;
2759dc794d3dSSakari Ailus 	__u32 acc_yds2:1;
2760dc794d3dSSakari Ailus 	__u32 acc_tcc:1;
2761dc794d3dSSakari Ailus 	__u32 acc_dpc:1;
2762dc794d3dSSakari Ailus 	__u32 acc_bds:1;
2763dc794d3dSSakari Ailus 	__u32 acc_anr:1;
2764dc794d3dSSakari Ailus 	__u32 acc_awb_fr:1;
2765dc794d3dSSakari Ailus 	__u32 acc_ae:1;
2766dc794d3dSSakari Ailus 	__u32 acc_af:1;
2767dc794d3dSSakari Ailus 	__u32 acc_awb:1;
2768dc794d3dSSakari Ailus 	__u32 reserved3:4;
2769dc794d3dSSakari Ailus 
2770dc794d3dSSakari Ailus 	__u32 lin_vmem_params:1;
2771dc794d3dSSakari Ailus 	__u32 tnr3_vmem_params:1;
2772dc794d3dSSakari Ailus 	__u32 xnr3_vmem_params:1;
2773dc794d3dSSakari Ailus 	__u32 tnr3_dmem_params:1;
2774dc794d3dSSakari Ailus 	__u32 xnr3_dmem_params:1;
2775dc794d3dSSakari Ailus 	__u32 reserved4:1;
2776dc794d3dSSakari Ailus 	__u32 obgrid_param:1;
2777dc794d3dSSakari Ailus 	__u32 reserved5:25;
2778dc794d3dSSakari Ailus } __packed;
2779dc794d3dSSakari Ailus 
2780dc794d3dSSakari Ailus /**
2781dc794d3dSSakari Ailus  * struct ipu3_uapi_params - V4L2_META_FMT_IPU3_PARAMS
2782dc794d3dSSakari Ailus  *
2783dc794d3dSSakari Ailus  * @use:	select which parameters to apply, see &ipu3_uapi_flags
2784dc794d3dSSakari Ailus  * @acc_param:	ACC parameters, as specified by &ipu3_uapi_acc_param
2785dc794d3dSSakari Ailus  * @lin_vmem_params:	linearization VMEM, as specified by
2786dc794d3dSSakari Ailus  *			&ipu3_uapi_isp_lin_vmem_params
2787dc794d3dSSakari Ailus  * @tnr3_vmem_params:	tnr3 VMEM as specified by
2788dc794d3dSSakari Ailus  *			&ipu3_uapi_isp_tnr3_vmem_params
2789dc794d3dSSakari Ailus  * @xnr3_vmem_params:	xnr3 VMEM as specified by
2790dc794d3dSSakari Ailus  *			&ipu3_uapi_isp_xnr3_vmem_params
2791dc794d3dSSakari Ailus  * @tnr3_dmem_params:	tnr3 DMEM as specified by &ipu3_uapi_isp_tnr3_params
2792dc794d3dSSakari Ailus  * @xnr3_dmem_params:	xnr3 DMEM as specified by &ipu3_uapi_isp_xnr3_params
2793dc794d3dSSakari Ailus  * @obgrid_param:	obgrid parameters as specified by
2794dc794d3dSSakari Ailus  *			&ipu3_uapi_obgrid_param
2795dc794d3dSSakari Ailus  *
2796dc794d3dSSakari Ailus  * The video queue "parameters" is of format V4L2_META_FMT_IPU3_PARAMS.
2797dc794d3dSSakari Ailus  * This is a "single plane" v4l2_meta_format using V4L2_BUF_TYPE_META_OUTPUT.
2798dc794d3dSSakari Ailus  *
2799dc794d3dSSakari Ailus  * struct ipu3_uapi_params as defined below contains a lot of parameters and
2800dc794d3dSSakari Ailus  * ipu3_uapi_flags selects which parameters to apply.
2801dc794d3dSSakari Ailus  */
2802dc794d3dSSakari Ailus struct ipu3_uapi_params {
2803dc794d3dSSakari Ailus 	/* Flags which of the settings below are to be applied */
2804dc794d3dSSakari Ailus 	struct ipu3_uapi_flags use __attribute__((aligned(32)));
2805dc794d3dSSakari Ailus 
2806dc794d3dSSakari Ailus 	/* Accelerator cluster parameters */
2807dc794d3dSSakari Ailus 	struct ipu3_uapi_acc_param acc_param;
2808dc794d3dSSakari Ailus 
2809dc794d3dSSakari Ailus 	/* ISP vector address space parameters */
2810dc794d3dSSakari Ailus 	struct ipu3_uapi_isp_lin_vmem_params lin_vmem_params;
2811dc794d3dSSakari Ailus 	struct ipu3_uapi_isp_tnr3_vmem_params tnr3_vmem_params;
2812dc794d3dSSakari Ailus 	struct ipu3_uapi_isp_xnr3_vmem_params xnr3_vmem_params;
2813dc794d3dSSakari Ailus 
2814dc794d3dSSakari Ailus 	/* ISP data memory (DMEM) parameters */
2815dc794d3dSSakari Ailus 	struct ipu3_uapi_isp_tnr3_params tnr3_dmem_params;
2816dc794d3dSSakari Ailus 	struct ipu3_uapi_isp_xnr3_params xnr3_dmem_params;
2817dc794d3dSSakari Ailus 
2818dc794d3dSSakari Ailus 	/* Optical black level compensation */
2819dc794d3dSSakari Ailus 	struct ipu3_uapi_obgrid_param obgrid_param;
2820dc794d3dSSakari Ailus } __packed;
2821dc794d3dSSakari Ailus 
2822dc794d3dSSakari Ailus #endif /* __IPU3_UAPI_H */
2823