1e91f8401SRodrigo Siqueira======================
2e91f8401SRodrigo SiqueiraAMDgpu Display Manager
3e91f8401SRodrigo Siqueira======================
4e91f8401SRodrigo Siqueira
5e91f8401SRodrigo Siqueira.. contents:: Table of Contents
6e91f8401SRodrigo Siqueira    :depth: 3
7e91f8401SRodrigo Siqueira
8e91f8401SRodrigo Siqueira.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9e91f8401SRodrigo Siqueira   :doc: overview
10e91f8401SRodrigo Siqueira
11e91f8401SRodrigo Siqueira.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
12e91f8401SRodrigo Siqueira   :internal:
13e91f8401SRodrigo Siqueira
14e91f8401SRodrigo SiqueiraLifecycle
15e91f8401SRodrigo Siqueira=========
16e91f8401SRodrigo Siqueira
17e91f8401SRodrigo Siqueira.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
18e91f8401SRodrigo Siqueira   :doc: DM Lifecycle
19e91f8401SRodrigo Siqueira
20e91f8401SRodrigo Siqueira.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
21e91f8401SRodrigo Siqueira   :functions: dm_hw_init dm_hw_fini
22e91f8401SRodrigo Siqueira
23e91f8401SRodrigo SiqueiraInterrupts
24e91f8401SRodrigo Siqueira==========
25e91f8401SRodrigo Siqueira
26e91f8401SRodrigo Siqueira.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
27e91f8401SRodrigo Siqueira   :doc: overview
28e91f8401SRodrigo Siqueira
29e91f8401SRodrigo Siqueira.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
30e91f8401SRodrigo Siqueira   :internal:
31e91f8401SRodrigo Siqueira
32e91f8401SRodrigo Siqueira.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
33e91f8401SRodrigo Siqueira   :functions: register_hpd_handlers dm_crtc_high_irq dm_pflip_high_irq
34e91f8401SRodrigo Siqueira
35e91f8401SRodrigo SiqueiraAtomic Implementation
36e91f8401SRodrigo Siqueira=====================
37e91f8401SRodrigo Siqueira
38e91f8401SRodrigo Siqueira.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
39e91f8401SRodrigo Siqueira   :doc: atomic
40e91f8401SRodrigo Siqueira
41e91f8401SRodrigo Siqueira.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
42e91f8401SRodrigo Siqueira   :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
43cdeec9a1SMelissa Wen
44cdeec9a1SMelissa WenColor Management Properties
45cdeec9a1SMelissa Wen===========================
46cdeec9a1SMelissa Wen
47cdeec9a1SMelissa Wen.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
48cdeec9a1SMelissa Wen   :doc: overview
49cdeec9a1SMelissa Wen
50cdeec9a1SMelissa Wen.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
51cdeec9a1SMelissa Wen   :internal:
5278e16ac1SMelissa Wen
5378e16ac1SMelissa Wen
5478e16ac1SMelissa WenDC Color Capabilities between DCN generations
5578e16ac1SMelissa Wen---------------------------------------------
5678e16ac1SMelissa Wen
5778e16ac1SMelissa WenDRM/KMS framework defines three CRTC color correction properties: degamma,
5878e16ac1SMelissa Wencolor transformation matrix (CTM) and gamma, and two properties for degamma and
5978e16ac1SMelissa Wengamma LUT sizes. AMD DC programs some of the color correction features
6078e16ac1SMelissa Wenpre-blending but DRM/KMS has not per-plane color correction properties.
6178e16ac1SMelissa Wen
6278e16ac1SMelissa WenIn general, the DRM CRTC color properties are programmed to DC, as follows:
6378e16ac1SMelissa WenCRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is
6478e16ac1SMelissa Wenprogrammed after blending, it is mapped to DPP hw blocks (pre-blending). Other
6578e16ac1SMelissa Wencolor caps available in the hw is not currently exposed by DRM interface and
6678e16ac1SMelissa Wenare bypassed.
6778e16ac1SMelissa Wen
6878e16ac1SMelissa Wen.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
6978e16ac1SMelissa Wen   :doc: color-management-caps
7078e16ac1SMelissa Wen
7178e16ac1SMelissa Wen.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
7278e16ac1SMelissa Wen   :internal:
7378e16ac1SMelissa Wen
7478e16ac1SMelissa WenThe color pipeline has undergone major changes between DCN hardware
7578e16ac1SMelissa Wengenerations. What's possible to do before and after blending depends on
7678e16ac1SMelissa Wenhardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families
7778e16ac1SMelissa Wenschemas.
7878e16ac1SMelissa Wen
7978e16ac1SMelissa Wen**DCN 2.0 family color caps and mapping**
8078e16ac1SMelissa Wen
8178e16ac1SMelissa Wen.. kernel-figure:: dcn2_cm_drm_current.svg
8278e16ac1SMelissa Wen
8378e16ac1SMelissa Wen**DCN 3.0 family color caps and mapping**
8478e16ac1SMelissa Wen
8578e16ac1SMelissa Wen.. kernel-figure:: dcn3_cm_drm_current.svg
8633fa4f1dSMelissa Wen
8733fa4f1dSMelissa WenBlend Mode Properties
8833fa4f1dSMelissa Wen=====================
8933fa4f1dSMelissa Wen
9033fa4f1dSMelissa WenPixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
9133fa4f1dSMelissa Wendescribes how pixels from a foreground plane (fg) are composited with the
9233fa4f1dSMelissa Wenbackground plane (bg). Here, we present main concepts of DRM blend mode to help
9333fa4f1dSMelissa Wento understand how this property is mapped to AMD DC interface. See more about
9433fa4f1dSMelissa Wenthis DRM property and the alpha blending equations in :ref:`DRM Plane
9533fa4f1dSMelissa WenComposition Properties <plane_composition_properties>`.
9633fa4f1dSMelissa Wen
9733fa4f1dSMelissa WenBasically, a blend mode sets the alpha blending equation for plane
9833fa4f1dSMelissa Wencomposition that fits the mode in which the alpha channel affects the state of
9933fa4f1dSMelissa Wenpixel color values and, therefore, the resulted pixel color. For
10033fa4f1dSMelissa Wenexample, consider the following elements of the alpha blending equation:
10133fa4f1dSMelissa Wen
10233fa4f1dSMelissa Wen- *fg.rgb*: Each of the RGB component values from the foreground's pixel.
10333fa4f1dSMelissa Wen- *fg.alpha*: Alpha component value from the foreground's pixel.
10433fa4f1dSMelissa Wen- *bg.rgb*: Each of the RGB component values from the background.
10533fa4f1dSMelissa Wen- *plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see
10633fa4f1dSMelissa Wen  more in :ref:`DRM Plane Composition Properties <plane_composition_properties>`.
10733fa4f1dSMelissa Wen
10833fa4f1dSMelissa Wenin the basic alpha blending equation::
10933fa4f1dSMelissa Wen
11033fa4f1dSMelissa Wen   out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb
11133fa4f1dSMelissa Wen
11233fa4f1dSMelissa Wenthe alpha channel value of each pixel in a plane is ignored and only the plane
11333fa4f1dSMelissa Wenalpha affects the resulted pixel color values.
11433fa4f1dSMelissa Wen
11533fa4f1dSMelissa WenDRM has three blend mode to define the blend formula in the plane composition:
11633fa4f1dSMelissa Wen
11733fa4f1dSMelissa Wen* **None**: Blend formula that ignores the pixel alpha.
11833fa4f1dSMelissa Wen
11933fa4f1dSMelissa Wen* **Pre-multiplied**: Blend formula that assumes the pixel color values in a
12033fa4f1dSMelissa Wen  plane was already pre-multiplied by its own alpha channel before storage.
12133fa4f1dSMelissa Wen
12233fa4f1dSMelissa Wen* **Coverage**: Blend formula that assumes the pixel color values were not
12333fa4f1dSMelissa Wen  pre-multiplied with the alpha channel values.
12433fa4f1dSMelissa Wen
12533fa4f1dSMelissa Wenand pre-multiplied is the default pixel blend mode, that means, when no blend
12633fa4f1dSMelissa Wenmode property is created or defined, DRM considers the plane's pixels has
12733fa4f1dSMelissa Wenpre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test
12833fa4f1dSMelissa Wenprovides a set of subtests to verify plane alpha and blend mode properties.
12933fa4f1dSMelissa Wen
13033fa4f1dSMelissa WenThe DRM blend mode and its elements are then mapped by AMDGPU display manager
13133fa4f1dSMelissa Wen(DM) to program the blending configuration of the Multiple Pipe/Plane Combined
13233fa4f1dSMelissa Wen(MPC), as follows:
13333fa4f1dSMelissa Wen
13433fa4f1dSMelissa Wen.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
13533fa4f1dSMelissa Wen   :doc: mpc-overview
13633fa4f1dSMelissa Wen
13733fa4f1dSMelissa Wen.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
13833fa4f1dSMelissa Wen   :functions: mpcc_blnd_cfg
13933fa4f1dSMelissa Wen
14033fa4f1dSMelissa WenTherefore, the blending configuration for a single MPCC instance on the MPC
14133fa4f1dSMelissa Wentree is defined by :c:type:`mpcc_blnd_cfg`, where
14233fa4f1dSMelissa Wen:c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to
14333fa4f1dSMelissa Wenset :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is
14433fa4f1dSMelissa Wenmultiplied (true/false), being only true for DRM pre-multiplied blend mode.
14533fa4f1dSMelissa Wen:c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel
14633fa4f1dSMelissa Wenalpha and plane alpha values. It sets one of the three modes for
14733fa4f1dSMelissa Wen:c:type:`MPCC_ALPHA_BLND_MODE`, as described below.
14833fa4f1dSMelissa Wen
14933fa4f1dSMelissa Wen.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
15033fa4f1dSMelissa Wen   :functions: mpcc_alpha_blend_mode
15133fa4f1dSMelissa Wen
15233fa4f1dSMelissa WenDM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM
15333fa4f1dSMelissa Wenblend formula, as follows:
15433fa4f1dSMelissa Wen
15533fa4f1dSMelissa Wen* *MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value
15633fa4f1dSMelissa Wen  from the plane's pixel
15733fa4f1dSMelissa Wen* *MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should
15833fa4f1dSMelissa Wen  be ignored and, therefore, pixel values are not pre-multiplied
15933fa4f1dSMelissa Wen* *MPC global gain* assumes *MPC global alpha* value when both *DRM
16033fa4f1dSMelissa Wen  fg.alpha* and *DRM plane_alpha* participate in the blend equation
16133fa4f1dSMelissa Wen
16233fa4f1dSMelissa WenIn short, *fg.alpha* is ignored by selecting
16333fa4f1dSMelissa Wen:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha *
16433fa4f1dSMelissa Wenfg.alpha) component becomes available by selecting
16533fa4f1dSMelissa Wen:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the
16633fa4f1dSMelissa Wen:c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are
16733fa4f1dSMelissa Wenpre-multiplied by alpha or not.
16833fa4f1dSMelissa Wen
16933fa4f1dSMelissa WenBlend configuration flow
17033fa4f1dSMelissa Wen------------------------
17133fa4f1dSMelissa Wen
17233fa4f1dSMelissa WenThe alpha blending equation is configured from DRM to DC interface by the
17333fa4f1dSMelissa Wenfollowing path:
17433fa4f1dSMelissa Wen
17533fa4f1dSMelissa Wen1. When updating a :c:type:`drm_plane_state <drm_plane_state>`, DM calls
176*8bf0d9cdSDavid Tadokoro   :c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()` that maps
17733fa4f1dSMelissa Wen   :c:type:`drm_plane_state <drm_plane_state>` attributes to
17833fa4f1dSMelissa Wen   :c:type:`dc_plane_info <dc_plane_info>` struct to be handled in the
17933fa4f1dSMelissa Wen   OS-agnostic component (DC).
18033fa4f1dSMelissa Wen
18133fa4f1dSMelissa Wen2. On DC interface, :c:type:`struct mpcc_blnd_cfg <mpcc_blnd_cfg>` programs the
18233fa4f1dSMelissa Wen   MPCC blend configuration considering the :c:type:`dc_plane_info
18333fa4f1dSMelissa Wen   <dc_plane_info>` input from DPP.
184