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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP FMan MAC
10 - Madalin Bucur <madalin.bucur@nxp.com>
13 Each FMan has several MACs, each implementing an Ethernet interface. Earlier
14 versions of FMan used the Datapath Three Speed Ethernet Controller (dTSEC) for
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
16 (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate
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H A Dfsl-fman.txt5 - FMan Node
6 - FMan Port Node
7 - FMan MURAM Node
8 - FMan dTSEC/XGEC/mEMAC Node
9 - FMan IEEE 1588 Node
10 - FMan MDIO Node
11 - Example
14 FMan Node
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 etc.) the FMan node will have child nodes for each of them.
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/openbmc/u-boot/board/freescale/corenet_ds/
H A Deth_superhydra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 * This file handles the board muxing between the Fman Ethernet MACs and
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
13 * and 5 1G interfaces and 10G interface per FMan. Based on the options in
23 * exist, and also which Fman's MACs are routed to which PHYs. So for a given
24 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
38 * values, so those values are hard-coded in the DTS. On the HYDRA board,
[all …]
H A Deth_hydra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 * This file handles the board muxing between the Fman Ethernet MACs and
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
13 * Fman device on a P3041 and P5020, we only support one SGMII card and one
23 * exist, and also which Fman MACs are routed to which PHYs. So for a given
24 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
38 * values, so those values are hard-coded in the DTS. On the HYDRA board,
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_mac.h2 * Copyright 2008-2015 Freescale Semiconductor Inc.
37 #include "fman.h"
62 (u8)((_addr64) >> ((5 - i) * 8)); \
116 /* dTSEC Babbling receive error */
118 /* dTSEC Receive control (pause frame) interrupt */
120 /* dTSEC Graceful transmit stop complete */
122 /* dTSEC Babbling transmit error */
124 /* dTSEC Transmit control (pause frame) interrupt */
126 /* dTSEC Transmit error */
128 /* dTSEC Late collision */
[all …]
H A Dfman_dtsec.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
9 #include "fman.h"
29 #define TBICON_AN_SENSE 0x0100 /* Auto-negotiation sense enable */
68 /* dtsec timestamp event bits */
154 /* dTSEC Memory Map registers */
156 /* dTSEC General Control and Status Registers */
165 u32 tmr_ctrl; /* 0x020 Time-stamp Control register */
166 u32 tmr_pevent; /* 0x024 Time-stamp event register */
173 u32 igaddr[8]; /* 0x080-0x09C Individual/group address */
[all …]
H A Dmac.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
30 MODULE_DESCRIPTION("FSL FMan MAC API based driver");
34 struct fman *fman; member
51 mac_dev->set_exception(mac_dev->fman_mac, in mac_exception()
53 dev_err(mac_dev->dev, "10G MAC got RX FIFO Error = %x\n", ex); in mac_exception()
56 dev_dbg(mac_dev->dev, "%s:%s() -> %d\n", KBUILD_BASENAME ".c", in mac_exception()
68 priv = mac_dev->priv; in fman_set_multi()
71 list_for_each_entry_safe(old_addr, tmp, &priv->mc_addr_list, list) { in fman_set_multi()
72 addr = (enet_addr_t *)old_addr->addr; in fman_set_multi()
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/openbmc/u-boot/board/freescale/p2041rdb/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
9 * are provided by the three on-board PHY or by the standard Freescale
10 * four-port SGMII riser card. We need to change the phy-handle in the
24 #include "../common/fman.h"
61 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
64 * 2) An Fman port
66 * ... update the phy-handle property of the Ethernet node to point to the
69 * The offset of the Fman Ethernet node is also passed in for convenience, but
72 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
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/openbmc/u-boot/board/freescale/b4860qds/
H A Deth_b4860qds.c1 // SPDX-License-Identifier: GPL-2.0+
10 * This file handles the board muxing between the Fman Ethernet MACs and
12 * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
14 * one Fman device on B4860. The SERDES configuration is used to determine
15 * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
16 * to which PHYs. So for a given Fman MAC, there is one and only PHY it
31 #include "../common/fman.h"
61 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & in initialize_lane_to_slot()
140 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", in initialize_lane_to_slot()
159 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & in board_eth_init()
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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman-1-1g-3.dtsi2 * QorIQ FMan 1g port #3 device tree stub [ controller @ offset 0x500000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@500000 {
37 cell-index = <0xb>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x2b>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <3>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
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H A Dqoriq-fman-1-1g-2.dtsi2 * QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x500000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@500000 {
37 cell-index = <0xa>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x2a>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <2>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
[all …]
H A Dqoriq-fman-1-1g-0.dtsi2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x500000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@500000 {
37 cell-index = <0x8>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x28>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <0>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
[all …]
H A Dqoriq-fman-0-1g-2.dtsi2 * QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x400000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@400000 {
37 cell-index = <0xa>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x2a>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <2>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
[all …]
H A Dqoriq-fman-0-1g-1.dtsi2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x400000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@400000 {
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x29>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <1>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
[all …]
H A Dqoriq-fman-1-1g-4.dtsi2 * QorIQ FMan 1g port #4 device tree stub [ controller @ offset 0x500000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@500000 {
37 cell-index = <0xc>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x2c>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <4>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
[all …]
H A Dqoriq-fman-0-1g-0.dtsi2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x400000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@400000 {
37 cell-index = <0x8>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x28>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <0>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
[all …]
H A Dqoriq-fman-0-1g-4.dtsi2 * QorIQ FMan 1g port #4 device tree stub [ controller @ offset 0x400000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@400000 {
37 cell-index = <0xc>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x2c>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <4>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
[all …]
H A Dqoriq-fman-0-1g-3.dtsi2 * QorIQ FMan 1g port #3 device tree stub [ controller @ offset 0x400000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@400000 {
37 cell-index = <0xb>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x2b>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <3>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
[all …]
H A Dqoriq-fman-1-1g-1.dtsi2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ]
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 fman@500000 {
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v2-port-rx";
43 cell-index = <0x29>;
44 compatible = "fsl,fman-v2-port-tx";
49 cell-index = <1>;
50 compatible = "fsl,fman-dtsec";
52 fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
[all …]
/openbmc/u-boot/board/freescale/t1040qds/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
7 * The RGMII PHYs are provided by the two on-board PHY connected to
8 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
9 * PHY or by the standard four-port SGMII riser card (VSC).
22 #include "../common/fman.h"
28 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
29 * Bank 1 -> Lanes A, B, C, D
30 * Bank 2 -> Lanes E, F, G, H
120 struct t1040_qds_mdio *priv = bus->priv; in t1040_qds_mdio_read()
122 t1040_qds_mux_mdio(priv->muxval); in t1040_qds_mdio_read()
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/openbmc/u-boot/drivers/net/fm/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0+
3 # Copyright 2009-2011 Freescale Semiconductor, Inc.
5 obj-y += dtsec.o
6 obj-y += eth.o
7 obj-y += fdt.o
8 obj-y += fm.o
9 obj-y += init.o
10 obj-y += tgec.o
11 obj-y += tgec_phy.o
13 # Soc have FMAN v3 with mEMAC
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H A Dinit.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011-2015 Freescale Semiconductor, Inc.
125 return -1; in fm_port_to_index()
156 if (i == -1) in fm_disable_port()
169 if (i == -1) in fm_enable_port()
180 if (i == -1) in fm_info_set_mdio()
190 if (i == -1) in fm_info_set_phy_address()
197 * Returns the PHY address for a given Fman port
206 if (i == -1) in fm_info_get_phy_address()
207 return -1; in fm_info_get_phy_address()
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/openbmc/u-boot/board/freescale/t104xrdb/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include "../common/fman.h"
29 printf("Initializing Fman\n"); in board_eth_init()
42 int idx = i - FM1_DTSEC1; in board_eth_init()
92 printf("Fman1: DTSEC%u set to unknown interface %i\n", in board_eth_init()
123 phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; in board_eth_init()
143 out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) | in board_eth_init()
/openbmc/linux/Documentation/networking/device_drivers/ethernet/freescale/
H A Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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/openbmc/u-boot/board/freescale/t4qds/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
27 #include "../common/fman.h"
111 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_read()
113 t4240qds_mux_mdio(priv->muxval); in t4240qds_mdio_read()
115 return priv->realbus->read(priv->realbus, addr, devad, regnum); in t4240qds_mdio_read()
121 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_write()
123 t4240qds_mux_mdio(priv->muxval); in t4240qds_mdio_write()
125 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); in t4240qds_mdio_write()
130 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_reset()
132 return priv->realbus->reset(priv->realbus); in t4240qds_mdio_reset()
[all …]

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