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/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_mac.c1 // SPDX-License-Identifier: GPL-2.0
11 * igc_disable_pcie_master - Disables PCI-express master access
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18 * Disables PCI-Express master access and verifies there are no pending
36 timeout--; in igc_disable_pcie_master()
41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING; in igc_disable_pcie_master()
50 * igc_init_rx_addrs - Initialize receive addresses
66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in igc_init_rx_addrs()
68 /* Zero out the other (rar_entry_count - 1) receive addresses */ in igc_init_rx_addrs()
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H A Digc_phy.c1 // SPDX-License-Identifier: GPL-2.0
8 * igc_check_reset_block - Check if PHY reset is blocked
11 * Read the PHY management control register and check whether a PHY reset
26 * igc_get_phy_id - Retrieve the PHY ID and revision
34 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
42 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
44 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
48 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in igc_get_phy_id()
49 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in igc_get_phy_id()
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/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
25 pci_read_config_word(adapter->pdev, in e1000e_get_bus_info_pcie()
28 bus->width = (enum e1000_bus_width)((pcie_link_status & in e1000e_get_bus_info_pcie()
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/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_mac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
18 * igb_get_bus_info_pcie - Get PCIe bus information
27 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
32 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
38 bus->width = e1000_bus_width_unknown; in igb_get_bus_info_pcie()
39 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
43 bus->speed = e1000_bus_speed_2500; in igb_get_bus_info_pcie()
46 bus->speed = e1000_bus_speed_5000; in igb_get_bus_info_pcie()
49 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
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/openbmc/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_mux.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
26 /* open session request (AP->CP) */
29 /* response to open session request (CP->AP) */
32 /* close session request (AP->CP) */
35 /* response to close session request (CP->AP) */
38 /* Flow control command with mask of the flow per queue/flow. */
41 /* ACK the flow control command. Shall have the same Transaction ID as the
103 u8 flow_ctrl; /* 0: Flow control disabled (flow allowed). */
104 /* 1: Flow control enabled (flow not allowed)*/
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H A Diosm_ipc_mux_codec.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
19 /* Enables the flow control (Flow is not allowed) */
22 /* Disables the flow control (Flow is allowed) */
25 /* ACK the flow control command. Shall have the same Transaction ID as the
64 /* FCTH: Signature of the Flow Credit Table */
82 /* MUX UL flow control lower threshold in bytes */
85 /* MUX UL flow control higher threshold in bytes (5ms worth of data)*/
89 * struct mux_cmdh - Structure of Command Header.
112 * struct mux_acbh - Structure of the Aggregated Command Block Header.
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/openbmc/linux/Documentation/core-api/
H A Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
51 This split implementation of high-level IRQ handlers allows us to
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/openbmc/linux/include/uapi/linux/
H A Ddcbnl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (c) 2008-2011, Intel Corporation.
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
50 * ----
53 * 1 credit-based shaper
55 * 3-254 reserved
94 * given in u-seconds
98 * before RP rate control state machine advances states
105 *@rpg_gd: Upon CNM receive, flow rate is limited to (Fb/Gd)*CurrentRate.
109 * value is given as percentage (1-100)
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/openbmc/linux/drivers/usb/serial/
H A Dbelkin_sa.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * This program is largely derived from work by the linux-usb group
12 * See Documentation/usb/usb-serial.rst for more information on using this
15 * 12-Mar-2001 gkh
16 * Added GoHubs GO-COM232 device id.
18 * 06-Nov-2000 gkh
21 * 12-Oct-2000 William Greathouse
59 #define BELKIN_SA_SET_FLOW_CTRL_REQUEST 16 /* Set flow control mode */
64 /* (always in Wininit sequence before flow control) */
73 #define BELKIN_SA_STOP_BITS(b) (b-1)
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H A Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
33 #define FCR 2 // ! Fifo Control Register (Write)
35 #define LCR 3 // Line Control Register
36 #define MCR 4 // Modem Control Register
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
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/openbmc/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Driver for Microsemi VSC85xx PHYs - MACsec support
11 #include <dt-bindings/net/mscc-phy-vsc8531.h>
37 /* non-MACsec access */ in vsc8584_macsec_phy_read()
321 struct vsc8531_private *priv = phydev->priv; in __vsc8584_macsec_init()
358 proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2; in __vsc8584_macsec_init()
371 struct macsec_flow *flow) in vsc8584_macsec_flow() argument
373 struct vsc8531_private *priv = phydev->priv; in vsc8584_macsec_flow()
374 enum macsec_bank bank = flow->bank; in vsc8584_macsec_flow()
375 u32 val, match = 0, mask = 0, action = 0, idx = flow->index; in vsc8584_macsec_flow()
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/openbmc/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dice.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
54 1) Make sure that your system's physical memory is in a high-performance
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H A Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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H A Dixgbe.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Known Issues
17 - Support
36 ----------------------------------
38 82599-BASED ADAPTERS
41 - If your 82599-based Intel(R) Network Adapter came with Intel optics or is an
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/openbmc/linux/drivers/net/ethernet/ti/
H A Dcpsw_sl.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
33 CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */
34 CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */
43 CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */
44 CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */
46 CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */
47 CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */
48 CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */
52 CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */
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/openbmc/linux/drivers/tty/serial/jsm/
H A Djsm_cls.c1 // SPDX-License-Identifier: GPL-2.0+
54 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
55 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
60 * the Line Control Register is set to 0xBFh. in cls_set_cts_flow_control()
62 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
64 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
66 /* Turn on CTS flow control, turn off IXON flow control */ in cls_set_cts_flow_control()
70 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
73 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
76 * Enable interrupts for CTS flow, turn off interrupts for in cls_set_cts_flow_control()
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dmilbeaut-uart.txt4 - compatible: should be "socionext,milbeaut-usio-uart".
5 - reg: offset and length of the register set for the device.
6 - interrupts: two interrupts specifier.
7 - interrupt-names: should be "rx", "tx".
8 - clocks: phandle to the input clock.
11 - auto-flow-control: flow control enable.
15 compatible = "socionext,milbeaut-usio-uart";
18 interrupt-names = "rx", "tx";
20 auto-flow-control;
/openbmc/linux/Documentation/devicetree/bindings/net/nfc/
H A Dmarvell,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - marvell,nfc-i2c
16 - marvell,nfc-spi
17 - marvell,nfc-uart
19 hci-muxed:
30 reset-n-io:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
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/openbmc/linux/drivers/net/usb/
H A Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
82 #define HW_CFG_ETC_ (0x00000010) /* EEPROM Timeout Control */
96 /* Power Management Control Register */
124 /* Automatic Flow Control Configuration Register */
126 #define AFC_CFG_HI_ (0x00FF0000) /* Auto Flow Ctrl High Level */
127 #define AFC_CFG_LO_ (0x0000FF00) /* Auto Flow Ctrl Low Level */
129 #define AFC_CFG_FC_MULT_ (0x00000008) /* Flow Ctrl on Mcast Frame */
130 #define AFC_CFG_FC_BRD_ (0x00000004) /* Flow Ctrl on Bcast Frame */
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/openbmc/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
89 * e1000_set_phy_type - Set the phy type member in the hw struct.
94 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
95 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
97 switch (hw->phy_id) { in e1000_set_phy_type()
103 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
106 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
107 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()
108 hw->mac_type == e1000_82547 || in e1000_set_phy_type()
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/openbmc/linux/include/net/phonet/
H A Dpep.h1 /* SPDX-License-Identifier: GPL-2.0-only */
19 /* XXX: union-ify listening vs connected stuff ? */
33 u8 rx_fc; /* RX flow control */
34 u8 tx_fc; /* TX flow control */
35 u8 init_enable; /* auto-enable at creation */
130 /* Phonet pipe sub-block types */
141 /* Phonet pipe flow control models */
152 /* Phonet pipe flow control states */
/openbmc/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_param.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define OPTION_UNSET -1
17 * TxDescriptors - Transmit Descriptor Count
18 * @Valid Range: PCH_GBE_MIN_TXD - PCH_GBE_MAX_TXD
26 * RxDescriptors -Receive Descriptor Count
27 * @Valid Range: PCH_GBE_MIN_RXD - PCH_GBE_MAX_RXD
35 * Speed - User Specified Speed Override
37 * - 0: auto-negotiate at all supported speeds
38 * - 10: only link at 10 Mbps
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/openbmc/linux/Documentation/networking/
H A Dopenvswitch.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The Open vSwitch kernel module allows flexible userspace control over
8 flow-level packet processing on selected network devices. It can be
10 VLAN processing, network access control, flow-based network control,
15 within a bridge). Each datapath also has associated with it a "flow
22 extracting its flow key and looking it up in the flow table. If there
23 is a matching flow, it executes the associated actions. If there is
25 its processing, userspace will likely set up a flow to handle further
26 packets of the same type entirely in-kernel).
29 Flow key compatibility
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/openbmc/linux/Documentation/networking/devlink/
H A Dmlx5.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 - Validation
18 * - ``enable_roce``
19 - driverinit
20 - Type: Boolean
23 device support for RoCE capability. Otherwise, the control occurs in the
26 * - ``io_eq_size``
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
20 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
47 /* PMT Control and Status */
61 * LPI status, timer and control register offset
66 /* LPI control and status defines */
79 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
81 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
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