1788a4ee6SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0+ */ 21da177e4SLinus Torvalds /************************************************************************ 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * 16654.H Definitions for 16C654 UART used on EdgePorts 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Copyright (C) 1998 Inside Out Networks, Inc. 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds ************************************************************************/ 91da177e4SLinus Torvalds 101da177e4SLinus Torvalds #if !defined(_16654_H) 111da177e4SLinus Torvalds #define _16654_H 121da177e4SLinus Torvalds 131da177e4SLinus Torvalds /************************************************************************ 141da177e4SLinus Torvalds * 151da177e4SLinus Torvalds * D e f i n e s / T y p e d e f s 161da177e4SLinus Torvalds * 171da177e4SLinus Torvalds ************************************************************************/ 181da177e4SLinus Torvalds 191da177e4SLinus Torvalds // 201da177e4SLinus Torvalds // UART register numbers 211da177e4SLinus Torvalds // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and 221da177e4SLinus Torvalds // above are used internally to indicate that we must enable access 231da177e4SLinus Torvalds // to them via LCR bit 0x80 or LCR = 0xBF. 241da177e4SLinus Torvalds // The register number sent to the Edgeport is then (x & 0x7). 251da177e4SLinus Torvalds // 261da177e4SLinus Torvalds // Driver must not access registers that affect operation of the 271da177e4SLinus Torvalds // the EdgePort firmware -- that includes THR, RHR, IER, FCR. 281da177e4SLinus Torvalds 291da177e4SLinus Torvalds 301da177e4SLinus Torvalds #define THR 0 // ! Transmit Holding Register (Write) 311da177e4SLinus Torvalds #define RDR 0 // ! Receive Holding Register (Read) 321da177e4SLinus Torvalds #define IER 1 // ! Interrupt Enable Register 331da177e4SLinus Torvalds #define FCR 2 // ! Fifo Control Register (Write) 341da177e4SLinus Torvalds #define ISR 2 // Interrupt Status Register (Read) 351da177e4SLinus Torvalds #define LCR 3 // Line Control Register 361da177e4SLinus Torvalds #define MCR 4 // Modem Control Register 371da177e4SLinus Torvalds #define LSR 5 // Line Status Register 381da177e4SLinus Torvalds #define MSR 6 // Modem Status Register 391da177e4SLinus Torvalds #define SPR 7 // ScratchPad Register 401da177e4SLinus Torvalds #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB 411da177e4SLinus Torvalds #define DLM 9 // Bank2[ 1 ] Divisor Latch MSB 421da177e4SLinus Torvalds #define EFR 10 // Bank2[ 2 ] Extended Function Register 431da177e4SLinus Torvalds //efine unused 11 // Bank2[ 3 ] 441da177e4SLinus Torvalds #define XON1 12 // Bank2[ 4 ] Xon-1 451da177e4SLinus Torvalds #define XON2 13 // Bank2[ 5 ] Xon-2 461da177e4SLinus Torvalds #define XOFF1 14 // Bank2[ 6 ] Xoff-1 471da177e4SLinus Torvalds #define XOFF2 15 // Bank2[ 7 ] Xoff-2 481da177e4SLinus Torvalds 491da177e4SLinus Torvalds #define NUM_16654_REGS 16 501da177e4SLinus Torvalds 511da177e4SLinus Torvalds #define IS_REG_2ND_BANK(x) ((x) >= 8) 521da177e4SLinus Torvalds 531da177e4SLinus Torvalds // 541da177e4SLinus Torvalds // Bit definitions for each register 551da177e4SLinus Torvalds // 561da177e4SLinus Torvalds 571da177e4SLinus Torvalds #define IER_RX 0x01 // Enable receive interrupt 581da177e4SLinus Torvalds #define IER_TX 0x02 // Enable transmit interrupt 591da177e4SLinus Torvalds #define IER_RXS 0x04 // Enable receive status interrupt 601da177e4SLinus Torvalds #define IER_MDM 0x08 // Enable modem status interrupt 611da177e4SLinus Torvalds #define IER_SLEEP 0x10 // Enable sleep mode 621da177e4SLinus Torvalds #define IER_XOFF 0x20 // Enable s/w flow control (XOFF) interrupt 631da177e4SLinus Torvalds #define IER_RTS 0x40 // Enable RTS interrupt 641da177e4SLinus Torvalds #define IER_CTS 0x80 // Enable CTS interrupt 651da177e4SLinus Torvalds #define IER_ENABLE_ALL 0xFF // Enable all ints 661da177e4SLinus Torvalds 671da177e4SLinus Torvalds 681da177e4SLinus Torvalds #define FCR_FIFO_EN 0x01 // Enable FIFOs 691da177e4SLinus Torvalds #define FCR_RXCLR 0x02 // Reset Rx FIFO 701da177e4SLinus Torvalds #define FCR_TXCLR 0x04 // Reset Tx FIFO 711da177e4SLinus Torvalds #define FCR_DMA_BLK 0x08 // Enable DMA block mode 721da177e4SLinus Torvalds #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level 731da177e4SLinus Torvalds #define FCR_TX_LEVEL_8 0x00 // Tx FIFO Level = 8 bytes 741da177e4SLinus Torvalds #define FCR_TX_LEVEL_16 0x10 // Tx FIFO Level = 16 bytes 751da177e4SLinus Torvalds #define FCR_TX_LEVEL_32 0x20 // Tx FIFO Level = 32 bytes 761da177e4SLinus Torvalds #define FCR_TX_LEVEL_56 0x30 // Tx FIFO Level = 56 bytes 771da177e4SLinus Torvalds #define FCR_RX_LEVEL_MASK 0xC0 // Mask for Rx FIFO Level 781da177e4SLinus Torvalds #define FCR_RX_LEVEL_8 0x00 // Rx FIFO Level = 8 bytes 791da177e4SLinus Torvalds #define FCR_RX_LEVEL_16 0x40 // Rx FIFO Level = 16 bytes 801da177e4SLinus Torvalds #define FCR_RX_LEVEL_56 0x80 // Rx FIFO Level = 56 bytes 811da177e4SLinus Torvalds #define FCR_RX_LEVEL_60 0xC0 // Rx FIFO Level = 60 bytes 821da177e4SLinus Torvalds 831da177e4SLinus Torvalds 841da177e4SLinus Torvalds #define ISR_INT_MDM_STATUS 0x00 // Modem status int pending 851da177e4SLinus Torvalds #define ISR_INT_NONE 0x01 // No interrupt pending 861da177e4SLinus Torvalds #define ISR_INT_TXRDY 0x02 // Tx ready int pending 871da177e4SLinus Torvalds #define ISR_INT_RXRDY 0x04 // Rx ready int pending 881da177e4SLinus Torvalds #define ISR_INT_LINE_STATUS 0x06 // Line status int pending 891da177e4SLinus Torvalds #define ISR_INT_RX_TIMEOUT 0x0C // Rx timeout int pending 901da177e4SLinus Torvalds #define ISR_INT_RX_XOFF 0x10 // Rx Xoff int pending 911da177e4SLinus Torvalds #define ISR_INT_RTS_CTS 0x20 // RTS/CTS change int pending 921da177e4SLinus Torvalds #define ISR_FIFO_ENABLED 0xC0 // Bits set if FIFOs enabled 931da177e4SLinus Torvalds #define ISR_INT_BITS_MASK 0x3E // Mask to isolate valid int causes 941da177e4SLinus Torvalds 951da177e4SLinus Torvalds 961da177e4SLinus Torvalds #define LCR_BITS_5 0x00 // 5 bits/char 971da177e4SLinus Torvalds #define LCR_BITS_6 0x01 // 6 bits/char 981da177e4SLinus Torvalds #define LCR_BITS_7 0x02 // 7 bits/char 991da177e4SLinus Torvalds #define LCR_BITS_8 0x03 // 8 bits/char 1001da177e4SLinus Torvalds #define LCR_BITS_MASK 0x03 // Mask for bits/char field 1011da177e4SLinus Torvalds 1021da177e4SLinus Torvalds #define LCR_STOP_1 0x00 // 1 stop bit 1031da177e4SLinus Torvalds #define LCR_STOP_1_5 0x04 // 1.5 stop bits (if 5 bits/char) 1041da177e4SLinus Torvalds #define LCR_STOP_2 0x04 // 2 stop bits (if 6-8 bits/char) 1051da177e4SLinus Torvalds #define LCR_STOP_MASK 0x04 // Mask for stop bits field 1061da177e4SLinus Torvalds 1071da177e4SLinus Torvalds #define LCR_PAR_NONE 0x00 // No parity 1081da177e4SLinus Torvalds #define LCR_PAR_ODD 0x08 // Odd parity 1091da177e4SLinus Torvalds #define LCR_PAR_EVEN 0x18 // Even parity 1101da177e4SLinus Torvalds #define LCR_PAR_MARK 0x28 // Force parity bit to 1 1111da177e4SLinus Torvalds #define LCR_PAR_SPACE 0x38 // Force parity bit to 0 1121da177e4SLinus Torvalds #define LCR_PAR_MASK 0x38 // Mask for parity field 1131da177e4SLinus Torvalds 1141da177e4SLinus Torvalds #define LCR_SET_BREAK 0x40 // Set Break condition 1151da177e4SLinus Torvalds #define LCR_DL_ENABLE 0x80 // Enable access to divisor latch 1161da177e4SLinus Torvalds 1171da177e4SLinus Torvalds #define LCR_ACCESS_EFR 0xBF // Load this value to access DLL,DLM, 1181da177e4SLinus Torvalds // and also the '654-only registers 1191da177e4SLinus Torvalds // EFR, XON1, XON2, XOFF1, XOFF2 1201da177e4SLinus Torvalds 1211da177e4SLinus Torvalds 1221da177e4SLinus Torvalds #define MCR_DTR 0x01 // Assert DTR 1231da177e4SLinus Torvalds #define MCR_RTS 0x02 // Assert RTS 1241da177e4SLinus Torvalds #define MCR_OUT1 0x04 // Loopback only: Sets state of RI 1251da177e4SLinus Torvalds #define MCR_MASTER_IE 0x08 // Enable interrupt outputs 1261da177e4SLinus Torvalds #define MCR_LOOPBACK 0x10 // Set internal (digital) loopback mode 1271da177e4SLinus Torvalds #define MCR_XON_ANY 0x20 // Enable any char to exit XOFF mode 1281da177e4SLinus Torvalds #define MCR_IR_ENABLE 0x40 // Enable IrDA functions 1291da177e4SLinus Torvalds #define MCR_BRG_DIV_4 0x80 // Divide baud rate clk by /4 instead of /1 1301da177e4SLinus Torvalds 1311da177e4SLinus Torvalds 1321da177e4SLinus Torvalds #define LSR_RX_AVAIL 0x01 // Rx data available 1331da177e4SLinus Torvalds #define LSR_OVER_ERR 0x02 // Rx overrun 1341da177e4SLinus Torvalds #define LSR_PAR_ERR 0x04 // Rx parity error 1351da177e4SLinus Torvalds #define LSR_FRM_ERR 0x08 // Rx framing error 1361da177e4SLinus Torvalds #define LSR_BREAK 0x10 // Rx break condition detected 1371da177e4SLinus Torvalds #define LSR_TX_EMPTY 0x20 // Tx Fifo empty 1381da177e4SLinus Torvalds #define LSR_TX_ALL_EMPTY 0x40 // Tx Fifo and shift register empty 1391da177e4SLinus Torvalds #define LSR_FIFO_ERR 0x80 // Rx Fifo contains at least 1 erred char 1401da177e4SLinus Torvalds 1411da177e4SLinus Torvalds 1421da177e4SLinus Torvalds #define EDGEPORT_MSR_DELTA_CTS 0x01 // CTS changed from last read 1431da177e4SLinus Torvalds #define EDGEPORT_MSR_DELTA_DSR 0x02 // DSR changed from last read 1441da177e4SLinus Torvalds #define EDGEPORT_MSR_DELTA_RI 0x04 // RI changed from 0 -> 1 1451da177e4SLinus Torvalds #define EDGEPORT_MSR_DELTA_CD 0x08 // CD changed from last read 1461da177e4SLinus Torvalds #define EDGEPORT_MSR_CTS 0x10 // Current state of CTS 1471da177e4SLinus Torvalds #define EDGEPORT_MSR_DSR 0x20 // Current state of DSR 1481da177e4SLinus Torvalds #define EDGEPORT_MSR_RI 0x40 // Current state of RI 1491da177e4SLinus Torvalds #define EDGEPORT_MSR_CD 0x80 // Current state of CD 1501da177e4SLinus Torvalds 1511da177e4SLinus Torvalds 1521da177e4SLinus Torvalds 1531da177e4SLinus Torvalds // Tx Rx 1541da177e4SLinus Torvalds //------------------------------- 1551da177e4SLinus Torvalds #define EFR_SWFC_NONE 0x00 // None None 1561da177e4SLinus Torvalds #define EFR_SWFC_RX1 0x02 // None XOFF1 1571da177e4SLinus Torvalds #define EFR_SWFC_RX2 0x01 // None XOFF2 1581da177e4SLinus Torvalds #define EFR_SWFC_RX12 0x03 // None XOFF1 & XOFF2 1591da177e4SLinus Torvalds #define EFR_SWFC_TX1 0x08 // XOFF1 None 1601da177e4SLinus Torvalds #define EFR_SWFC_TX1_RX1 0x0a // XOFF1 XOFF1 1611da177e4SLinus Torvalds #define EFR_SWFC_TX1_RX2 0x09 // XOFF1 XOFF2 1621da177e4SLinus Torvalds #define EFR_SWFC_TX1_RX12 0x0b // XOFF1 XOFF1 & XOFF2 1631da177e4SLinus Torvalds #define EFR_SWFC_TX2 0x04 // XOFF2 None 1641da177e4SLinus Torvalds #define EFR_SWFC_TX2_RX1 0x06 // XOFF2 XOFF1 1651da177e4SLinus Torvalds #define EFR_SWFC_TX2_RX2 0x05 // XOFF2 XOFF2 1661da177e4SLinus Torvalds #define EFR_SWFC_TX2_RX12 0x07 // XOFF2 XOFF1 & XOFF2 1671da177e4SLinus Torvalds #define EFR_SWFC_TX12 0x0c // XOFF1 & XOFF2 None 1681da177e4SLinus Torvalds #define EFR_SWFC_TX12_RX1 0x0e // XOFF1 & XOFF2 XOFF1 1691da177e4SLinus Torvalds #define EFR_SWFC_TX12_RX2 0x0d // XOFF1 & XOFF2 XOFF2 1701da177e4SLinus Torvalds #define EFR_SWFC_TX12_RX12 0x0f // XOFF1 & XOFF2 XOFF1 & XOFF2 1711da177e4SLinus Torvalds 1721da177e4SLinus Torvalds #define EFR_TX_FC_MASK 0x0c // Mask to isolate Rx flow control 1731da177e4SLinus Torvalds #define EFR_TX_FC_NONE 0x00 // No Tx Xon/Xoff flow control 1741da177e4SLinus Torvalds #define EFR_TX_FC_X1 0x08 // Transmit Xon1/Xoff1 1751da177e4SLinus Torvalds #define EFR_TX_FC_X2 0x04 // Transmit Xon2/Xoff2 1761da177e4SLinus Torvalds #define EFR_TX_FC_X1_2 0x0c // Transmit Xon1&2/Xoff1&2 1771da177e4SLinus Torvalds 1781da177e4SLinus Torvalds #define EFR_RX_FC_MASK 0x03 // Mask to isolate Rx flow control 1791da177e4SLinus Torvalds #define EFR_RX_FC_NONE 0x00 // No Rx Xon/Xoff flow control 1801da177e4SLinus Torvalds #define EFR_RX_FC_X1 0x02 // Receiver compares Xon1/Xoff1 1811da177e4SLinus Torvalds #define EFR_RX_FC_X2 0x01 // Receiver compares Xon2/Xoff2 1821da177e4SLinus Torvalds #define EFR_RX_FC_X1_2 0x03 // Receiver compares Xon1&2/Xoff1&2 1831da177e4SLinus Torvalds 1841da177e4SLinus Torvalds 1851da177e4SLinus Torvalds #define EFR_SWFC_MASK 0x0F // Mask for software flow control field 1861da177e4SLinus Torvalds #define EFR_ENABLE_16654 0x10 // Enable 16C654 features 1871da177e4SLinus Torvalds #define EFR_SPEC_DETECT 0x20 // Enable special character detect interrupt 1881da177e4SLinus Torvalds #define EFR_AUTO_RTS 0x40 // Use RTS for Rx flow control 1891da177e4SLinus Torvalds #define EFR_AUTO_CTS 0x80 // Use CTS for Tx flow control 1901da177e4SLinus Torvalds 1911da177e4SLinus Torvalds #endif // if !defined(_16654_H) 1921da177e4SLinus Torvalds 193