Lines Matching +full:flow +full:- +full:control
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
18 * igb_get_bus_info_pcie - Get PCIe bus information
27 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
32 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
38 bus->width = e1000_bus_width_unknown; in igb_get_bus_info_pcie()
39 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
43 bus->speed = e1000_bus_speed_2500; in igb_get_bus_info_pcie()
46 bus->speed = e1000_bus_speed_5000; in igb_get_bus_info_pcie()
49 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
53 bus->width = (enum e1000_bus_width)((pcie_link_status & in igb_get_bus_info_pcie()
59 bus->func = FIELD_GET(E1000_STATUS_FUNC_MASK, reg); in igb_get_bus_info_pcie()
65 * igb_clear_vfta - Clear VLAN filter table
75 for (offset = E1000_VLAN_FILTER_TBL_SIZE; offset--;) in igb_clear_vfta()
76 hw->mac.ops.write_vfta(hw, offset, 0); in igb_clear_vfta()
80 * igb_write_vfta - Write value to VLAN filter table
90 struct igb_adapter *adapter = hw->back; in igb_write_vfta()
95 adapter->shadow_vfta[offset] = value; in igb_write_vfta()
99 * igb_init_rx_addrs - Initialize receive address's
115 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in igb_init_rx_addrs()
117 /* Zero out the other (rar_entry_count - 1) receive addresses */ in igb_init_rx_addrs()
118 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1); in igb_init_rx_addrs()
120 hw->mac.ops.rar_set(hw, mac_addr, i); in igb_init_rx_addrs()
124 * igb_find_vlvf_slot - find the VLAN id or the first empty slot
145 first_empty_slot = vlvf_bypass ? -E1000_ERR_NO_SPACE : 0; in igb_find_vlvf_slot()
150 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 in igb_find_vlvf_slot()
152 for (regindex = E1000_VLVF_ARRAY_SIZE; --regindex > 0;) { in igb_find_vlvf_slot()
160 return first_empty_slot ? : -E1000_ERR_NO_SPACE; in igb_find_vlvf_slot()
164 * igb_vfta_set - enable or disable vlan in VLAN filter table
177 struct igb_adapter *adapter = hw->back; in igb_vfta_set()
182 return -E1000_ERR_PARAM; in igb_vfta_set()
184 /* this is a 2 part operation - first the VFTA, then the in igb_vfta_set()
190 * The VFTA is a bitstring made up of 128 32-bit registers in igb_vfta_set()
192 * bits[11-5]: which register in igb_vfta_set()
193 * bits[4-0]: which bit in the register in igb_vfta_set()
197 vfta = adapter->shadow_vfta[regidx]; in igb_vfta_set()
214 if (!adapter->vfs_allocated_count) in igb_vfta_set()
240 hw->mac.ops.write_vfta(hw, regidx, vfta); in igb_vfta_set()
271 hw->mac.ops.write_vfta(hw, regidx, vfta); in igb_vfta_set()
277 * igb_check_alt_mac_addr - Check for alternate MAC addr
281 * can be setup by pre-boot software and must be treated like a permanent
297 if (hw->mac.type >= e1000_82580) in igb_check_alt_mac_addr()
300 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, in igb_check_alt_mac_addr()
312 if (hw->bus.func == E1000_FUNC_1) in igb_check_alt_mac_addr()
314 if (hw->bus.func == E1000_FUNC_2) in igb_check_alt_mac_addr()
317 if (hw->bus.func == E1000_FUNC_3) in igb_check_alt_mac_addr()
321 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in igb_check_alt_mac_addr()
341 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); in igb_check_alt_mac_addr()
348 * igb_rar_set - Set receive address register
373 /* Some bridges will combine consecutive 32-bit writes into in igb_rar_set()
384 * igb_mta_set - Set multicast filter table address
388 * The multicast table address is a register array of 32-bit registers.
397 /* The MTA is a register array of 32-bit registers. It is in igb_mta_set()
401 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a in igb_mta_set()
406 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); in igb_mta_set()
418 * igb_hash_mc_addr - Generate a multicast hash value
432 hash_mask = (hw->mac.mta_reg_count * 32) - 1; in igb_hash_mc_addr()
434 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts in igb_hash_mc_addr()
444 * left-shifts where the MSB of mc_addr[5] would still fall within in igb_hash_mc_addr()
447 * remaining number of bits. Thus 8 - bit_shift. The rest of the in igb_hash_mc_addr()
450 * 8-bit shifting total. in igb_hash_mc_addr()
453 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), in igb_hash_mc_addr()
465 switch (hw->mac.mc_filter_type) { in igb_hash_mc_addr()
480 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | in igb_hash_mc_addr()
487 * igb_i21x_hw_doublecheck - double checks potential HW issue in i21X
501 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) { in igb_i21x_hw_doublecheck()
502 if (array_rd32(E1000_MTA, i) != hw->mac.mta_shadow[i]) { in igb_i21x_hw_doublecheck()
504 array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]); in igb_i21x_hw_doublecheck()
508 if (is_failed && --failed_cnt <= 0) { in igb_i21x_hw_doublecheck()
516 * igb_update_mc_addr_list - Update Multicast addresses
531 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in igb_update_mc_addr_list()
537 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); in igb_update_mc_addr_list()
540 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit); in igb_update_mc_addr_list()
545 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) in igb_update_mc_addr_list()
546 array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]); in igb_update_mc_addr_list()
548 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) in igb_update_mc_addr_list()
553 * igb_clear_hw_cntrs_base - Clear base hardware counters
600 * igb_check_for_copper_link - Check for link (Copper)
609 struct e1000_mac_info *mac = &hw->mac; in igb_check_for_copper_link()
613 /* We only want to go out to the PHY registers to see if Auto-Neg in igb_check_for_copper_link()
618 if (!mac->get_link_status) { in igb_check_for_copper_link()
634 mac->get_link_status = false; in igb_check_for_copper_link()
637 * immediately after link-up in igb_check_for_copper_link()
644 if (!mac->autoneg) { in igb_check_for_copper_link()
645 ret_val = -E1000_ERR_CONFIG; in igb_check_for_copper_link()
649 /* Auto-Neg is enabled. Auto Speed Detection takes care in igb_check_for_copper_link()
655 /* Configure Flow Control now that Auto-Neg has completed. in igb_check_for_copper_link()
656 * First, we need to restore the desired flow control in igb_check_for_copper_link()
657 * settings because we may have had to re-autoneg with a in igb_check_for_copper_link()
662 hw_dbg("Error configuring flow control\n"); in igb_check_for_copper_link()
669 * igb_setup_link - Setup flow control and link settings
672 * Determines which flow control settings to use, then configures flow
673 * control. Calls the appropriate media-specific link configuration
688 /* If requested flow control is set to default, set flow control in igb_setup_link()
689 * based on the EEPROM flow control settings. in igb_setup_link()
691 if (hw->fc.requested_mode == e1000_fc_default) { in igb_setup_link()
697 /* We want to save off the original Flow Control configuration just in igb_setup_link()
699 * hub or switch with different Flow Control capabilities. in igb_setup_link()
701 hw->fc.current_mode = hw->fc.requested_mode; in igb_setup_link()
703 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); in igb_setup_link()
706 ret_val = hw->mac.ops.setup_physical_interface(hw); in igb_setup_link()
710 /* Initialize the flow control address, type, and PAUSE timer in igb_setup_link()
711 * registers to their default values. This is done even if flow in igb_setup_link()
712 * control is disabled, because it does not hurt anything to in igb_setup_link()
715 hw_dbg("Initializing the Flow Control address, type and timer regs\n"); in igb_setup_link()
720 wr32(E1000_FCTTV, hw->fc.pause_time); in igb_setup_link()
730 * igb_config_collision_dist - Configure collision distance
751 * igb_set_fc_watermarks - Set flow control high/low watermarks
754 * Sets the flow control high/low threshold (watermark) registers. If
755 * flow control XON frame transmission is enabled, then set XON frame
762 /* Set the flow control receive threshold registers. Normally, in igb_set_fc_watermarks()
768 if (hw->fc.current_mode & e1000_fc_tx_pause) { in igb_set_fc_watermarks()
773 fcrtl = hw->fc.low_water; in igb_set_fc_watermarks()
774 if (hw->fc.send_xon) in igb_set_fc_watermarks()
777 fcrth = hw->fc.high_water; in igb_set_fc_watermarks()
784 * igb_set_default_fc - Set flow control default values
787 * Read the EEPROM for the default values for flow control and store the
797 * that determine the hardware's default PAUSE (flow control) mode, in igb_set_default_fc()
799 * disabling auto-negotiation, and the direction of the in igb_set_default_fc()
800 * SW defined pins. If there is no SW over-ride of the flow in igb_set_default_fc()
801 * control setting, then the variable hw->fc will in igb_set_default_fc()
804 if (hw->mac.type == e1000_i350) in igb_set_default_fc()
805 lan_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); in igb_set_default_fc()
809 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG + lan_offset, in igb_set_default_fc()
817 hw->fc.requested_mode = e1000_fc_none; in igb_set_default_fc()
819 hw->fc.requested_mode = e1000_fc_tx_pause; in igb_set_default_fc()
821 hw->fc.requested_mode = e1000_fc_full; in igb_set_default_fc()
828 * igb_force_mac_fc - Force the MAC's flow control settings
831 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
832 * device control register to reflect the adapter settings. TFCE and RFCE
844 /* Because we didn't get link via the internal auto-negotiation in igb_force_mac_fc()
846 * auto-neg), we have to manually enable/disable transmit an in igb_force_mac_fc()
847 * receive flow control. in igb_force_mac_fc()
849 * The "Case" statement below enables/disable flow control in igb_force_mac_fc()
850 * according to the "hw->fc.current_mode" parameter. in igb_force_mac_fc()
853 * 0: Flow control is completely disabled in igb_force_mac_fc()
854 * 1: Rx flow control is enabled (we can receive pause in igb_force_mac_fc()
856 * 2: Tx flow control is enabled (we can send pause frames in igb_force_mac_fc()
858 * 3: Both Rx and TX flow control (symmetric) is enabled. in igb_force_mac_fc()
861 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); in igb_force_mac_fc()
863 switch (hw->fc.current_mode) { in igb_force_mac_fc()
879 hw_dbg("Flow control param set incorrectly\n"); in igb_force_mac_fc()
880 ret_val = -E1000_ERR_CONFIG; in igb_force_mac_fc()
891 * igb_config_fc_after_link_up - Configures flow control after link
894 * Checks the status of auto-negotiation after link up to ensure that the
896 * flow control needs to be forced also. If auto-negotiation is enabled
897 * and did not fail, then we configure flow control based on our link
902 struct e1000_mac_info *mac = &hw->mac; in igb_config_fc_after_link_up()
908 /* Check for the case where we have fiber media and auto-neg failed in igb_config_fc_after_link_up()
912 if (mac->autoneg_failed) { in igb_config_fc_after_link_up()
913 if (hw->phy.media_type == e1000_media_type_internal_serdes) in igb_config_fc_after_link_up()
916 if (hw->phy.media_type == e1000_media_type_copper) in igb_config_fc_after_link_up()
921 hw_dbg("Error forcing flow control settings\n"); in igb_config_fc_after_link_up()
925 /* Check for the case where we have copper media and auto-neg is in igb_config_fc_after_link_up()
926 * enabled. In this case, we need to check and see if Auto-Neg in igb_config_fc_after_link_up()
928 * flow control configured. in igb_config_fc_after_link_up()
930 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { in igb_config_fc_after_link_up()
935 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igb_config_fc_after_link_up()
939 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igb_config_fc_after_link_up()
953 * flow control was negotiated. in igb_config_fc_after_link_up()
955 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, in igb_config_fc_after_link_up()
959 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, in igb_config_fc_after_link_up()
966 * Page Ability Register (Address 5) determine flow control in igb_config_fc_after_link_up()
969 * 1999, describes these PAUSE resolution bits and how flow in igb_config_fc_after_link_up()
970 * control is determined based upon these settings. in igb_config_fc_after_link_up()
975 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
986 * Symmetric Flow Control is enabled at both ends. The in igb_config_fc_after_link_up()
989 * For Symmetric Flow Control: in igb_config_fc_after_link_up()
993 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1001 * FULL flow control because we could not advertise RX in igb_config_fc_after_link_up()
1005 if (hw->fc.requested_mode == e1000_fc_full) { in igb_config_fc_after_link_up()
1006 hw->fc.current_mode = e1000_fc_full; in igb_config_fc_after_link_up()
1007 hw_dbg("Flow Control = FULL.\n"); in igb_config_fc_after_link_up()
1009 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
1010 hw_dbg("Flow Control = RX PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1017 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1024 hw->fc.current_mode = e1000_fc_tx_pause; in igb_config_fc_after_link_up()
1025 hw_dbg("Flow Control = TX PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1031 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1038 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
1039 hw_dbg("Flow Control = RX PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1041 /* Per the IEEE spec, at this point flow control should be in igb_config_fc_after_link_up()
1044 * desired flow control, but can be forced on the link in igb_config_fc_after_link_up()
1045 * partner. So if we advertised no flow control, that is in igb_config_fc_after_link_up()
1047 * receive capability (Rx Pause Only or Full Flow Control) in igb_config_fc_after_link_up()
1049 * ourselves to enable Rx Flow Control only. We can do in igb_config_fc_after_link_up()
1051 * didn't want flow control enabled, and we enable Rx, no in igb_config_fc_after_link_up()
1054 * flow control enabled, then by us enabling RX only, we in igb_config_fc_after_link_up()
1061 else if ((hw->fc.requested_mode == e1000_fc_none) || in igb_config_fc_after_link_up()
1062 (hw->fc.requested_mode == e1000_fc_tx_pause) || in igb_config_fc_after_link_up()
1063 (hw->fc.strict_ieee)) { in igb_config_fc_after_link_up()
1064 hw->fc.current_mode = e1000_fc_none; in igb_config_fc_after_link_up()
1065 hw_dbg("Flow Control = NONE.\n"); in igb_config_fc_after_link_up()
1067 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
1068 hw_dbg("Flow Control = RX PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1071 /* Now we need to do one last check... If we auto- in igb_config_fc_after_link_up()
1072 * negotiated to HALF DUPLEX, flow control should not be in igb_config_fc_after_link_up()
1075 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); in igb_config_fc_after_link_up()
1082 hw->fc.current_mode = e1000_fc_none; in igb_config_fc_after_link_up()
1085 * controller to use the correct flow control settings. in igb_config_fc_after_link_up()
1089 hw_dbg("Error forcing flow control settings\n"); in igb_config_fc_after_link_up()
1093 /* Check for the case where we have SerDes media and auto-neg is in igb_config_fc_after_link_up()
1094 * enabled. In this case, we need to check and see if Auto-Neg in igb_config_fc_after_link_up()
1096 * flow control configured. in igb_config_fc_after_link_up()
1098 if ((hw->phy.media_type == e1000_media_type_internal_serdes) in igb_config_fc_after_link_up()
1099 && mac->autoneg) { in igb_config_fc_after_link_up()
1114 * flow control was negotiated. in igb_config_fc_after_link_up()
1121 * Page Ability Register (PCS_LPAB) determine flow control in igb_config_fc_after_link_up()
1124 * 1999, describes these PAUSE resolution bits and how flow in igb_config_fc_after_link_up()
1125 * control is determined based upon these settings. in igb_config_fc_after_link_up()
1130 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1141 * Symmetric Flow Control is enabled at both ends. The in igb_config_fc_after_link_up()
1144 * For Symmetric Flow Control: in igb_config_fc_after_link_up()
1148 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1156 * FULL flow control because we could not advertise Rx in igb_config_fc_after_link_up()
1160 if (hw->fc.requested_mode == e1000_fc_full) { in igb_config_fc_after_link_up()
1161 hw->fc.current_mode = e1000_fc_full; in igb_config_fc_after_link_up()
1162 hw_dbg("Flow Control = FULL.\n"); in igb_config_fc_after_link_up()
1164 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
1165 hw_dbg("Flow Control = Rx PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1172 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1179 hw->fc.current_mode = e1000_fc_tx_pause; in igb_config_fc_after_link_up()
1180 hw_dbg("Flow Control = Tx PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1186 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1193 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
1194 hw_dbg("Flow Control = Rx PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1196 /* Per the IEEE spec, at this point flow control in igb_config_fc_after_link_up()
1199 hw->fc.current_mode = e1000_fc_none; in igb_config_fc_after_link_up()
1200 hw_dbg("Flow Control = NONE.\n"); in igb_config_fc_after_link_up()
1204 * controller to use the correct flow control settings. in igb_config_fc_after_link_up()
1212 hw_dbg("Error forcing flow control settings\n"); in igb_config_fc_after_link_up()
1222 * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
1259 * igb_get_hw_semaphore - Acquire hardware semaphore
1268 s32 timeout = hw->nvm.word_size + 1; in igb_get_hw_semaphore()
1282 hw_dbg("Driver can't access device - SMBI bit is set.\n"); in igb_get_hw_semaphore()
1283 ret_val = -E1000_ERR_NVM; in igb_get_hw_semaphore()
1303 ret_val = -E1000_ERR_NVM; in igb_get_hw_semaphore()
1312 * igb_put_hw_semaphore - Release hardware semaphore
1329 * igb_get_auto_rd_done - Check for auto read completion
1349 ret_val = -E1000_ERR_RESET; in igb_get_auto_rd_done()
1358 * igb_valid_led_default - Verify a valid default LED config
1369 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in igb_valid_led_default()
1376 switch (hw->phy.media_type) { in igb_valid_led_default()
1391 * igb_id_led_init -
1397 struct e1000_mac_info *mac = &hw->mac; in igb_id_led_init()
1406 if ((hw->mac.type == e1000_i210) || in igb_id_led_init()
1407 (hw->mac.type == e1000_i211)) in igb_id_led_init()
1415 mac->ledctl_default = rd32(E1000_LEDCTL); in igb_id_led_init()
1416 mac->ledctl_mode1 = mac->ledctl_default; in igb_id_led_init()
1417 mac->ledctl_mode2 = mac->ledctl_default; in igb_id_led_init()
1425 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); in igb_id_led_init()
1426 mac->ledctl_mode1 |= ledctl_on << (i << 3); in igb_id_led_init()
1431 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); in igb_id_led_init()
1432 mac->ledctl_mode1 |= ledctl_off << (i << 3); in igb_id_led_init()
1442 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); in igb_id_led_init()
1443 mac->ledctl_mode2 |= ledctl_on << (i << 3); in igb_id_led_init()
1448 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); in igb_id_led_init()
1449 mac->ledctl_mode2 |= ledctl_off << (i << 3); in igb_id_led_init()
1462 * igb_cleanup_led - Set LED config to default operation
1470 wr32(E1000_LEDCTL, hw->mac.ledctl_default); in igb_cleanup_led()
1475 * igb_blink_led - Blink LED
1485 if (hw->phy.media_type == e1000_media_type_fiber) { in igb_blink_led()
1486 /* always blink LED0 for PCI-E fiber */ in igb_blink_led()
1496 ledctl_blink = hw->mac.ledctl_mode2; in igb_blink_led()
1498 u32 mode = (hw->mac.ledctl_mode2 >> i) & in igb_blink_led()
1500 u32 led_default = hw->mac.ledctl_default >> i; in igb_blink_led()
1520 * igb_led_off - Turn LED off
1527 switch (hw->phy.media_type) { in igb_led_off()
1529 wr32(E1000_LEDCTL, hw->mac.ledctl_mode1); in igb_led_off()
1539 * igb_disable_pcie_master - Disables PCI-express master access
1542 * Returns 0 (0) if successful, else returns -10
1543 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1546 * Disables PCI-Express master access and verifies there are no pending
1555 if (hw->bus.type != e1000_bus_type_pci_express) in igb_disable_pcie_master()
1567 timeout--; in igb_disable_pcie_master()
1572 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; in igb_disable_pcie_master()
1581 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1584 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1592 if (hw->mac.type >= e1000_82580) in igb_validate_mdi_setting()
1595 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { in igb_validate_mdi_setting()
1597 hw->phy.mdix = 1; in igb_validate_mdi_setting()
1598 ret_val = -E1000_ERR_CONFIG; in igb_validate_mdi_setting()
1607 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1613 * Writes an address/data control type register. There are several of these
1636 ret_val = -E1000_ERR_PHY; in igb_write_8bit_ctrl_reg()
1645 * igb_enable_mng_pass_thru - Enable processing of ARP's
1657 if (!hw->mac.asf_firmware_present) in igb_enable_mng_pass_thru()
1665 if (hw->mac.arc_subsystem_valid) { in igb_enable_mng_pass_thru()