Lines Matching +full:flow +full:- +full:control
1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
33 #define FCR 2 // ! Fifo Control Register (Write)
35 #define LCR 3 // Line Control Register
36 #define MCR 4 // Modem Control Register
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
62 #define IER_XOFF 0x20 // Enable s/w flow control (XOFF) interrupt
104 #define LCR_STOP_2 0x04 // 2 stop bits (if 6-8 bits/char)
118 // and also the '654-only registers
144 #define EDGEPORT_MSR_DELTA_RI 0x04 // RI changed from 0 -> 1
154 //-------------------------------
172 #define EFR_TX_FC_MASK 0x0c // Mask to isolate Rx flow control
173 #define EFR_TX_FC_NONE 0x00 // No Tx Xon/Xoff flow control
178 #define EFR_RX_FC_MASK 0x03 // Mask to isolate Rx flow control
179 #define EFR_RX_FC_NONE 0x00 // No Rx Xon/Xoff flow control
185 #define EFR_SWFC_MASK 0x0F // Mask for software flow control field
188 #define EFR_AUTO_RTS 0x40 // Use RTS for Rx flow control
189 #define EFR_AUTO_CTS 0x80 // Use CTS for Tx flow control