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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
[all …]
H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-beacon-baseboard.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 compatible = "gpio-leds";
15 default-state = "off";
21 default-state = "off";
27 default-state = "off";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_led3>;
35 linux,default-trigger = "heartbeat";
39 pcie0_refclk: pcie0-refclk {
[all …]
H A Dimx8mp-venice-gw7905.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
11 led-controller {
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
16 led-0 {
20 default-state = "on";
[all …]
H A Dimx8mq-mnt-reform2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright 2019-2021 MNT Research GmbH
8 /dts-v1/;
10 #include "imx8mq-nitrogen-som.dtsi"
14 compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
15 chassis-type = "laptop";
18 compatible = "pwm-backlight";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_backlight>;
22 power-supply = <&reg_main_usb>;
[all …]
H A Dimx8mq-tqma8mq-mba8mx.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2019-2021 TQ-Systems GmbH
6 /dts-v1/;
8 #include "imx8mq-tqma8mq.dtsi"
12 model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
13 compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
23 extcon_usbotg: extcon-usbotg0 {
24 compatible = "linux,extcon-usb-gpio";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_usbcon0>;
[all …]
H A Dimx8mm-venice-gw7905.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
11 led-controller {
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
16 led-0 {
20 default-state = "on";
[all …]
H A Dimx8mp-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
16 stdout-path = &uart2;
19 hdmi-connector {
20 compatible = "hdmi-connector";
26 remote-endpoint = <&adv7535_out>;
31 gpio-leds {
32 compatible = "gpio-leds";
[all …]
H A Dimx8mm-evk.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h>
14 stdout-path = &uart2;
22 hdmi-connector {
23 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
35 compatible = "gpio-leds";
36 pinctrl-names = "default";
[all …]
H A Dimx8mm-innocomm-wb15.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 reg_modem: regulator-modem {
11 compatible = "regulator-fixed";
12 pinctrl-names = "default";
13 pinctrl-0 = <&pinctrl_modem_regulator>;
14 regulator-min-microvolt = <3300000>;
15 regulator-max-microvolt = <3300000>;
16 regulator-name = "epdev_on";
18 enable-active-high;
[all …]
H A Dimx8mp-venice-gw74xx.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
30 stdout-path = &uart2;
38 gpio-keys {
39 compatible = "gpio-keys";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
25 - description: pipe clock
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dchipone-icn6211.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/media-bus-format.h>
155 struct clk *refclk; member
214 return ret == val_size ? 0 : -EINVAL; in chipone_dsi_read()
240 ret = regmap_read(icn->regmap, reg, &pval); in chipone_readb()
247 return regmap_write(icn->regmap, reg, val); in chipone_writeb()
254 unsigned int mode_clock = mode->clock * 1000; in chipone_configure_pll()
271 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider in chipone_configure_pll()
274 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider in chipone_configure_pll()
276 * It seems the PLL input clock after applying P pre-divider have in chipone_configure_pll()
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
90 u16 enable; member
148 struct clk *refclk; member
156 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
158 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
166 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
167 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
168 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
170 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
[all …]
/openbmc/linux/drivers/net/ethernet/ti/
H A Dam65-cpts.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
9 #include <linux/clk-provider.h>
23 #include "am65-cpts.h"
44 u32 ts_load_en; /* Time stamp load enable */
49 u32 int_enable; /* Time sync interrupt enable */
164 struct clk *refclk; member
201 #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
202 #define am65_cpts_read32(c, r) readl(&(c)->reg->r)
219 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; in am65_cpts_set_add_val()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-bosch-acc.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Support for the i.MX6-based Bosch ACC board.
8 * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
20 compatible = "bosch,imx6q-acc", "fsl,imx6q";
37 backlight_lvds: backlight-lvds {
38 compatible = "pwm-backlight";
40 brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
[all …]
H A Dimx6q-h100.dts4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
45 #include "imx6qdl-sr-som.dtsi"
46 #include "imx6qdl-sr-som-brcm.dtsi"
64 stdout-path = &uart2;
67 hdmi_osc: hdmi-osc {
68 compatible = "fixed-clock";
69 clock-output-names = "hdmi-osc";
70 clock-frequency = <27000000>;
71 #clock-cells = <0>;
[all …]
H A Dimx6qdl-icore-rqs.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/imx6qdl-clock.h>
9 #include <dt-bindings/sound/fsl-imx-audmux.h>
17 reg_1p8v: regulator-1p8v {
18 compatible = "regulator-fixed";
19 regulator-name = "1P8V";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-boot-on;
[all …]
/openbmc/u-boot/drivers/video/
H A Dmvebu_lcd.c1 // SPDX-License-Identifier: GPL-2.0+
113 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
114 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()
115 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in mvebu_lcd_conf_mbus_registers()
116 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()
119 writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i)); in mvebu_lcd_conf_mbus_registers()
128 int x = lcd_info->x_res; in mvebu_lcd_register_init()
129 int y = lcd_info->y_res; in mvebu_lcd_register_init()
144 * end (currently 1GB-64MB but also may be 2GB-64MB). in mvebu_lcd_register_init()
147 writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR0); in mvebu_lcd_register_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
[all …]
H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
[all …]
H A Dk3-am65-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
9 mcu_conf: scm-conf@40f00000 {
10 compatible = "syscon", "simple-mfd";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 compatible = "ti,am654-phy-gmii-sel";
19 #phy-cells = <1>;
25 compatible = "pinctrl-single";
27 #pinctrl-cells = <1>;
[all …]
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
303 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
308 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
317 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
327 if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) in tegra_pcie_icc_set()
328 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
[all …]

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