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/openbmc/linux/drivers/memory/tegra/
H A Dtegra20-emc.c216 * There are multiple sources in the EMC driver which could request
237 struct tegra_emc *emc = data; in tegra_emc_isr() local
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
256 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
262 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
263 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
264 timing = &emc->timings[i]; in tegra_emc_find_timing()
270 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
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H A Dtegra186-emc.c42 * to control the EMC frequency. The top-level directory can be found here:
44 * /sys/kernel/debug/emc
49 * EMC frequencies.
53 * configured EMC frequency, this will cause the frequency to be
58 * the value is lower than the currently configured EMC frequency, this
63 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, in tegra186_emc_validate_rate() argument
68 for (i = 0; i < emc->num_dvfs; i++) in tegra186_emc_validate_rate()
69 if (rate == emc->dvfs[i].rate) in tegra186_emc_validate_rate()
78 struct tegra186_emc *emc = s->private; in tegra186_emc_debug_available_rates_show() local
82 for (i = 0; i < emc->num_dvfs; i++) { in tegra186_emc_debug_available_rates_show()
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H A Dtegra30-emc.c5 * Based on downstream driver from NVIDIA and tegra124-emc.c
387 * There are multiple sources in the EMC driver which could request
398 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
418 struct tegra_emc *emc = data; in tegra_emc_isr() local
422 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
428 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
432 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
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H A Dtegra210-emc-core.c21 #include "tegra210-emc.h"
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
572 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_train()
574 mod_timer(&emc->training, in tegra210_emc_train()
575 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_train()
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H A Dtegra124-emc.c507 * There are multiple sources in the EMC driver which could request
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
525 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
542 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument
547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
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H A Dtegra210-emc-cc-r21021.c14 #include "tegra210-emc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%lu) EMA: %u\n", \
116 static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type) in update_clock_tree_delay() argument
119 struct tegra210_emc_timing *last = emc->last; in update_clock_tree_delay()
120 struct tegra210_emc_timing *next = emc->next; in update_clock_tree_delay()
134 value = tegra210_emc_mrr_read(emc, 2, 19); in update_clock_tree_delay()
136 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
145 value = tegra210_emc_mrr_read(emc, 2, 18); in update_clock_tree_delay()
147 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
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H A Dtegra210-emc-table.c8 #include "tegra210-emc.h"
15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local
21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init()
33 if (emc->derated) { in tegra210_emc_table_device_init()
34 dev_warn(dev, "excess EMC table '%s'\n", rmem->name); in tegra210_emc_table_device_init()
38 if (emc->nominal) { in tegra210_emc_table_device_init()
39 if (count != emc->num_timings) { in tegra210_emc_table_device_init()
41 count, emc->num_timings); in tegra210_emc_table_device_init()
46 emc->derated = timings; in tegra210_emc_table_device_init()
48 emc->num_timings = count; in tegra210_emc_table_device_init()
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H A DMakefile16 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
17 obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o
18 obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
19 obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
20 obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
21 obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o
22 obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o
23 obj-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186-emc.o
25 tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o
/openbmc/qemu/hw/net/
H A Dnpcm7xx_emc.c2 * Nuvoton NPCM7xx EMC Module
98 static void emc_reset(NPCM7xxEMCState *emc) in emc_reset() argument
102 trace_npcm7xx_emc_reset(emc->emc_num); in emc_reset()
104 memset(&emc->regs[0], 0, sizeof(emc->regs)); in emc_reset()
107 emc->regs[REG_TXDLSA] = 0xfffffffc; in emc_reset()
108 emc->regs[REG_RXDLSA] = 0xfffffffc; in emc_reset()
109 emc->regs[REG_MIIDA] = 0x00900000; in emc_reset()
110 emc->regs[REG_FFTCR] = 0x0101; in emc_reset()
111 emc->regs[REG_DMARFC] = 0x0800; in emc_reset()
112 emc->regs[REG_MPCNT] = 0x7fff; in emc_reset()
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/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-jetson-tk1-emc.dtsi7 emc-timings-3 {
14 clock-names = "emc-parent";
21 clock-names = "emc-parent";
28 clock-names = "emc-parent";
35 clock-names = "emc-parent";
42 clock-names = "emc-parent";
49 clock-names = "emc-parent";
56 clock-names = "emc-parent";
63 clock-names = "emc-parent";
70 clock-names = "emc-parent";
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H A Dtegra124-apalis-emc.dtsi11 emc-timings-1 {
18 clock-names = "emc-parent";
25 clock-names = "emc-parent";
32 clock-names = "emc-parent";
39 clock-names = "emc-parent";
46 clock-names = "emc-parent";
53 clock-names = "emc-parent";
60 clock-names = "emc-parent";
67 clock-names = "emc-parent";
74 clock-names = "emc-parent";
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H A Dtegra124-nyan-blaze-emc.dtsi7 emc-timings-1 {
14 clock-names = "emc-parent";
21 clock-names = "emc-parent";
28 clock-names = "emc-parent";
35 clock-names = "emc-parent";
42 clock-names = "emc-parent";
49 clock-names = "emc-parent";
56 clock-names = "emc-parent";
63 clock-names = "emc-parent";
72 clock-names = "emc-parent";
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H A Dtegra30-asus-tf300t.dts146 emc-timings-0 {
211 emc-timings-1 {
276 emc-timings-2 {
343 emc-timings-0 {
350 nvidia,emc-auto-cal-interval = <0x001fffff>;
351 nvidia,emc-mode-1 = <0x80100003>;
352 nvidia,emc-mode-2 = <0x80200008>;
353 nvidia,emc-mode-reset = <0x80001221>;
354 nvidia,emc-zcal-cnt-long = <0x00000040>;
355 nvidia,emc-cfg-dyn-self-ref;
[all …]
H A Dtegra30-asus-tf300tg.dts220 emc-timings-0 {
285 emc-timings-1 {
350 emc-timings-2 {
417 emc-timings-0 {
424 nvidia,emc-auto-cal-interval = <0x001fffff>;
425 nvidia,emc-mode-1 = <0x80100003>;
426 nvidia,emc-mode-2 = <0x80200048>;
427 nvidia,emc-mode-reset = <0x80001221>;
428 nvidia,emc-zcal-cnt-long = <0x00000040>;
429 nvidia,emc-cfg-dyn-self-ref;
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H A Dtegra30-asus-tf201.dts112 emc-timings-0 {
167 emc-timings-1 {
224 emc-timings-0 {
231 nvidia,emc-auto-cal-interval = <0x001fffff>;
232 nvidia,emc-mode-1 = <0x00010022>;
233 nvidia,emc-mode-2 = <0x00020001>;
234 nvidia,emc-mode-reset = <0x00000000>;
235 nvidia,emc-zcal-cnt-long = <0x00000009>;
236 nvidia,emc-cfg-periodic-qrst;
238 nvidia,emc-configuration = < 0x00000001
[all …]
H A Dtegra30-asus-tf700t.dts141 emc-timings-0 {
206 emc-timings-1 {
273 emc-timings-0 {
280 nvidia,emc-auto-cal-interval = <0x001fffff>;
281 nvidia,emc-mode-1 = <0x80100003>;
282 nvidia,emc-mode-2 = <0x80200008>;
283 nvidia,emc-mode-reset = <0x80001221>;
284 nvidia,emc-zcal-cnt-long = <0x00000040>;
285 nvidia,emc-cfg-dyn-self-ref;
286 nvidia,emc-cfg-periodic-qrst;
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H A Dtegra124-nyan-big-emc.dtsi7 emc-timings-1 {
14 clock-names = "emc-parent";
21 clock-names = "emc-parent";
28 clock-names = "emc-parent";
35 clock-names = "emc-parent";
42 clock-names = "emc-parent";
49 clock-names = "emc-parent";
56 clock-names = "emc-parent";
63 clock-names = "emc-parent";
70 clock-names = "emc-parent";
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H A Dtegra30-pegatron-chagall.dts1535 emc-timings-0 {
1590 emc-timings-1 {
1645 emc-timings-2 {
1700 emc-timings-3 {
1757 emc-timings-0 {
1764 nvidia,emc-auto-cal-interval = <0x001fffff>;
1765 nvidia,emc-mode-1 = <0x00010022>;
1766 nvidia,emc-mode-2 = <0x00020001>;
1767 nvidia,emc-mode-reset = <0x00000000>;
1768 nvidia,emc-zcal-cnt-long = <0x00000009>;
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/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra20-emc.c3 * Based on drivers/clk/tegra/clk-emc.c
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
57 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
68 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_get_parent() local
70 return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT; in emc_get_parent()
75 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_set_parent() local
78 val = readl_relaxed(emc->reg); in emc_set_parent()
84 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter) in emc_set_parent()
89 if (emc->mc_same_freq) in emc_set_parent()
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H A Dclk-tegra210-emc.c53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()
75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate()
81 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_recalc_rate()
92 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_round_rate() local
93 struct tegra210_clk_emc_provider *provider = emc->provider; in tegra210_clk_emc_round_rate()
107 static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc, in tegra210_clk_emc_find_parent() argument
110 struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index); in tegra210_clk_emc_find_parent()
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c18 #include <asm/arch/emc.h>
22 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; variable
28 /* Enable EMC interface and choose little endian mode */ in ddr_init()
29 writel(1, &emc->ctrl); in ddr_init()
30 writel(0, &emc->config); in ddr_init()
31 /* Select maximum EMC Dynamic Memory Refresh Time */ in ddr_init()
32 writel(0x7FF, &emc->refresh); in ddr_init()
37 writel(dram->config0, &emc->config0); in ddr_init()
38 writel(dram->rascas0, &emc->rascas0); in ddr_init()
39 writel(dram->rdconfig, &emc->read_config); in ddr_init()
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
30 - const: emc
51 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-config:
77 nvidia,emc-auto-cal-config2:
83 nvidia,emc-auto-cal-config3:
89 nvidia,emc-auto-cal-interval:
96 nvidia,emc-bgbias-ctl0:
[all …]
H A Dnvidia,tegra30-emc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
23 const: nvidia,tegra30-emc
53 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-interval:
78 nvidia,emc-mode-1:
83 nvidia,emc-mode-2:
88 nvidia,emc-mode-reset:
[all …]
H A Dnvidia,tegra20-emc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
18 parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
23 const: nvidia,tegra20-emc
61 If present, the emc-tables@ sub-nodes will be addressed.
64 emc-table:
68 const: nvidia,tegra20-emc-table
82 nvidia,emc-registers:
84 EMC timing characterization data. These are the registers
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Demc.c12 #include <asm/arch/emc.h>
16 * The EMC registers have shadow registers. When the EMC clock is updated
20 * and relies on the clock lock on the emc clock to avoid races between
104 * Find EMC tables for the given ram code.
106 * The tegra EMC binding has two options, one using the ram code and one not.
108 * If this is not present, then the EMC tables are directly below 'node',
109 * otherwise we select the correct emc-tables subnode based on the 'ram_code'
113 * @param node EMC node (nvidia,tegra20-emc compatible string)
146 if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL))) in find_emc_tables()
160 * Decode the EMC node of the device tree, returning a pointer to the emc
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