Lines Matching full:emc
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
23 const: nvidia,tegra30-emc
53 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-interval:
78 nvidia,emc-mode-1:
83 nvidia,emc-mode-2:
88 nvidia,emc-mode-reset:
93 nvidia,emc-zcal-cnt-long:
95 Number of EMC clocks to wait before issuing any commands after
101 nvidia,emc-cfg-dyn-self-ref:
106 nvidia,emc-cfg-periodic-qrst:
111 nvidia,emc-configuration:
113 EMC timing characterization data. These are the registers
114 (see section "18.13.2 EMC Registers" in the TRM) whose values
210 - nvidia,emc-auto-cal-interval
211 - nvidia,emc-mode-1
212 - nvidia,emc-mode-2
213 - nvidia,emc-mode-reset
214 - nvidia,emc-zcal-cnt-long
215 - nvidia,emc-configuration
238 compatible = "nvidia,tegra30-emc";
249 emc-timings-1 {
255 nvidia,emc-auto-cal-interval = <0x001fffff>;
256 nvidia,emc-mode-1 = <0x80100002>;
257 nvidia,emc-mode-2 = <0x80200018>;
258 nvidia,emc-mode-reset = <0x80000b71>;
259 nvidia,emc-zcal-cnt-long = <0x00000040>;
260 nvidia,emc-cfg-periodic-qrst;
262 nvidia,emc-configuration = <