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/openbmc/linux/Documentation/devicetree/bindings/opp/
H A Dti,omap-opp-supply.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/ti,omap-opp-supply.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 OMAP5, DRA7, and AM57 families of SoCs have Class 0 AVS eFuse
11 registers, which contain OPP-specific voltage information tailored
16 Also, some supplies may have an associated vbb-supply, an Adaptive
18 w.r.t the vdd-supply and clk when making an OPP transition. By
20 transitions, we can use the multi-regulator support implemented by
22 OPP core binding Documentation/devicetree/bindings/opp/opp-v2.yaml
[all …]
/openbmc/linux/drivers/opp/
H A Dti-opp-supply.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
5 * Dave Gerlach <d-gerlach@ti.com>
25 * struct ti_opp_supply_optimum_voltage_table - optimized voltage table
27 * @optimized_uv: Optimized voltage from efuse
35 * struct ti_opp_supply_data - OMAP specific opp supply data
53 * struct ti_opp_supply_of_data - device tree match data
55 * @efuse_voltage_mask: mask required for efuse register representing voltage
56 * @efuse_voltage_uv: Are the efuse entries in micro-volts? if not, assume
57 * milli-volts.
[all …]
/openbmc/linux/drivers/phy/mediatek/
H A Dphy-mtk-pcie.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/nvmem-consumer.h>
15 #include "phy-mtk-io.h"
36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
50 * struct mtk_pcie_phy_data - phy data for each SoC
52 * @sw_efuse_supported: support software to load eFuse data
60 * struct mtk_pcie_phy - PCIe phy driver main structure
65 * @sw_efuse_en: software eFuse enable status
67 * @efuse: pointer to eFuse data for each lane
[all …]
/openbmc/linux/drivers/nvmem/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 tristate "Apple eFuse support"
37 calibration data required for the PCIe or the USB-C PHY.
40 be called nvmem-apple-efuses.
43 tristate "Broadcom On-Chip OTP Controller support"
52 will be called nvmem-bcm-ocotp.
72 will be called nvmem-imx-iim.
75 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
79 This is a driver for the On-Chip OTP Controller (OCOTP) available on
80 i.MX6 SoCs, providing access to 4 Kbits of one-time programmable
[all …]
H A Dqfprom.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/nvmem-provider.h>
23 /* Amount of time required to hold charge to blow fuse in micro-seconds */
44 * struct qfprom_soc_data - config that varies from SoC to SoC.
47 * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
50 * @qfprom_blow_uV: LDO voltage to be set when doing efuse blow
60 * struct qfprom_priv - structure holding qfprom attributes
62 * @qfpraw: iomapped memory space for qfprom-efuse raw address space.
63 * @qfpconf: iomapped memory space for qfprom-efuse configuration address
84 * struct qfprom_touched_values - saved values to restore after blowing
[all …]
/openbmc/u-boot/doc/
H A DREADME.armada-secureboot16 -------------------------------
24 pertaining to the boot process. Furthermore, a eFuse structure (a
25 one-time-writeable memory) need to be configured in the correct way.
30 key from it, and verify its SHA-256 hash against a SHA-256 stored in a eFuse
43 * The SHA-256 value in the eFuse field verifies the "root" public key.
47 In the special case of building a boot image containing U-Boot as the binary
52 2. Creation of a conforming boot image containing the U-Boot image as binary
54 3. Burning the necessary eFuse values.
56 (1) will be addressed later, (2) will be taken care of by U-Boot's build
58 data (essentially a series of U-Boot commands to be entered at the U-Boot
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/openbmc/u-boot/board/gateworks/gw_ventana/
H A DREADME1 U-Boot for the Gateworks Ventana Product Family boards
3 This file contains information for the port of U-Boot to the Gateworks
7 is supported by a single bootloader build by using a common SPL and U-Boot
13 ---------------------------------
19 will build the following artifacts from U-Boot source:
20 - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
22 The DRAM controller, loads u-boot.img from the detected boot device,
25 - u-boot.img - The main U-Boot core which is u-boot.bin with a image header.
29 --------
31 To build U-Boot for the Gateworks Ventana product family:
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/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0+ */
220 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
221 /* ES1.0 settings */
230 /* ES2.0 settings */
238 /* Efuse register offsets for OMAP5 platform */
254 /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
261 /* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
266 /* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
271 /* Efuse register offsets for DRA7xx platform */
H A Domap.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 * L4 Peripherals - L4 Wakeup and L4 Core now
82 /* Watchdog Timer2 - MPU watchdog */
200 #define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
219 /* ABB settings */
230 /* ABB efuse masks */
/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dmicrochip,sama7g5-otpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
15 settings, chip identifiers) or user specific data could be stored.
18 - $ref: nvmem.yaml#
23 - const: microchip,sama7g5-otpc
24 - const: syscon
30 - compatible
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
12 target-module@42c01900 {
13 compatible = "ti,sysc-dra7-mcan", "ti,sysc";
15 #address-cells = <1>;
16 #size-cells = <1>;
20 reg-names = "rev", "sysc", "syss";
21 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
23 ti,syss-mask = <1>;
25 clock-names = "fck";
[all …]
H A Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dmt6315-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/mt6315-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
15 by different efuse settings.
19 const: mediatek,mt6315-regulator
29 "^vbuck[1-4]$":
37 - compatible
38 - reg
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dabb.c1 // SPDX-License-Identifier: GPL-2.0+
17 * On OMAP5+ some ABB settings are fused. They are handled
20 * 1. corresponding EFUSE register contains ABB enable bit
44 return -1; in abb_setup_ldovbb()
48 vset >>= ffs(fuse_vset_mask) - 1; in abb_setup_ldovbb()
49 vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; in abb_setup_ldovbb()
/openbmc/u-boot/board/ti/am57xx/
H A Dboard.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
66 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
133 /* Ext phy ctrl regs 1-35 */
324 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
325 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
333 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-inno-hdmi.txt4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
13 - #clock-cells: should be 0.
14 - clock-output-names : shall be the name for the output clock.
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhwinit.c1 // SPDX-License-Identifier: GPL-2.0+
54 writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); in do_io_settings()
55 writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); in do_io_settings()
58 (*ctrl)->control_lpddr2io1_2); in do_io_settings()
59 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); in do_io_settings()
62 writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); in do_io_settings()
63 writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); in do_io_settings()
66 (*ctrl)->control_lpddr2io2_2); in do_io_settings()
67 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); in do_io_settings()
70 * Some of these settings (TRIM values) come from eFuse and are in do_io_settings()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dclocks-common.c1 // SPDX-License-Identifier: GPL-2.0+
49 * due to hw issue. So, use hard-coded value. If this value is not in __get_sys_clk_index()
50 * correct for any board over-ride this function in board file in __get_sys_clk_index()
57 /* SYS_CLKSEL - 1 to match the dpll param array indices */ in __get_sys_clk_index()
58 ind = (readl((*prcm)->cm_sys_clksel) & in __get_sys_clk_index()
59 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; in __get_sys_clk_index()
77 /* Setup post-dividers */ in setup_post_dividers()
78 if (params->m2 >= 0) in setup_post_dividers()
79 writel(params->m2, &dpll_regs->cm_div_m2_dpll); in setup_post_dividers()
80 if (params->m3 >= 0) in setup_post_dividers()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
11 #include <dt-bindings/clock/maxim,max77802.h>
12 #include <dt-bindings/regulator/maxim,max77802.h>
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
34 compatible = "pwm-backlight";
[all …]
H A Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/input/input.h>
48 samsung,bl1-offset = <0x1400>;
49 samsung,bl2-offset = <0x3400>;
50 u-boot-memory = "/memory";
51 u-boot-offset = <0x3e00000 0x100000>;
56 #address-cells = <1>;
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8723b.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTL8XXXU mac80211 USB driver - 8723b specific subdriver
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
254 * they never actually check the package type - and just default
309 struct device *dev = &priv->udev->dev; in rtl8723bu_identify_chip()
314 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8723bu_identify_chip()
317 ret = -ENOTSUPP; in rtl8723bu_identify_chip()
321 strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name)); in rtl8723bu_identify_chip()
322 priv->rtl_chip = RTL8723B; in rtl8723bu_identify_chip()
[all …]
H A Drtl8xxxu_8192e.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTL8XXXU mac80211 USB driver - 8192e specific subdriver
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
483 struct device *dev = &priv->udev->dev; in rtl8192eu_identify_chip()
488 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8192eu_identify_chip()
491 ret = -ENOTSUPP; in rtl8192eu_identify_chip()
498 strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
499 priv->tx_paths = 1; in rtl8192eu_identify_chip()
500 priv->rtl_chip = RTL8191E; in rtl8192eu_identify_chip()
[all …]
/openbmc/u-boot/board/silica/pengwyn/
H A Dboard.c1 // SPDX-License-Identifier: GPL-2.0+
65 /* break into full u-boot on 'c' */ in spl_start_uboot()
72 266, OSC-1, 1, -1, -1, -1, -1};
74 303, OSC-1, 1, -1, -1, -1, -1};
76 400, OSC-1, 1, -1, -1, -1, -1};
101 /* future configs can return other clock settings */ in get_dpll_ddr_params()
128 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
175 printf("<ethaddr> not set. Reading from E-fuse\n"); in board_eth_init()
176 /* try reading mac address from efuse */ in board_eth_init()
177 mac_lo = readl(&cdev->macid0l); in board_eth_init()
[all …]
/openbmc/linux/drivers/regulator/
H A Dti-abb-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2012-2013 Texas Instruments, Inc.
27 * FAST_OPP: sets ABB LDO to Forward Body-Bias
28 * SLOW_OPP: sets ABB LDO to Reverse Body-Bias
35 * struct ti_abb_info - ABB information per voltage setting
48 * struct ti_abb_reg - Register description for ABB block
51 * @sr2_wtcnt_value_mask: setup register- sr2_wtcnt_value mask
52 * @fbb_sel_mask: setup register- FBB sel mask
53 * @rbb_sel_mask: setup register- RBB sel mask
54 * @sr2_en_mask: setup register- enable mask
[all …]
/openbmc/linux/drivers/remoteproc/
H A Dti_k3_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
9 #include <linux/dma-mapping.h>
19 #include <linux/omap-mailbox.h>
33 /* R5 TI-SCI Processor Configuration Flags */
47 /* R5 TI-SCI Processor Control Flags */
50 /* R5 TI-SCI Processor Status Flags */
59 * struct k3_r5_mem - internal memory structure
77 * Single-CPU mode : AM64x SoCs only
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