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/openbmc/smbios-mdr/include/
H A Dcpu.hpp8 // http://www.apache.org/licenses/LICENSE-2.0
77 {0x1b, "K6-2"},
78 {0x1c, "K6-3"},
81 {0x1f, "K6-2+"},
90 {0x28, "Intel Core Duo processor"},
91 {0x29, "Intel Core Duo mobile processor"},
92 {0x2a, "Intel Core Solo mobile processor"},
94 {0x2c, "Intel Core M processor"},
95 {0x2d, "Intel Core m3 processor"},
96 {0x2e, "Intel Core m5 processor"},
[all …]
/openbmc/linux/drivers/media/pci/cx88/
H A Dcx88-dsp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "cx88-reg.h"
77 return -int_cos(x - INT_PI); in int_cos()
80 return -int_cos(INT_PI / 2 - (x % (INT_PI / 2))); in int_cos()
89 ret = 32768 - t2 + t4 - t6 + t8; in int_cos()
108 s32 s = x[i] + ((s64)coeff * s_prev / 32768) - s_prev2; in int_goertzel()
114 tmp = (s64)s_prev2 * s_prev2 + (s64)s_prev * s_prev - in int_goertzel()
143 x += (N - 192); in noise_magnitude()
147 freq_step = (freq_end - freq_start) / (samples - 1); in noise_magnitude()
157 static s32 detect_a2_a2m_eiaj(struct cx88_core *core, s16 x[], u32 N) in detect_a2_a2m_eiaj() argument
[all …]
/openbmc/linux/drivers/usb/cdns3/
H A DKconfig8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
34 Cadence USBSS-DEV driver.
51 tristate "Cadence USB3 support on PCIe-based platforms"
55 If you're using the USBSS Core IP with a PCIe, please say
59 be dynamically linked and module will be called cdns3-pci.ko
67 platforms that contain Cadence USB3 controller core.
[all …]
/openbmc/linux/drivers/usb/dwc2/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 tristate "DesignWare USB2 DRD Core Support"
10 Say Y here if your system has a Dual Role Hi-Speed USB
11 controller based on the DesignWare HSOTG IP Core.
14 linked modules, the core module will be called dwc2.ko, the PCI
18 dwc2_platform.ko. For all modes(host, gadget and dual-role), there
33 The Designware USB2.0 high-speed host controller
35 driver to operate in Host-only mode.
37 comment "Gadget/Dual-role mode requires USB Gadget support to be enabled"
43 The Designware USB2.0 high-speed gadget controller
[all …]
/openbmc/linux/Documentation/arch/arm/
H A Dmarvell.rst13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Dadvantech,idk-2121wr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/advantech,idk-2121wr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Advantech IDK-2121WR 21.5" Full-HD dual-LVDS panel
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The IDK-2121WR from Advantech is a Full-HD dual-LVDS panel.
15 A dual-LVDS interface is a dual-link connection with even pixels traveling
20 dual-lvds-odd-pixels or dual-lvds-even-pixels).
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
65 bool "Integrator/CM720T core module"
71 bool "Integrator/CM920T core module"
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
89 bool "Integrator/CM10200E rev.0 core module"
95 bool "Integrator/CM10200E core module"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-controller-main.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
[all …]
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/linux/Documentation/arch/x86/
H A Dtopology.rst1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - cpuinfo_x86.x86_max_cores:
54 - cpuinfo_x86.x86_max_dies:
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
[all …]
/openbmc/u-boot/board/freescale/p1022ds/
H A DREADME2 --------
3 P1022ds is a Low End Dual core platform supporting the P1022 processor
4 of QorIQ series. P1022 is an e500 based dual core SOC.
8 -------------------------------
21 'setenv hwconfig 'audclk:12;tdm' --- error !
22 'setenv hwconfig 'audclk:11;tdm' --- error !
23 'setenv hwconfig 'audclk:10' --- error !
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
24 AM62 SoC family support a single R5F core only which runs Device Manager
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt16 communication. Xilinx provides a standard IP core that can be used to access the
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
28 Xilinx System Management Wizard fabric IP core to access the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dthine,thc63lvd1024.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
15 streams to parallel data outputs. The chip supports single/dual input/output
19 Single or dual operation mode, output data mapping and DDR output modes are
30 The device can operate in single or dual input and output modes.
33 and port@1 shall not contain any endpoint. In dual input mode,
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A DKconfig82 The AM335x high performance SOC features a Cortex-A8
83 ARM core and more.
92 The AM335x high performance SOC features a Cortex-A8
93 ARM core and more.
112 The AM43xx high performance SOC features a Cortex-A9
113 ARM core, a quad core PRU-ICSS for industrial Ethernet
114 protocols, dual camera support, optional 3D graphics
130 The AM335x high performance SOC features a Cortex-A8
131 ARM core, a dual core PRU-ICSS for industrial Ethernet
149 Reserved EMIF region start address. Set to "0" to auto-select
[all …]
/openbmc/u-boot/board/intel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
23 mini-ITX form factor containing the Intel Braswell SoC, which has
24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
25 serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
48 This is the Intel Edison Compute Module. It contains a dual core Intel
50 eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
56 Arduino-certified development and prototyping boards based on Intel
57 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
58 single-core, single-thread, Intel Pentium processor instrunction set
[all …]
/openbmc/linux/drivers/usb/dwc3/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 tristate "DesignWare USB3 DRD Core Support"
10 Say Y or M here if your system has a Dual Role SuperSpeed
11 USB controller based on the DesignWare USB3 IP Core.
46 bool "Dual Role mode"
74 Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
78 tristate "PCIe-based Platforms"
82 If you're using the DesignWare Core IP with a PCIe (but not HAPS
86 tristate "Synopsys PCIe-based HAPS Platforms"
90 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dst,stusb160x.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STUSB160x Type-C controller
10 - Amelie Delaunay <amelie.delaunay@foss.st.com>
15 - st,stusb1600
23 vdd-supply:
24 description: main power supply (4.1V-22V)
26 vsys-supply:
27 description: low power supply (3.0V-5.5V)
[all …]
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/u-boot/board/theobroma-systems/puma_rk3399/
H A DREADME4 The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
5 RK3399 in a Qseven-compatible form-factor.
7 RK3399-Q7 features:
8 * CPU: ARMv8 64bit Big-Little architecture,
9 * Big: dual-core Cortex-A72
10 * Little: quad-core Cortex-A53
12 * DRAM: 4GB-128MB dual-channel
17 * USB3.0 dual role port
22 * Companion Controller: onboard additional Cortex-M0 microcontroller
27 Here is the step-by-step to boot to U-Boot on rk3399.
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun6i-a31s-sina31s-core.dtsi2 * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
43 /dts-v1/;
44 #include "sun6i-a31s.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
50 model = "Sinlinx SinA31s Core Board";
51 compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s";
59 cpu-supply = <&reg_dcdc3>;
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun6i-a31s-sina31s-core.dtsi2 * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
43 /dts-v1/;
44 #include "sun6i-a31s.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
50 model = "Sinlinx SinA31s Core Board";
51 compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s";
59 cpu-supply = <&reg_dcdc3>;
[all …]
H A Dsun8i-a23-gt90h-v4.dts4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
43 /dts-v1/;
44 #include "sun8i-a23.dtsi"
45 #include "sun8i-reference-design-tablet.dtsi"
48 model = "Allwinner GT90H Dual Core Tablet (v4)";
49 compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23";
59 firmware-name = "gsl3675-gt90h.fw";
60 touchscreen-size-x = <1792>;
61 touchscreen-size-y = <1024>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dst,stm32-bxcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Dario Binacchi <dario.binacchi@amarulasolutions.com>
15 - $ref: can-controller.yaml#
20 - st,stm32f4-bxcan
22 st,can-primary:
25 two CAN peripherals in dual CAN configuration. In that case they share
32 st,can-secondary:
[all …]

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