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/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt36523.c26 #define mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, cmd, seq...) \ argument
28 mipi_dsi_dcs_write_seq(dsi0, cmd, seq); \
70 struct mipi_dsi_device *dsi0 = pinfo->dsi[0]; in elish_boe_init_sequence() local
73 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10); in elish_boe_init_sequence()
74 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01); in elish_boe_init_sequence()
75 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x05); in elish_boe_init_sequence()
76 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20); in elish_boe_init_sequence()
77 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01); in elish_boe_init_sequence()
78 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x18, 0x40); in elish_boe_init_sequence()
79 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10); in elish_boe_init_sequence()
[all …]
/openbmc/linux/drivers/gpu/drm/vc4/tests/
H A Dvc4_test_pv_muxing.c199 VC4_PV_MUXING_TEST("1 output: DSI0",
211 VC4_PV_MUXING_TEST("2 outputs: DSI0, HDMI0",
214 VC4_PV_MUXING_TEST("2 outputs: DSI0, VEC",
217 VC4_PV_MUXING_TEST("2 outputs: DSI0, DSI1",
220 VC4_PV_MUXING_TEST("2 outputs: DSI0, TXP",
247 VC4_PV_MUXING_TEST("3 outputs: DSI0, HDMI0, DSI1",
251 VC4_PV_MUXING_TEST("3 outputs: DSI0, HDMI0, TXP",
255 VC4_PV_MUXING_TEST("3 outputs: DSI0, VEC, DSI1",
259 VC4_PV_MUXING_TEST("3 outputs: DSI0, VEC, TXP",
286 VC4_PV_MUXING_TEST("DPI/DSI0 Conflict",
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dbrcm,bcm2835-cprman.txt25 - DSI0 byte clock
26 - DSI0 DDR2 clock
27 - DSI0 DDR clock
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dbrcm,bcm2835-dsi0.yaml4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-dsi0.yaml#
22 - brcm,bcm2835-dsi0
H A Dallwinner,sun6i-a31-mipi-dsi.yaml108 dsi0: dsi@1ca0000 {
H A Dste,mcde.yaml129 dsi0: dsi@a0351000 {
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm283x.dtsi96 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
358 dsi0: dsi@7e209000 { label
359 compatible = "brcm,bcm2835-dsi0";
H A Dbcm2835-rpi.dtsi63 &dsi0 {
/openbmc/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun50i-a100.c204 SUNXI_FUNCTION(0x4, "dsi0"), /* DP0 */
211 SUNXI_FUNCTION(0x4, "dsi0"), /* DM0 */
218 SUNXI_FUNCTION(0x4, "dsi0"), /* DP1 */
225 SUNXI_FUNCTION(0x4, "dsi0"), /* DM1 */
232 SUNXI_FUNCTION(0x4, "dsi0"), /* CKP */
239 SUNXI_FUNCTION(0x4, "dsi0"), /* CKM */
246 SUNXI_FUNCTION(0x4, "dsi0"), /* DP2 */
253 SUNXI_FUNCTION(0x4, "dsi0"), /* DM2 */
259 SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
265 SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
/openbmc/qemu/include/hw/misc/
H A Dbcm2835_cprman_internals.h326 .name = "plla-dsi0",
327 FILL_PLL_CHANNEL_INIT_INFO(PLLA, DSI0),
360 .name = "plld-dsi0",
361 FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI0),
492 * The DSI0 channels. This one got an intermediate mux between the PLL channels
590 FILL_CLOCK_MUX_INIT_INFO(DSI0E, dsi0),
596 FILL_CLOCK_MUX_INIT_INFO(DSI0P, dsi0),
/openbmc/u-boot/arch/arm/dts/
H A Dbcm283x.dtsi126 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
435 dsi0: dsi@7e209000 { label
436 compatible = "brcm,bcm2835-dsi0";
H A Dbcm2835-rpi.dtsi102 &dsi0 {
/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Dstartek,kd070fhfid015.yaml49 dsi0 {
H A Dnovatek,nt36672a.yaml66 dsi0 {
H A Dsharp,lq101r1sx01.yaml65 dsi0: dsi@fd922800 {
H A Dnovatek,nt35950.yaml69 dsi0 {
/openbmc/linux/drivers/gpu/drm/vc4/
H A Dvc4_dsi.c7 * DOC: VC4 DSI0/DSI1 module
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
14 * while the compute module brings both DSI0 and DSI1 out.
17 * currently, with most of the information necessary for DSI0
539 /* Whether we're on bcm2835's DSI0 or DSI1. */
623 /* DSI0 should be able to write normally. */ in dsi_dma_workaround_write()
1459 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi-csi2-tx.yaml89 dsi0: dsi-encoder@fed80000 {
H A Drenesas,dsi.yaml138 dsi0: dsi@10850000 {
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3566-anbernic-rg353x.dtsi29 &dsi0 {
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dicl_dsi_regs.h12 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \ argument
13 dsi0, dsi1)
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dbrcm,bcm2835-armctrl-ic.txt83 4: DSI0
/openbmc/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,dsi.yaml101 dsi0: dsi@14014000 {
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9611uxc.c47 struct mipi_dsi_device *dsi0; member
950 lt9611uxc->dsi0 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi0_node); in lt9611uxc_probe()
951 if (IS_ERR(lt9611uxc->dsi0)) { in lt9611uxc_probe()
952 ret = PTR_ERR(lt9611uxc->dsi0); in lt9611uxc_probe()
/openbmc/linux/Documentation/gpu/
H A Dvc4.rst43 :doc: VC4 DSI0/DSI1 module

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