12abb0b99SLinus Walleij# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
22abb0b99SLinus Walleij%YAML 1.2
32abb0b99SLinus Walleij---
42abb0b99SLinus Walleij$id: http://devicetree.org/schemas/display/ste,mcde.yaml#
52abb0b99SLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml#
62abb0b99SLinus Walleij
72abb0b99SLinus Walleijtitle: ST-Ericsson Multi Channel Display Engine MCDE
82abb0b99SLinus Walleij
92abb0b99SLinus Walleijmaintainers:
102abb0b99SLinus Walleij  - Linus Walleij <linus.walleij@linaro.org>
112abb0b99SLinus Walleij
122abb0b99SLinus Walleijproperties:
132abb0b99SLinus Walleij  compatible:
142abb0b99SLinus Walleij    const: ste,mcde
152abb0b99SLinus Walleij
162abb0b99SLinus Walleij  reg:
172abb0b99SLinus Walleij    maxItems: 1
182abb0b99SLinus Walleij
192abb0b99SLinus Walleij  interrupts:
202abb0b99SLinus Walleij    maxItems: 1
212abb0b99SLinus Walleij
222abb0b99SLinus Walleij  clocks:
232abb0b99SLinus Walleij    description: an array of the MCDE clocks
242abb0b99SLinus Walleij    items:
252abb0b99SLinus Walleij      - description: MCDECLK (main MCDE clock)
262abb0b99SLinus Walleij      - description: LCDCLK (LCD clock)
272abb0b99SLinus Walleij      - description: PLLDSI (HDMI clock)
282abb0b99SLinus Walleij
292abb0b99SLinus Walleij  clock-names:
302abb0b99SLinus Walleij    items:
312abb0b99SLinus Walleij      - const: mcde
322abb0b99SLinus Walleij      - const: lcd
332abb0b99SLinus Walleij      - const: hdmi
342abb0b99SLinus Walleij
352abb0b99SLinus Walleij  resets:
362abb0b99SLinus Walleij    maxItems: 1
372abb0b99SLinus Walleij
382abb0b99SLinus Walleij  epod-supply:
392abb0b99SLinus Walleij    description: a phandle to the EPOD regulator
402abb0b99SLinus Walleij
412abb0b99SLinus Walleij  vana-supply:
422abb0b99SLinus Walleij    description: a phandle to the analog voltage regulator
432abb0b99SLinus Walleij
442abb0b99SLinus Walleij  port:
45b6755423SRob Herring    $ref: /schemas/graph.yaml#/properties/port
462abb0b99SLinus Walleij    description:
47b6755423SRob Herring      A DPI port node
482abb0b99SLinus Walleij
492abb0b99SLinus Walleij  "#address-cells":
502abb0b99SLinus Walleij    const: 1
512abb0b99SLinus Walleij
522abb0b99SLinus Walleij  "#size-cells":
532abb0b99SLinus Walleij    const: 1
542abb0b99SLinus Walleij
552abb0b99SLinus Walleij  ranges: true
562abb0b99SLinus Walleij
572abb0b99SLinus WalleijpatternProperties:
582abb0b99SLinus Walleij  "^dsi@[0-9a-f]+$":
592abb0b99SLinus Walleij    description: subnodes for the three DSI host adapters
602abb0b99SLinus Walleij    type: object
61*dca66935SRob Herring    $ref: dsi-controller.yaml#
62*dca66935SRob Herring
632abb0b99SLinus Walleij    properties:
642abb0b99SLinus Walleij      compatible:
652abb0b99SLinus Walleij        const: ste,mcde-dsi
662abb0b99SLinus Walleij
672abb0b99SLinus Walleij      reg:
682abb0b99SLinus Walleij        maxItems: 1
692abb0b99SLinus Walleij
702abb0b99SLinus Walleij      vana-supply:
712abb0b99SLinus Walleij        description: a phandle to the analog voltage regulator
722abb0b99SLinus Walleij
732abb0b99SLinus Walleij      clocks:
742abb0b99SLinus Walleij        description: phandles to the high speed and low power (energy save) clocks
752abb0b99SLinus Walleij          the high speed clock is not present on the third (dsi2) block, so it
762abb0b99SLinus Walleij          should only have the "lp" clock
772abb0b99SLinus Walleij        minItems: 1
782abb0b99SLinus Walleij        maxItems: 2
792abb0b99SLinus Walleij
802abb0b99SLinus Walleij      clock-names:
812abb0b99SLinus Walleij        oneOf:
822abb0b99SLinus Walleij          - items:
832abb0b99SLinus Walleij              - const: hs
842abb0b99SLinus Walleij              - const: lp
852abb0b99SLinus Walleij          - items:
862abb0b99SLinus Walleij              - const: lp
872abb0b99SLinus Walleij
882abb0b99SLinus Walleij    required:
892abb0b99SLinus Walleij      - compatible
902abb0b99SLinus Walleij      - reg
912abb0b99SLinus Walleij      - vana-supply
922abb0b99SLinus Walleij      - clocks
932abb0b99SLinus Walleij      - clock-names
942abb0b99SLinus Walleij
952abb0b99SLinus Walleij    unevaluatedProperties: false
962abb0b99SLinus Walleij
972abb0b99SLinus Walleijrequired:
982abb0b99SLinus Walleij  - compatible
992abb0b99SLinus Walleij  - reg
1002abb0b99SLinus Walleij  - interrupts
1012abb0b99SLinus Walleij  - clocks
1022abb0b99SLinus Walleij  - clock-names
1032abb0b99SLinus Walleij  - epod-supply
1042abb0b99SLinus Walleij  - vana-supply
1052abb0b99SLinus Walleij
1062abb0b99SLinus WalleijadditionalProperties: false
1072abb0b99SLinus Walleij
1082abb0b99SLinus Walleijexamples:
1092abb0b99SLinus Walleij  - |
1102abb0b99SLinus Walleij    #include <dt-bindings/interrupt-controller/irq.h>
1112abb0b99SLinus Walleij    #include <dt-bindings/interrupt-controller/arm-gic.h>
1122abb0b99SLinus Walleij    #include <dt-bindings/mfd/dbx500-prcmu.h>
1132abb0b99SLinus Walleij    #include <dt-bindings/gpio/gpio.h>
1142abb0b99SLinus Walleij
1152abb0b99SLinus Walleij    mcde@a0350000 {
1162abb0b99SLinus Walleij      compatible = "ste,mcde";
1172abb0b99SLinus Walleij      reg = <0xa0350000 0x1000>;
1182abb0b99SLinus Walleij      interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1192abb0b99SLinus Walleij      epod-supply = <&db8500_b2r2_mcde_reg>;
1202abb0b99SLinus Walleij      vana-supply = <&ab8500_ldo_ana_reg>;
1212abb0b99SLinus Walleij      clocks = <&prcmu_clk PRCMU_MCDECLK>,
1222abb0b99SLinus Walleij               <&prcmu_clk PRCMU_LCDCLK>,
1232abb0b99SLinus Walleij               <&prcmu_clk PRCMU_PLLDSI>;
1242abb0b99SLinus Walleij      clock-names = "mcde", "lcd", "hdmi";
1252abb0b99SLinus Walleij      #address-cells = <1>;
1262abb0b99SLinus Walleij      #size-cells = <1>;
1272abb0b99SLinus Walleij      ranges;
1282abb0b99SLinus Walleij
1292abb0b99SLinus Walleij      dsi0: dsi@a0351000 {
1302abb0b99SLinus Walleij        compatible = "ste,mcde-dsi";
1312abb0b99SLinus Walleij        reg = <0xa0351000 0x1000>;
1322abb0b99SLinus Walleij        vana-supply = <&ab8500_ldo_ana_reg>;
1332abb0b99SLinus Walleij        clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1342abb0b99SLinus Walleij        clock-names = "hs", "lp";
1352abb0b99SLinus Walleij        #address-cells = <1>;
1362abb0b99SLinus Walleij        #size-cells = <0>;
1372abb0b99SLinus Walleij
1382abb0b99SLinus Walleij        panel@0 {
1392abb0b99SLinus Walleij          compatible = "samsung,s6d16d0";
1402abb0b99SLinus Walleij          reg = <0>;
1412abb0b99SLinus Walleij          vdd1-supply = <&ab8500_ldo_aux1_reg>;
1422abb0b99SLinus Walleij          reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
1432abb0b99SLinus Walleij        };
1442abb0b99SLinus Walleij      };
1452abb0b99SLinus Walleij
1462abb0b99SLinus Walleij      dsi1: dsi@a0352000 {
1472abb0b99SLinus Walleij        compatible = "ste,mcde-dsi";
1482abb0b99SLinus Walleij        reg = <0xa0352000 0x1000>;
1492abb0b99SLinus Walleij        vana-supply = <&ab8500_ldo_ana_reg>;
1502abb0b99SLinus Walleij        clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1512abb0b99SLinus Walleij        clock-names = "hs", "lp";
1522abb0b99SLinus Walleij        #address-cells = <1>;
1532abb0b99SLinus Walleij        #size-cells = <0>;
1542abb0b99SLinus Walleij      };
1552abb0b99SLinus Walleij
1562abb0b99SLinus Walleij      dsi2: dsi@a0353000 {
1572abb0b99SLinus Walleij        compatible = "ste,mcde-dsi";
1582abb0b99SLinus Walleij        reg = <0xa0353000 0x1000>;
1592abb0b99SLinus Walleij        vana-supply = <&ab8500_ldo_ana_reg>;
1602abb0b99SLinus Walleij        /* This DSI port only has the Low Power / Energy Save clock */
1612abb0b99SLinus Walleij        clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1622abb0b99SLinus Walleij        clock-names = "lp";
1632abb0b99SLinus Walleij        #address-cells = <1>;
1642abb0b99SLinus Walleij        #size-cells = <0>;
1652abb0b99SLinus Walleij      };
1662abb0b99SLinus Walleij    };
1672abb0b99SLinus Walleij
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