| /openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
7 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
17 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p…
23 "BriefDescription": "DRAM Activate Count : All Activates",
27 …DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this cha…
32 "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
36 …DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on…
41 "BriefDescription": "All DRAM CAS commands issued",
45 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | Kconfig | 4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
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| H A D | dram_sun4i.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * sunxi DRAM controller initialization
7 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
8 * and earlier U-Boot Allwinner A10 SPL work
10 * (C) Copyright 2007-2012
17 * Unfortunately the only documentation we have on the sun7i DRAM
18 * controller is Allwinner boot0 + boot1 code, and that code uses
26 #include <asm/arch/dram.h>
54 * This performs the external DRAM reset by driving the RESET pin low and
60 struct sunxi_dram_reg *dram = in mctl_ddr3_reset() local
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| /openbmc/linux/Documentation/devicetree/bindings/arm/sunxi/ |
| H A D | allwinner,sun4i-a10-mbus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner Memory Bus (MBUS) controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The MBUS controller drives the MBUS that other devices in the SoC
20 the interconnects and interconnect-names properties set to the MBUS
21 controller and with "dma-mem" as the interconnect name.
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| /openbmc/linux/drivers/memory/tegra/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "NVIDIA Tegra Memory Controller support"
8 This driver supports the Memory Controller (MC) hardware found on
14 tristate "NVIDIA Tegra20 External Memory Controller driver"
21 This driver is for the External Memory Controller (EMC) found on
22 Tegra20 chips. The EMC controls the external DRAM on the board.
27 tristate "NVIDIA Tegra30 External Memory Controller driver"
33 This driver is for the External Memory Controller (EMC) found on
34 Tegra30 chips. The EMC controls the external DRAM on the board.
39 tristate "NVIDIA Tegra124 External Memory Controller driver"
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | uncore-memory.json | 3 "BriefDescription": "DRAM Activate Count : All Activates",
7 …DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this cha…
12 "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
16 …DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on…
21 "BriefDescription": "All DRAM CAS commands issued",
25 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
30 "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
34 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
39 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
43 …ption": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_C…
[all …]
|
| H A D | other.json | 3 … where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
6 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX…
14 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct…
22 … running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). …
92 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
94 "EventName": "OCR.DEMAND_CODE_RD.DRAM",
101 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S…
110 …e prefetches that were supplied by DRAM on a distant memory controller of this socket when the sys…
128 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
130 "EventName": "OCR.DEMAND_DATA_RD.DRAM",
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | uncore-memory.json | 3 "BriefDescription": "DRAM Activate Count",
7 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued…
11 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
19 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
27 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
35 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
43 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
51 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read…
59 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Writ…
70 "PublicDescription": "Uncore Fixed Counter - uclks",
[all …]
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| /openbmc/linux/drivers/edac/ |
| H A D | i3000_edac.c | 2 * Intel 3000/3010 Memory Controller kernel module
5 * Intel D82875P Memory Controller kernel module
25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
31 #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
36 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
54 deap |= (edeap & 1) << (32 - PAGE_SHIFT); in deap_pfn()
60 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK; in deap_offset()
68 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
70 * 7:0 DRAM ECC Syndrome
79 * 9 LOCK to non-DRAM Memory Flag (LCKF)
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|
| H A D | ie31200_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel E3-1200
6 * Support for the E3-1200 processor family. Heavily based on previous
9 * Since the DRAM controller is on the cpu chip, we can use its PCI device
12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
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|
| H A D | altera_edac.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
10 #include <linux/arm-smccc.h>
14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
[all …]
|
| H A D | amd64_edac.h | 2 * AMD64 class Memory Controller kernel module
5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
57 * is within a range affected by memory hoisting. The DRAM Base
58 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
61 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
77 * memory controller for the node that the DramAddr is associated
78 * with. The memory controller then maps the InputAddr to a csrow.
84 * The memory controller for a given node uses its DRAM CS Base and
85 * DRAM CS Mask registers to map an InputAddr to a csrow. See
105 * PCI-defined configuration space registers
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|
| H A D | i82975x_edac.c | 2 * Intel 82975X Memory Controller kernel module
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
37 * 31:7 128 byte cache-line address
42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
44 * 7:0 DRAM ECC Syndrome
47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
50 * More - See Page 65 of Intel DocSheet.
58 * 9 non-DRAM lock error (ndlock)
61 * 1 ECC UE (multibit DRAM error)
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|
| H A D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
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|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | other.json | 26 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
28 "EventName": "OCR.DEMAND_CODE_RD.DRAM",
35 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S…
44 …e prefetches that were supplied by DRAM on a distant memory controller of this socket when the sys…
62 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
64 "EventName": "OCR.DEMAND_DATA_RD.DRAM",
71 …ds that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S…
98 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke…
116 …d data reads that were supplied by DRAM on a distant memory controller of this socket when the sys…
134 … requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
[all …]
|
| H A D | uncore-memory.json | 3 "BriefDescription": "Cycles - at UCLK",
186 "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
195 "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
204 "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
213 "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
286 "BriefDescription": "Multi-socket cacheline Directory update from A to I",
294 "BriefDescription": "Multi-socket cacheline Directory update from A to S",
302 "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
310 "BriefDescription": "Multi-socket cacheline Directory Updates",
321 "BriefDescription": "Multi-socket cacheline Directory Updates",
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| /openbmc/linux/drivers/usb/host/ |
| H A D | ehci-orion.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/usb/host/ehci-orion.c
13 #include <linux/platform_data/usb-ehci-orion.h>
19 #include <linux/dma-mapping.h>
23 #define rdl(off) readl_relaxed(hcd->regs + (off))
24 #define wrl(off, val) writel_relaxed((val), hcd->regs + (off))
59 #define hcd_to_orion_priv(h) ((struct orion_ehci_hcd *)hcd_to_ehci(h)->priv)
69 * Implement Orion USB controller specification guidelines
81 * Reset controller in orion_usb_phy_v1_setup()
87 * GL# USB-10: Set IPG for non start of frame packets in orion_usb_phy_v1_setup()
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
18 The individual DRAM chips on a memory stick. These devices commonly
20 provides the number of bits that the memory controller expects:
37 A memory controller channel, responsible to communicate with a group of
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
44 controller. Typically, it contains two channels. Two channels at the
52 * Single-channel
54 The data accessed by the memory controller is contained into one dimm
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
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| /openbmc/u-boot/board/xes/xpedite537x/ |
| H A D | ddr.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 * There are four board-specific SDRAM timing parameters which must be
23 * - TIMING_CFG_2 register
25 * chip-specific internal delays.
27 * - TIMING_CFG_2 register
33 * - DDR_SDRAM_CLK_CNTL register
36 * - TIMING_CFG_2 register
38 * Usually only needed with heavy load/very high speed (>DDR2-800)
40 * ====== XPedite5370 DDR2-600 read delay calculations ======
43 * contains the chip-specific delays for 8548E, 8572, etc.
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| /openbmc/linux/drivers/memory/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 bool "Samsung Exynos Memory Controller support" if COMPILE_TEST
5 Support for the Memory Controller (MC) devices found on
11 tristate "Exynos5422 Dynamic Memory Controller driver"
18 Controller). The driver provides support for Dynamic Voltage and
19 Frequency Scaling in DMC and DRAM. It also supports changing timings
20 of DRAM running with different frequency. The timings are calculated
25 bool "Exynos SROM controller driver" if COMPILE_TEST
28 This adds driver for Samsung Exynos SoC SROM controller. The driver
|
| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | cortina,gemini-pinctrl.txt | 1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
5 controller.
7 The pin controller node must be a subnode of the system controller node.
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
19 - skew-delay is supported on the Ethernet pins
20 - drive-strength with 4, 8, 12 or 16 mA as argument is supported for
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | uncore-memory.json | 3 "BriefDescription": "DRAM Activate Count; Activate due to Write",
7 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued…
12 "BriefDescription": "DRAM Activate Count; Activate due to Read",
16 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued…
21 "BriefDescription": "DRAM Activate Count; Activate due to Write",
25 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued…
54 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
58 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command…
63 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
67 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | amlogic,meson-gx-mmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/amlogic,meson-gx-mmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic SD / eMMC controller for S905/GXBB family SoCs
10 The MMC 5.1 compliant host controller on Amlogic provides the
14 - Neil Armstrong <neil.armstrong@linaro.org>
17 - $ref: mmc-controller.yaml#
22 - const: amlogic,meson-axg-mmc
23 - items:
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
7 …DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on D…
13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
17 …DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM,…
23 "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
27 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued…
32 "BriefDescription": "DRAM Activate Count; Activate due to Read",
36 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued…
41 "BriefDescription": "DRAM Page Activate commands sent due to a write request",
45 …DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Control…
[all …]
|