109c434b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
27ee40b89SJason Baron /*
37ee40b89SJason Baron * Intel E3-1200
47ee40b89SJason Baron * Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
57ee40b89SJason Baron *
67ee40b89SJason Baron * Support for the E3-1200 processor family. Heavily based on previous
77ee40b89SJason Baron * Intel EDAC drivers.
87ee40b89SJason Baron *
97ee40b89SJason Baron * Since the DRAM controller is on the cpu chip, we can use its PCI device
107ee40b89SJason Baron * id to identify these processors.
117ee40b89SJason Baron *
127d4c1ea2SAlexander A. Klimov * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
137ee40b89SJason Baron *
147ee40b89SJason Baron * 0108: Xeon E3-1200 Processor Family DRAM Controller
157ee40b89SJason Baron * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
167ee40b89SJason Baron * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
177ee40b89SJason Baron * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
187ee40b89SJason Baron * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
197ee40b89SJason Baron * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
207ee40b89SJason Baron * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
21953dee9bSJason Baron * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
227103de0eSJason Baron * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
23*7a14a11fSJosh Hant * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
24*7a14a11fSJosh Hant * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
25c452a9d3SMarco Elver * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
267ee40b89SJason Baron *
277ee40b89SJason Baron * Based on Intel specification:
287d4c1ea2SAlexander A. Klimov * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
297ee40b89SJason Baron * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
30*7a14a11fSJosh Hant * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf
31*7a14a11fSJosh Hant * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf
327d4c1ea2SAlexander A. Klimov * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
33c452a9d3SMarco Elver * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
347ee40b89SJason Baron *
357ee40b89SJason Baron * According to the above datasheet (p.16):
367ee40b89SJason Baron * "
377ee40b89SJason Baron * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
387ee40b89SJason Baron * requests that cross a DW boundary.
397ee40b89SJason Baron * "
407ee40b89SJason Baron *
417ee40b89SJason Baron * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
427ee40b89SJason Baron * 2 readl() calls. This restriction may be lifted in subsequent chip releases,
437ee40b89SJason Baron * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
447ee40b89SJason Baron */
457ee40b89SJason Baron
467ee40b89SJason Baron #include <linux/module.h>
477ee40b89SJason Baron #include <linux/init.h>
487ee40b89SJason Baron #include <linux/pci.h>
497ee40b89SJason Baron #include <linux/pci_ids.h>
507ee40b89SJason Baron #include <linux/edac.h>
517ee40b89SJason Baron
522f8e2c87SChristoph Hellwig #include <linux/io-64-nonatomic-lo-hi.h>
5378d88e8aSMauro Carvalho Chehab #include "edac_module.h"
547ee40b89SJason Baron
557ee40b89SJason Baron #define EDAC_MOD_STR "ie31200_edac"
567ee40b89SJason Baron
577ee40b89SJason Baron #define ie31200_printk(level, fmt, arg...) \
587ee40b89SJason Baron edac_printk(level, "ie31200", fmt, ##arg)
597ee40b89SJason Baron
607ee40b89SJason Baron #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
617ee40b89SJason Baron #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
627ee40b89SJason Baron #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
637ee40b89SJason Baron #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
647ee40b89SJason Baron #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
657ee40b89SJason Baron #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
667ee40b89SJason Baron #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
67*7a14a11fSJosh Hant #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
68*7a14a11fSJosh Hant #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
69*7a14a11fSJosh Hant #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
70*7a14a11fSJosh Hant #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
717ee40b89SJason Baron
72c452a9d3SMarco Elver /* Coffee Lake-S */
73c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
74c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f
75c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18
76c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f
77c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30
78c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31
79c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32
80c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33
81c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2
82c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6
83c452a9d3SMarco Elver #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca
84c452a9d3SMarco Elver
85c452a9d3SMarco Elver /* Test if HB is for Skylake or later. */
86c452a9d3SMarco Elver #define DEVICE_ID_SKYLAKE_OR_LATER(did) \
87c452a9d3SMarco Elver (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
88c452a9d3SMarco Elver ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
89*7a14a11fSJosh Hant ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
90*7a14a11fSJosh Hant ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \
91c452a9d3SMarco Elver (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
92c452a9d3SMarco Elver PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
93c452a9d3SMarco Elver
947ee40b89SJason Baron #define IE31200_DIMMS 4
957ee40b89SJason Baron #define IE31200_RANKS 8
967ee40b89SJason Baron #define IE31200_RANKS_PER_CHANNEL 4
977ee40b89SJason Baron #define IE31200_DIMMS_PER_CHANNEL 2
987ee40b89SJason Baron #define IE31200_CHANNELS 2
997ee40b89SJason Baron
1007ee40b89SJason Baron /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
1017ee40b89SJason Baron #define IE31200_MCHBAR_LOW 0x48
1027ee40b89SJason Baron #define IE31200_MCHBAR_HIGH 0x4c
1037ee40b89SJason Baron #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15)
1047ee40b89SJason Baron #define IE31200_MMR_WINDOW_SIZE BIT(15)
1057ee40b89SJason Baron
1067ee40b89SJason Baron /*
1077ee40b89SJason Baron * Error Status Register (16b)
1087ee40b89SJason Baron *
1097ee40b89SJason Baron * 15 reserved
1107ee40b89SJason Baron * 14 Isochronous TBWRR Run Behind FIFO Full
1117ee40b89SJason Baron * (ITCV)
1127ee40b89SJason Baron * 13 Isochronous TBWRR Run Behind FIFO Put
1137ee40b89SJason Baron * (ITSTV)
1147ee40b89SJason Baron * 12 reserved
1157ee40b89SJason Baron * 11 MCH Thermal Sensor Event
1167ee40b89SJason Baron * for SMI/SCI/SERR (GTSE)
1177ee40b89SJason Baron * 10 reserved
1187ee40b89SJason Baron * 9 LOCK to non-DRAM Memory Flag (LCKF)
1197ee40b89SJason Baron * 8 reserved
1207ee40b89SJason Baron * 7 DRAM Throttle Flag (DTF)
1217ee40b89SJason Baron * 6:2 reserved
1227ee40b89SJason Baron * 1 Multi-bit DRAM ECC Error Flag (DMERR)
1237ee40b89SJason Baron * 0 Single-bit DRAM ECC Error Flag (DSERR)
1247ee40b89SJason Baron */
1257ee40b89SJason Baron #define IE31200_ERRSTS 0xc8
1267ee40b89SJason Baron #define IE31200_ERRSTS_UE BIT(1)
1277ee40b89SJason Baron #define IE31200_ERRSTS_CE BIT(0)
1287ee40b89SJason Baron #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
1297ee40b89SJason Baron
1307ee40b89SJason Baron /*
1317ee40b89SJason Baron * Channel 0 ECC Error Log (64b)
1327ee40b89SJason Baron *
1337ee40b89SJason Baron * 63:48 Error Column Address (ERRCOL)
1347ee40b89SJason Baron * 47:32 Error Row Address (ERRROW)
1357ee40b89SJason Baron * 31:29 Error Bank Address (ERRBANK)
1367ee40b89SJason Baron * 28:27 Error Rank Address (ERRRANK)
1377ee40b89SJason Baron * 26:24 reserved
1387ee40b89SJason Baron * 23:16 Error Syndrome (ERRSYND)
1397ee40b89SJason Baron * 15: 2 reserved
1407ee40b89SJason Baron * 1 Multiple Bit Error Status (MERRSTS)
1417ee40b89SJason Baron * 0 Correctable Error Status (CERRSTS)
1427ee40b89SJason Baron */
143953dee9bSJason Baron
1447ee40b89SJason Baron #define IE31200_C0ECCERRLOG 0x40c8
1457ee40b89SJason Baron #define IE31200_C1ECCERRLOG 0x44c8
146953dee9bSJason Baron #define IE31200_C0ECCERRLOG_SKL 0x4048
147953dee9bSJason Baron #define IE31200_C1ECCERRLOG_SKL 0x4448
1487ee40b89SJason Baron #define IE31200_ECCERRLOG_CE BIT(0)
1497ee40b89SJason Baron #define IE31200_ECCERRLOG_UE BIT(1)
1507ee40b89SJason Baron #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
1517ee40b89SJason Baron #define IE31200_ECCERRLOG_RANK_SHIFT 27
1527ee40b89SJason Baron #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16)
1537ee40b89SJason Baron #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16
1547ee40b89SJason Baron
1557ee40b89SJason Baron #define IE31200_ECCERRLOG_SYNDROME(log) \
1567ee40b89SJason Baron ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
1577ee40b89SJason Baron IE31200_ECCERRLOG_SYNDROME_SHIFT)
1587ee40b89SJason Baron
1597ee40b89SJason Baron #define IE31200_CAPID0 0xe4
1607ee40b89SJason Baron #define IE31200_CAPID0_PDCD BIT(4)
1617ee40b89SJason Baron #define IE31200_CAPID0_DDPCD BIT(6)
1627ee40b89SJason Baron #define IE31200_CAPID0_ECC BIT(1)
1637ee40b89SJason Baron
1647ee40b89SJason Baron #define IE31200_MAD_DIMM_0_OFFSET 0x5004
165953dee9bSJason Baron #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C
1667ee40b89SJason Baron #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
1677ee40b89SJason Baron #define IE31200_MAD_DIMM_A_RANK BIT(17)
168953dee9bSJason Baron #define IE31200_MAD_DIMM_A_RANK_SHIFT 17
169953dee9bSJason Baron #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10)
170953dee9bSJason Baron #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10
1717ee40b89SJason Baron #define IE31200_MAD_DIMM_A_WIDTH BIT(19)
172953dee9bSJason Baron #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19
173953dee9bSJason Baron #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8)
174953dee9bSJason Baron #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8
1757ee40b89SJason Baron
176953dee9bSJason Baron /* Skylake reports 1GB increments, everything else is 256MB */
177953dee9bSJason Baron #define IE31200_PAGES(n, skl) \
178953dee9bSJason Baron (n << (28 + (2 * skl) - PAGE_SHIFT))
1797ee40b89SJason Baron
1807ee40b89SJason Baron static int nr_channels;
181709ed1bcSJason Baron static struct pci_dev *mci_pdev;
182709ed1bcSJason Baron static int ie31200_registered = 1;
1837ee40b89SJason Baron
1847ee40b89SJason Baron struct ie31200_priv {
1857ee40b89SJason Baron void __iomem *window;
186953dee9bSJason Baron void __iomem *c0errlog;
187953dee9bSJason Baron void __iomem *c1errlog;
1887ee40b89SJason Baron };
1897ee40b89SJason Baron
1907ee40b89SJason Baron enum ie31200_chips {
1917ee40b89SJason Baron IE31200 = 0,
1927ee40b89SJason Baron };
1937ee40b89SJason Baron
1947ee40b89SJason Baron struct ie31200_dev_info {
1957ee40b89SJason Baron const char *ctl_name;
1967ee40b89SJason Baron };
1977ee40b89SJason Baron
1987ee40b89SJason Baron struct ie31200_error_info {
1997ee40b89SJason Baron u16 errsts;
2007ee40b89SJason Baron u16 errsts2;
2017ee40b89SJason Baron u64 eccerrlog[IE31200_CHANNELS];
2027ee40b89SJason Baron };
2037ee40b89SJason Baron
2047ee40b89SJason Baron static const struct ie31200_dev_info ie31200_devs[] = {
2057ee40b89SJason Baron [IE31200] = {
2067ee40b89SJason Baron .ctl_name = "IE31200"
2077ee40b89SJason Baron },
2087ee40b89SJason Baron };
2097ee40b89SJason Baron
2107ee40b89SJason Baron struct dimm_data {
211953dee9bSJason Baron u8 size; /* in multiples of 256MB, except Skylake is 1GB */
2127ee40b89SJason Baron u8 dual_rank : 1,
213953dee9bSJason Baron x16_width : 2; /* 0 means x8 width */
2147ee40b89SJason Baron };
2157ee40b89SJason Baron
how_many_channels(struct pci_dev * pdev)2167ee40b89SJason Baron static int how_many_channels(struct pci_dev *pdev)
2177ee40b89SJason Baron {
2187ee40b89SJason Baron int n_channels;
2197ee40b89SJason Baron unsigned char capid0_2b; /* 2nd byte of CAPID0 */
2207ee40b89SJason Baron
2217ee40b89SJason Baron pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
2227ee40b89SJason Baron
2237ee40b89SJason Baron /* check PDCD: Dual Channel Disable */
2247ee40b89SJason Baron if (capid0_2b & IE31200_CAPID0_PDCD) {
2257ee40b89SJason Baron edac_dbg(0, "In single channel mode\n");
2267ee40b89SJason Baron n_channels = 1;
2277ee40b89SJason Baron } else {
2287ee40b89SJason Baron edac_dbg(0, "In dual channel mode\n");
2297ee40b89SJason Baron n_channels = 2;
2307ee40b89SJason Baron }
2317ee40b89SJason Baron
2327ee40b89SJason Baron /* check DDPCD - check if both channels are filled */
2337ee40b89SJason Baron if (capid0_2b & IE31200_CAPID0_DDPCD)
2347ee40b89SJason Baron edac_dbg(0, "2 DIMMS per channel disabled\n");
2357ee40b89SJason Baron else
2367ee40b89SJason Baron edac_dbg(0, "2 DIMMS per channel enabled\n");
2377ee40b89SJason Baron
2387ee40b89SJason Baron return n_channels;
2397ee40b89SJason Baron }
2407ee40b89SJason Baron
ecc_capable(struct pci_dev * pdev)2417ee40b89SJason Baron static bool ecc_capable(struct pci_dev *pdev)
2427ee40b89SJason Baron {
2437ee40b89SJason Baron unsigned char capid0_4b; /* 4th byte of CAPID0 */
2447ee40b89SJason Baron
2457ee40b89SJason Baron pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
2467ee40b89SJason Baron if (capid0_4b & IE31200_CAPID0_ECC)
2477ee40b89SJason Baron return false;
2487ee40b89SJason Baron return true;
2497ee40b89SJason Baron }
2507ee40b89SJason Baron
eccerrlog_row(u64 log)251953dee9bSJason Baron static int eccerrlog_row(u64 log)
2527ee40b89SJason Baron {
253953dee9bSJason Baron return ((log & IE31200_ECCERRLOG_RANK_BITS) >>
2547ee40b89SJason Baron IE31200_ECCERRLOG_RANK_SHIFT);
2557ee40b89SJason Baron }
2567ee40b89SJason Baron
ie31200_clear_error_info(struct mem_ctl_info * mci)2577ee40b89SJason Baron static void ie31200_clear_error_info(struct mem_ctl_info *mci)
2587ee40b89SJason Baron {
2597ee40b89SJason Baron /*
2607ee40b89SJason Baron * Clear any error bits.
2617ee40b89SJason Baron * (Yes, we really clear bits by writing 1 to them.)
2627ee40b89SJason Baron */
2637ee40b89SJason Baron pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
2647ee40b89SJason Baron IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
2657ee40b89SJason Baron }
2667ee40b89SJason Baron
ie31200_get_and_clear_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)2677ee40b89SJason Baron static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
2687ee40b89SJason Baron struct ie31200_error_info *info)
2697ee40b89SJason Baron {
2707ee40b89SJason Baron struct pci_dev *pdev;
2717ee40b89SJason Baron struct ie31200_priv *priv = mci->pvt_info;
2727ee40b89SJason Baron
2737ee40b89SJason Baron pdev = to_pci_dev(mci->pdev);
2747ee40b89SJason Baron
2757ee40b89SJason Baron /*
2767ee40b89SJason Baron * This is a mess because there is no atomic way to read all the
2777ee40b89SJason Baron * registers at once and the registers can transition from CE being
2787ee40b89SJason Baron * overwritten by UE.
2797ee40b89SJason Baron */
2807ee40b89SJason Baron pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
2817ee40b89SJason Baron if (!(info->errsts & IE31200_ERRSTS_BITS))
2827ee40b89SJason Baron return;
2837ee40b89SJason Baron
284953dee9bSJason Baron info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
2857ee40b89SJason Baron if (nr_channels == 2)
286953dee9bSJason Baron info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
2877ee40b89SJason Baron
2887ee40b89SJason Baron pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
2897ee40b89SJason Baron
2907ee40b89SJason Baron /*
2917ee40b89SJason Baron * If the error is the same for both reads then the first set
2927ee40b89SJason Baron * of reads is valid. If there is a change then there is a CE
2937ee40b89SJason Baron * with no info and the second set of reads is valid and
2947ee40b89SJason Baron * should be UE info.
2957ee40b89SJason Baron */
2967ee40b89SJason Baron if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
297953dee9bSJason Baron info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
2987ee40b89SJason Baron if (nr_channels == 2)
2997ee40b89SJason Baron info->eccerrlog[1] =
300953dee9bSJason Baron lo_hi_readq(priv->c1errlog);
3017ee40b89SJason Baron }
3027ee40b89SJason Baron
3037ee40b89SJason Baron ie31200_clear_error_info(mci);
3047ee40b89SJason Baron }
3057ee40b89SJason Baron
ie31200_process_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)3067ee40b89SJason Baron static void ie31200_process_error_info(struct mem_ctl_info *mci,
3077ee40b89SJason Baron struct ie31200_error_info *info)
3087ee40b89SJason Baron {
3097ee40b89SJason Baron int channel;
3107ee40b89SJason Baron u64 log;
3117ee40b89SJason Baron
3127ee40b89SJason Baron if (!(info->errsts & IE31200_ERRSTS_BITS))
3137ee40b89SJason Baron return;
3147ee40b89SJason Baron
3157ee40b89SJason Baron if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
3167ee40b89SJason Baron edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
3177ee40b89SJason Baron -1, -1, -1, "UE overwrote CE", "");
3187ee40b89SJason Baron info->errsts = info->errsts2;
3197ee40b89SJason Baron }
3207ee40b89SJason Baron
3217ee40b89SJason Baron for (channel = 0; channel < nr_channels; channel++) {
3227ee40b89SJason Baron log = info->eccerrlog[channel];
3237ee40b89SJason Baron if (log & IE31200_ECCERRLOG_UE) {
3247ee40b89SJason Baron edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
3257ee40b89SJason Baron 0, 0, 0,
326953dee9bSJason Baron eccerrlog_row(log),
3277ee40b89SJason Baron channel, -1,
3287ee40b89SJason Baron "ie31200 UE", "");
3297ee40b89SJason Baron } else if (log & IE31200_ECCERRLOG_CE) {
3307ee40b89SJason Baron edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
3317ee40b89SJason Baron 0, 0,
3327ee40b89SJason Baron IE31200_ECCERRLOG_SYNDROME(log),
333953dee9bSJason Baron eccerrlog_row(log),
3347ee40b89SJason Baron channel, -1,
3357ee40b89SJason Baron "ie31200 CE", "");
3367ee40b89SJason Baron }
3377ee40b89SJason Baron }
3387ee40b89SJason Baron }
3397ee40b89SJason Baron
ie31200_check(struct mem_ctl_info * mci)3407ee40b89SJason Baron static void ie31200_check(struct mem_ctl_info *mci)
3417ee40b89SJason Baron {
3427ee40b89SJason Baron struct ie31200_error_info info;
3437ee40b89SJason Baron
3447ee40b89SJason Baron ie31200_get_and_clear_error_info(mci, &info);
3457ee40b89SJason Baron ie31200_process_error_info(mci, &info);
3467ee40b89SJason Baron }
3477ee40b89SJason Baron
ie31200_map_mchbar(struct pci_dev * pdev)3487ee40b89SJason Baron static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
3497ee40b89SJason Baron {
3507ee40b89SJason Baron union {
3517ee40b89SJason Baron u64 mchbar;
3527ee40b89SJason Baron struct {
3537ee40b89SJason Baron u32 mchbar_low;
3547ee40b89SJason Baron u32 mchbar_high;
3557ee40b89SJason Baron };
3567ee40b89SJason Baron } u;
3577ee40b89SJason Baron void __iomem *window;
3587ee40b89SJason Baron
3597ee40b89SJason Baron pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
3607ee40b89SJason Baron pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
3617ee40b89SJason Baron u.mchbar &= IE31200_MCHBAR_MASK;
3627ee40b89SJason Baron
3637ee40b89SJason Baron if (u.mchbar != (resource_size_t)u.mchbar) {
3647ee40b89SJason Baron ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
3657ee40b89SJason Baron (unsigned long long)u.mchbar);
3667ee40b89SJason Baron return NULL;
3677ee40b89SJason Baron }
3687ee40b89SJason Baron
3694bdc0d67SChristoph Hellwig window = ioremap(u.mchbar, IE31200_MMR_WINDOW_SIZE);
3707ee40b89SJason Baron if (!window)
3717ee40b89SJason Baron ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
3727ee40b89SJason Baron (unsigned long long)u.mchbar);
3737ee40b89SJason Baron
3747ee40b89SJason Baron return window;
3757ee40b89SJason Baron }
3767ee40b89SJason Baron
__skl_populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan)377953dee9bSJason Baron static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
378953dee9bSJason Baron int chan)
379953dee9bSJason Baron {
380953dee9bSJason Baron dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE;
381953dee9bSJason Baron dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;
382953dee9bSJason Baron dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>
383953dee9bSJason Baron (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4)));
384953dee9bSJason Baron }
385953dee9bSJason Baron
__populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan)386953dee9bSJason Baron static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
387953dee9bSJason Baron int chan)
388953dee9bSJason Baron {
389953dee9bSJason Baron dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;
390953dee9bSJason Baron dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;
391953dee9bSJason Baron dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;
392953dee9bSJason Baron }
393953dee9bSJason Baron
populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan,bool skl)394953dee9bSJason Baron static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan,
395953dee9bSJason Baron bool skl)
396953dee9bSJason Baron {
397953dee9bSJason Baron if (skl)
398953dee9bSJason Baron __skl_populate_dimm_info(dd, addr_decode, chan);
399953dee9bSJason Baron else
400953dee9bSJason Baron __populate_dimm_info(dd, addr_decode, chan);
401953dee9bSJason Baron }
402953dee9bSJason Baron
403953dee9bSJason Baron
ie31200_probe1(struct pci_dev * pdev,int dev_idx)4047ee40b89SJason Baron static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
4057ee40b89SJason Baron {
40678fd4d12SJason Baron int i, j, ret;
4077ee40b89SJason Baron struct mem_ctl_info *mci = NULL;
4087ee40b89SJason Baron struct edac_mc_layer layers[2];
4097ee40b89SJason Baron struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
4107ee40b89SJason Baron void __iomem *window;
4117ee40b89SJason Baron struct ie31200_priv *priv;
412953dee9bSJason Baron u32 addr_decode, mad_offset;
4137103de0eSJason Baron
4147103de0eSJason Baron /*
415c452a9d3SMarco Elver * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit
416c452a9d3SMarco Elver * this logic when adding new CPU support.
4177103de0eSJason Baron */
418c452a9d3SMarco Elver bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device);
4197ee40b89SJason Baron
4207ee40b89SJason Baron edac_dbg(0, "MC:\n");
4217ee40b89SJason Baron
4227ee40b89SJason Baron if (!ecc_capable(pdev)) {
4237ee40b89SJason Baron ie31200_printk(KERN_INFO, "No ECC support\n");
4247ee40b89SJason Baron return -ENODEV;
4257ee40b89SJason Baron }
4267ee40b89SJason Baron
42778fd4d12SJason Baron nr_channels = how_many_channels(pdev);
42878fd4d12SJason Baron layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
42978fd4d12SJason Baron layers[0].size = IE31200_DIMMS;
43078fd4d12SJason Baron layers[0].is_virt_csrow = true;
43178fd4d12SJason Baron layers[1].type = EDAC_MC_LAYER_CHANNEL;
43278fd4d12SJason Baron layers[1].size = nr_channels;
43378fd4d12SJason Baron layers[1].is_virt_csrow = false;
43478fd4d12SJason Baron mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
43578fd4d12SJason Baron sizeof(struct ie31200_priv));
43678fd4d12SJason Baron if (!mci)
43778fd4d12SJason Baron return -ENOMEM;
43878fd4d12SJason Baron
4397ee40b89SJason Baron window = ie31200_map_mchbar(pdev);
44078fd4d12SJason Baron if (!window) {
44178fd4d12SJason Baron ret = -ENODEV;
44278fd4d12SJason Baron goto fail_free;
44378fd4d12SJason Baron }
44478fd4d12SJason Baron
44578fd4d12SJason Baron edac_dbg(3, "MC: init mci\n");
44678fd4d12SJason Baron mci->pdev = &pdev->dev;
447953dee9bSJason Baron if (skl)
448953dee9bSJason Baron mci->mtype_cap = MEM_FLAG_DDR4;
449953dee9bSJason Baron else
45078fd4d12SJason Baron mci->mtype_cap = MEM_FLAG_DDR3;
45178fd4d12SJason Baron mci->edac_ctl_cap = EDAC_FLAG_SECDED;
45278fd4d12SJason Baron mci->edac_cap = EDAC_FLAG_SECDED;
45378fd4d12SJason Baron mci->mod_name = EDAC_MOD_STR;
45478fd4d12SJason Baron mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
45578fd4d12SJason Baron mci->dev_name = pci_name(pdev);
45678fd4d12SJason Baron mci->edac_check = ie31200_check;
45778fd4d12SJason Baron mci->ctl_page_to_phys = NULL;
45878fd4d12SJason Baron priv = mci->pvt_info;
45978fd4d12SJason Baron priv->window = window;
460953dee9bSJason Baron if (skl) {
461953dee9bSJason Baron priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL;
462953dee9bSJason Baron priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL;
463953dee9bSJason Baron mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL;
464953dee9bSJason Baron } else {
465953dee9bSJason Baron priv->c0errlog = window + IE31200_C0ECCERRLOG;
466953dee9bSJason Baron priv->c1errlog = window + IE31200_C1ECCERRLOG;
467953dee9bSJason Baron mad_offset = IE31200_MAD_DIMM_0_OFFSET;
468953dee9bSJason Baron }
4697ee40b89SJason Baron
4707ee40b89SJason Baron /* populate DIMM info */
4717ee40b89SJason Baron for (i = 0; i < IE31200_CHANNELS; i++) {
472953dee9bSJason Baron addr_decode = readl(window + mad_offset +
4737ee40b89SJason Baron (i * 4));
4747ee40b89SJason Baron edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
4757ee40b89SJason Baron for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
476953dee9bSJason Baron populate_dimm_info(&dimm_info[i][j], addr_decode, j,
477953dee9bSJason Baron skl);
4787ee40b89SJason Baron edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
4797ee40b89SJason Baron dimm_info[i][j].size,
4807ee40b89SJason Baron dimm_info[i][j].dual_rank,
4817ee40b89SJason Baron dimm_info[i][j].x16_width);
4827ee40b89SJason Baron }
4837ee40b89SJason Baron }
4847ee40b89SJason Baron
4857ee40b89SJason Baron /*
4867ee40b89SJason Baron * The dram rank boundary (DRB) reg values are boundary addresses
4877ee40b89SJason Baron * for each DRAM rank with a granularity of 64MB. DRB regs are
4887ee40b89SJason Baron * cumulative; the last one will contain the total memory
4897ee40b89SJason Baron * contained in all ranks.
4907ee40b89SJason Baron */
4917ee40b89SJason Baron for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
4927ee40b89SJason Baron for (j = 0; j < IE31200_CHANNELS; j++) {
4937ee40b89SJason Baron struct dimm_info *dimm;
4947ee40b89SJason Baron unsigned long nr_pages;
4957ee40b89SJason Baron
496953dee9bSJason Baron nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl);
4977ee40b89SJason Baron if (nr_pages == 0)
4987ee40b89SJason Baron continue;
4997ee40b89SJason Baron
5007ee40b89SJason Baron if (dimm_info[j][i].dual_rank) {
5017ee40b89SJason Baron nr_pages = nr_pages / 2;
502bc9ad9e4SRobert Richter dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0);
5037ee40b89SJason Baron dimm->nr_pages = nr_pages;
5047ee40b89SJason Baron edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
5057ee40b89SJason Baron dimm->grain = 8; /* just a guess */
506953dee9bSJason Baron if (skl)
507953dee9bSJason Baron dimm->mtype = MEM_DDR4;
508953dee9bSJason Baron else
5097ee40b89SJason Baron dimm->mtype = MEM_DDR3;
5107ee40b89SJason Baron dimm->dtype = DEV_UNKNOWN;
5117ee40b89SJason Baron dimm->edac_mode = EDAC_UNKNOWN;
5127ee40b89SJason Baron }
513bc9ad9e4SRobert Richter dimm = edac_get_dimm(mci, i * 2, j, 0);
5147ee40b89SJason Baron dimm->nr_pages = nr_pages;
5157ee40b89SJason Baron edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
5167ee40b89SJason Baron dimm->grain = 8; /* same guess */
517953dee9bSJason Baron if (skl)
518953dee9bSJason Baron dimm->mtype = MEM_DDR4;
519953dee9bSJason Baron else
5207ee40b89SJason Baron dimm->mtype = MEM_DDR3;
5217ee40b89SJason Baron dimm->dtype = DEV_UNKNOWN;
5227ee40b89SJason Baron dimm->edac_mode = EDAC_UNKNOWN;
5237ee40b89SJason Baron }
5247ee40b89SJason Baron }
5257ee40b89SJason Baron
5267ee40b89SJason Baron ie31200_clear_error_info(mci);
5277ee40b89SJason Baron
5287ee40b89SJason Baron if (edac_mc_add_mc(mci)) {
5297ee40b89SJason Baron edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
53078fd4d12SJason Baron ret = -ENODEV;
53178fd4d12SJason Baron goto fail_unmap;
5327ee40b89SJason Baron }
5337ee40b89SJason Baron
5347ee40b89SJason Baron /* get this far and it's successful */
5357ee40b89SJason Baron edac_dbg(3, "MC: success\n");
5367ee40b89SJason Baron return 0;
5377ee40b89SJason Baron
5387ee40b89SJason Baron fail_unmap:
5397ee40b89SJason Baron iounmap(window);
5407ee40b89SJason Baron
54178fd4d12SJason Baron fail_free:
54278fd4d12SJason Baron edac_mc_free(mci);
54378fd4d12SJason Baron
54478fd4d12SJason Baron return ret;
5457ee40b89SJason Baron }
5467ee40b89SJason Baron
ie31200_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)5477ee40b89SJason Baron static int ie31200_init_one(struct pci_dev *pdev,
5487ee40b89SJason Baron const struct pci_device_id *ent)
5497ee40b89SJason Baron {
550709ed1bcSJason Baron int rc;
5517ee40b89SJason Baron
552709ed1bcSJason Baron edac_dbg(0, "MC:\n");
5537ee40b89SJason Baron if (pci_enable_device(pdev) < 0)
5547ee40b89SJason Baron return -EIO;
555709ed1bcSJason Baron rc = ie31200_probe1(pdev, ent->driver_data);
556709ed1bcSJason Baron if (rc == 0 && !mci_pdev)
557709ed1bcSJason Baron mci_pdev = pci_dev_get(pdev);
5587ee40b89SJason Baron
559709ed1bcSJason Baron return rc;
5607ee40b89SJason Baron }
5617ee40b89SJason Baron
ie31200_remove_one(struct pci_dev * pdev)5627ee40b89SJason Baron static void ie31200_remove_one(struct pci_dev *pdev)
5637ee40b89SJason Baron {
5647ee40b89SJason Baron struct mem_ctl_info *mci;
5657ee40b89SJason Baron struct ie31200_priv *priv;
5667ee40b89SJason Baron
5677ee40b89SJason Baron edac_dbg(0, "\n");
568709ed1bcSJason Baron pci_dev_put(mci_pdev);
569709ed1bcSJason Baron mci_pdev = NULL;
5707ee40b89SJason Baron mci = edac_mc_del_mc(&pdev->dev);
5717ee40b89SJason Baron if (!mci)
5727ee40b89SJason Baron return;
5737ee40b89SJason Baron priv = mci->pvt_info;
5747ee40b89SJason Baron iounmap(priv->window);
5757ee40b89SJason Baron edac_mc_free(mci);
5767ee40b89SJason Baron }
5777ee40b89SJason Baron
5787ee40b89SJason Baron static const struct pci_device_id ie31200_pci_tbl[] = {
5794d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5804d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5814d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5824d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5834d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5844d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5854d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5864d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5874d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
588*7a14a11fSJosh Hant { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
589*7a14a11fSJosh Hant { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5904d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5914d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5924d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5934d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5944d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5954d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5964d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5974d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5984d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
5994d91fde8SMarco Elver { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
6004d91fde8SMarco Elver { 0, } /* 0 terminated list. */
6017ee40b89SJason Baron };
6027ee40b89SJason Baron MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
6037ee40b89SJason Baron
6047ee40b89SJason Baron static struct pci_driver ie31200_driver = {
6057ee40b89SJason Baron .name = EDAC_MOD_STR,
6067ee40b89SJason Baron .probe = ie31200_init_one,
6077ee40b89SJason Baron .remove = ie31200_remove_one,
6087ee40b89SJason Baron .id_table = ie31200_pci_tbl,
6097ee40b89SJason Baron };
6107ee40b89SJason Baron
ie31200_init(void)6117ee40b89SJason Baron static int __init ie31200_init(void)
6127ee40b89SJason Baron {
613709ed1bcSJason Baron int pci_rc, i;
614709ed1bcSJason Baron
6157ee40b89SJason Baron edac_dbg(3, "MC:\n");
6167ee40b89SJason Baron /* Ensure that the OPSTATE is set correctly for POLL or NMI */
6177ee40b89SJason Baron opstate_init();
6187ee40b89SJason Baron
619709ed1bcSJason Baron pci_rc = pci_register_driver(&ie31200_driver);
620709ed1bcSJason Baron if (pci_rc < 0)
621709ed1bcSJason Baron goto fail0;
622709ed1bcSJason Baron
623709ed1bcSJason Baron if (!mci_pdev) {
624709ed1bcSJason Baron ie31200_registered = 0;
625709ed1bcSJason Baron for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {
626709ed1bcSJason Baron mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor,
627709ed1bcSJason Baron ie31200_pci_tbl[i].device,
628709ed1bcSJason Baron NULL);
629709ed1bcSJason Baron if (mci_pdev)
630709ed1bcSJason Baron break;
631709ed1bcSJason Baron }
632709ed1bcSJason Baron if (!mci_pdev) {
633709ed1bcSJason Baron edac_dbg(0, "ie31200 pci_get_device fail\n");
634709ed1bcSJason Baron pci_rc = -ENODEV;
635709ed1bcSJason Baron goto fail1;
636709ed1bcSJason Baron }
637709ed1bcSJason Baron pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]);
638709ed1bcSJason Baron if (pci_rc < 0) {
639709ed1bcSJason Baron edac_dbg(0, "ie31200 init fail\n");
640709ed1bcSJason Baron pci_rc = -ENODEV;
641709ed1bcSJason Baron goto fail1;
642709ed1bcSJason Baron }
643709ed1bcSJason Baron }
644709ed1bcSJason Baron return 0;
645709ed1bcSJason Baron
646709ed1bcSJason Baron fail1:
647709ed1bcSJason Baron pci_unregister_driver(&ie31200_driver);
648709ed1bcSJason Baron fail0:
649709ed1bcSJason Baron pci_dev_put(mci_pdev);
650709ed1bcSJason Baron
651709ed1bcSJason Baron return pci_rc;
6527ee40b89SJason Baron }
6537ee40b89SJason Baron
ie31200_exit(void)6547ee40b89SJason Baron static void __exit ie31200_exit(void)
6557ee40b89SJason Baron {
6567ee40b89SJason Baron edac_dbg(3, "MC:\n");
6577ee40b89SJason Baron pci_unregister_driver(&ie31200_driver);
658709ed1bcSJason Baron if (!ie31200_registered)
659709ed1bcSJason Baron ie31200_remove_one(mci_pdev);
6607ee40b89SJason Baron }
6617ee40b89SJason Baron
6627ee40b89SJason Baron module_init(ie31200_init);
6637ee40b89SJason Baron module_exit(ie31200_exit);
6647ee40b89SJason Baron
6657ee40b89SJason Baron MODULE_LICENSE("GPL");
6667ee40b89SJason Baron MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
6677ee40b89SJason Baron MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");
668