1cfe40fdbSDoug Thompson /*
2cfe40fdbSDoug Thompson * AMD64 class Memory Controller kernel module
3cfe40fdbSDoug Thompson *
4cfe40fdbSDoug Thompson * Copyright (c) 2009 SoftwareBitMaker.
51a8bc770SAravind Gopalakrishnan * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
6cfe40fdbSDoug Thompson *
7cfe40fdbSDoug Thompson * This file may be distributed under the terms of the
8cfe40fdbSDoug Thompson * GNU General Public License.
9cfe40fdbSDoug Thompson */
10cfe40fdbSDoug Thompson
11cfe40fdbSDoug Thompson #include <linux/module.h>
12cfe40fdbSDoug Thompson #include <linux/ctype.h>
13cfe40fdbSDoug Thompson #include <linux/init.h>
14cfe40fdbSDoug Thompson #include <linux/pci.h>
15cfe40fdbSDoug Thompson #include <linux/pci_ids.h>
16cfe40fdbSDoug Thompson #include <linux/slab.h>
17cfe40fdbSDoug Thompson #include <linux/mmzone.h>
18cfe40fdbSDoug Thompson #include <linux/edac.h>
19*4251566eSYazen Ghannam #include <linux/bitfield.h>
201bd9900bSYazen Ghannam #include <asm/cpu_device_id.h>
21f9431992SDoug Thompson #include <asm/msr.h>
2278d88e8aSMauro Carvalho Chehab #include "edac_module.h"
2347ca08a4SBorislav Petkov #include "mce_amd.h"
24cfe40fdbSDoug Thompson
2524f9a7feSBorislav Petkov #define amd64_info(fmt, arg...) \
2624f9a7feSBorislav Petkov edac_printk(KERN_INFO, "amd64", fmt, ##arg)
2724f9a7feSBorislav Petkov
2824f9a7feSBorislav Petkov #define amd64_warn(fmt, arg...) \
295246c540SBorislav Petkov edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
3024f9a7feSBorislav Petkov
3124f9a7feSBorislav Petkov #define amd64_err(fmt, arg...) \
325246c540SBorislav Petkov edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
3324f9a7feSBorislav Petkov
3424f9a7feSBorislav Petkov #define amd64_mc_warn(mci, fmt, arg...) \
3524f9a7feSBorislav Petkov edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
3624f9a7feSBorislav Petkov
3724f9a7feSBorislav Petkov #define amd64_mc_err(mci, fmt, arg...) \
3824f9a7feSBorislav Petkov edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
39cfe40fdbSDoug Thompson
40cfe40fdbSDoug Thompson /*
41cfe40fdbSDoug Thompson * Throughout the comments in this code, the following terms are used:
42cfe40fdbSDoug Thompson *
43cfe40fdbSDoug Thompson * SysAddr, DramAddr, and InputAddr
44cfe40fdbSDoug Thompson *
45cfe40fdbSDoug Thompson * These terms come directly from the amd64 documentation
46cfe40fdbSDoug Thompson * (AMD publication #26094). They are defined as follows:
47cfe40fdbSDoug Thompson *
48cfe40fdbSDoug Thompson * SysAddr:
49cfe40fdbSDoug Thompson * This is a physical address generated by a CPU core or a device
50cfe40fdbSDoug Thompson * doing DMA. If generated by a CPU core, a SysAddr is the result of
51cfe40fdbSDoug Thompson * a virtual to physical address translation by the CPU core's address
52cfe40fdbSDoug Thompson * translation mechanism (MMU).
53cfe40fdbSDoug Thompson *
54cfe40fdbSDoug Thompson * DramAddr:
55cfe40fdbSDoug Thompson * A DramAddr is derived from a SysAddr by subtracting an offset that
56cfe40fdbSDoug Thompson * depends on which node the SysAddr maps to and whether the SysAddr
57cfe40fdbSDoug Thompson * is within a range affected by memory hoisting. The DRAM Base
58cfe40fdbSDoug Thompson * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
59cfe40fdbSDoug Thompson * determine which node a SysAddr maps to.
60cfe40fdbSDoug Thompson *
61cfe40fdbSDoug Thompson * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
62cfe40fdbSDoug Thompson * is within the range of addresses specified by this register, then
63cfe40fdbSDoug Thompson * a value x from the DHAR is subtracted from the SysAddr to produce a
64cfe40fdbSDoug Thompson * DramAddr. Here, x represents the base address for the node that
65cfe40fdbSDoug Thompson * the SysAddr maps to plus an offset due to memory hoisting. See
66cfe40fdbSDoug Thompson * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
67cfe40fdbSDoug Thompson * sys_addr_to_dram_addr() below for more information.
68cfe40fdbSDoug Thompson *
69cfe40fdbSDoug Thompson * If the SysAddr is not affected by the DHAR then a value y is
70cfe40fdbSDoug Thompson * subtracted from the SysAddr to produce a DramAddr. Here, y is the
71cfe40fdbSDoug Thompson * base address for the node that the SysAddr maps to. See section
72cfe40fdbSDoug Thompson * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
73cfe40fdbSDoug Thompson * information.
74cfe40fdbSDoug Thompson *
75cfe40fdbSDoug Thompson * InputAddr:
76cfe40fdbSDoug Thompson * A DramAddr is translated to an InputAddr before being passed to the
77cfe40fdbSDoug Thompson * memory controller for the node that the DramAddr is associated
78cfe40fdbSDoug Thompson * with. The memory controller then maps the InputAddr to a csrow.
79cfe40fdbSDoug Thompson * If node interleaving is not in use, then the InputAddr has the same
80cfe40fdbSDoug Thompson * value as the DramAddr. Otherwise, the InputAddr is produced by
81cfe40fdbSDoug Thompson * discarding the bits used for node interleaving from the DramAddr.
82cfe40fdbSDoug Thompson * See section 3.4.4 for more information.
83cfe40fdbSDoug Thompson *
84cfe40fdbSDoug Thompson * The memory controller for a given node uses its DRAM CS Base and
85cfe40fdbSDoug Thompson * DRAM CS Mask registers to map an InputAddr to a csrow. See
86cfe40fdbSDoug Thompson * sections 3.5.4 and 3.5.5 for more information.
87cfe40fdbSDoug Thompson */
88cfe40fdbSDoug Thompson
89e62d2ca9SBorislav Petkov #define EDAC_MOD_STR "amd64_edac"
90cfe40fdbSDoug Thompson
91cfe40fdbSDoug Thompson /* Extended Model from CPUID, for CPU Revision numbers */
92cfe40fdbSDoug Thompson #define K8_REV_D 1
931433eb99SBorislav Petkov #define K8_REV_E 2
941433eb99SBorislav Petkov #define K8_REV_F 4
951433eb99SBorislav Petkov
96cfe40fdbSDoug Thompson /* Hardware limit on ChipSelect rows per MC and processors per system */
97cfe40fdbSDoug Thompson #define NUM_CHIPSELECTS 8
987f19bf75SBorislav Petkov #define DRAM_RANGES 8
997f19bf75SBorislav Petkov #define NUM_CONTROLLERS 12
100e2be5955SYazen Ghannam
101cfe40fdbSDoug Thompson #define ON true
102f6d6ae96SBorislav Petkov #define OFF false
103f6d6ae96SBorislav Petkov
104cfe40fdbSDoug Thompson /*
105cfe40fdbSDoug Thompson * PCI-defined configuration space registers
106cfe40fdbSDoug Thompson */
107cfe40fdbSDoug Thompson #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
108df71a053SBorislav Petkov #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
109df71a053SBorislav Petkov #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
110a597d2a5SAravind Gopalakrishnan #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
111a597d2a5SAravind Gopalakrishnan #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
112a597d2a5SAravind Gopalakrishnan #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
113a597d2a5SAravind Gopalakrishnan #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
11494c1acf2SAravind Gopalakrishnan #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
11594c1acf2SAravind Gopalakrishnan #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
11685a8885bSAravind Gopalakrishnan #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
11785a8885bSAravind Gopalakrishnan
118cfe40fdbSDoug Thompson /*
119cfe40fdbSDoug Thompson * Function 1 - Address Map
120cfe40fdbSDoug Thompson */
121cfe40fdbSDoug Thompson #define DRAM_BASE_LO 0x40
1227f19bf75SBorislav Petkov #define DRAM_LIMIT_LO 0x44
1237f19bf75SBorislav Petkov
1247f19bf75SBorislav Petkov /*
12518b94f66SAravind Gopalakrishnan * F15 M30h D18F1x2[1C:00]
12618b94f66SAravind Gopalakrishnan */
12718b94f66SAravind Gopalakrishnan #define DRAM_CONT_BASE 0x200
12818b94f66SAravind Gopalakrishnan #define DRAM_CONT_LIMIT 0x204
12918b94f66SAravind Gopalakrishnan
13018b94f66SAravind Gopalakrishnan /*
13118b94f66SAravind Gopalakrishnan * F15 M30h D18F1x2[4C:40]
13218b94f66SAravind Gopalakrishnan */
13318b94f66SAravind Gopalakrishnan #define DRAM_CONT_HIGH_OFF 0x240
13418b94f66SAravind Gopalakrishnan
13518b94f66SAravind Gopalakrishnan #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
136151fa71cSBorislav Petkov #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
137151fa71cSBorislav Petkov #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
138151fa71cSBorislav Petkov
1397f19bf75SBorislav Petkov #define DHAR 0xf0
140bc21fa57SBorislav Petkov #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
141c8e518d5SBorislav Petkov #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
142c8e518d5SBorislav Petkov #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
143c8e518d5SBorislav Petkov
144cfe40fdbSDoug Thompson /* NOTE: Extra mask bit vs K8 */
145cfe40fdbSDoug Thompson #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
146c8e518d5SBorislav Petkov
147cfe40fdbSDoug Thompson #define DCT_CFG_SEL 0x10C
148b2b0c605SBorislav Petkov
149cfe40fdbSDoug Thompson #define DRAM_LOCAL_NODE_BASE 0x120
150c1ae6830SBorislav Petkov #define DRAM_LOCAL_NODE_LIM 0x124
151f08e457cSBorislav Petkov
152f08e457cSBorislav Petkov #define DRAM_BASE_HI 0x140
1537f19bf75SBorislav Petkov #define DRAM_LIMIT_HI 0x144
1547f19bf75SBorislav Petkov
155cfe40fdbSDoug Thompson
156cfe40fdbSDoug Thompson /*
157cfe40fdbSDoug Thompson * Function 2 - DRAM controller
158cfe40fdbSDoug Thompson */
159cfe40fdbSDoug Thompson #define DCSB0 0x40
16011c75eadSBorislav Petkov #define DCSB1 0x140
16111c75eadSBorislav Petkov #define DCSB_CS_ENABLE BIT(0)
16211c75eadSBorislav Petkov
163cfe40fdbSDoug Thompson #define DCSM0 0x60
16411c75eadSBorislav Petkov #define DCSM1 0x160
16511c75eadSBorislav Petkov
166cfe40fdbSDoug Thompson #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
16711c75eadSBorislav Petkov #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
16881f5090dSYazen Ghannam
169cfe40fdbSDoug Thompson #define DRAM_CONTROL 0x78
170a597d2a5SAravind Gopalakrishnan
171a597d2a5SAravind Gopalakrishnan #define DBAM0 0x80
172cfe40fdbSDoug Thompson #define DBAM1 0x180
173cfe40fdbSDoug Thompson
174cfe40fdbSDoug Thompson /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
175cfe40fdbSDoug Thompson #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
1760a5dfc31SBorislav Petkov
177cfe40fdbSDoug Thompson #define DBAM_MAX_VALUE 11
178cfe40fdbSDoug Thompson
179cfe40fdbSDoug Thompson #define DCLR0 0x90
180cb328507SBorislav Petkov #define DCLR1 0x190
181cb328507SBorislav Petkov #define REVE_WIDTH_128 BIT(16)
182cfe40fdbSDoug Thompson #define WIDTH_128 BIT(11)
18341d8bfabSBorislav Petkov
184cfe40fdbSDoug Thompson #define DCHR0 0x94
185cb328507SBorislav Petkov #define DCHR1 0x194
186cb328507SBorislav Petkov #define DDR3_MODE BIT(8)
1871433eb99SBorislav Petkov
188cfe40fdbSDoug Thompson #define DCT_SEL_LO 0x110
18978da121eSBorislav Petkov #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
19078da121eSBorislav Petkov #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
19178da121eSBorislav Petkov
192cb328507SBorislav Petkov #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
19378da121eSBorislav Petkov
194cb328507SBorislav Petkov #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
19578da121eSBorislav Petkov #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
19678da121eSBorislav Petkov
197cfe40fdbSDoug Thompson #define SWAP_INTLV_REG 0x10c
19895b0ef55SBorislav Petkov
19995b0ef55SBorislav Petkov #define DCT_SEL_HI 0x114
20078da121eSBorislav Petkov
201cfe40fdbSDoug Thompson #define F15H_M60H_SCRCTRL 0x1C8
202da92110dSAravind Gopalakrishnan
203da92110dSAravind Gopalakrishnan /*
204cfe40fdbSDoug Thompson * Function 3 - Misc Control
205cfe40fdbSDoug Thompson */
206cfe40fdbSDoug Thompson #define NBCTL 0x40
207c9f4f26eSBorislav Petkov
208cfe40fdbSDoug Thompson #define NBCFG 0x44
209a97fa68eSBorislav Petkov #define NBCFG_CHIPKILL BIT(23)
210a97fa68eSBorislav Petkov #define NBCFG_ECC_ENABLE BIT(22)
211a97fa68eSBorislav Petkov
212cfe40fdbSDoug Thompson /* F3x48: NBSL */
2135980bb9cSBorislav Petkov #define F10_NBSL_EXT_ERR_ECC 0x8
214cfe40fdbSDoug Thompson #define NBSL_PP_OBS 0x2
2155980bb9cSBorislav Petkov
216cfe40fdbSDoug Thompson #define SCRCTRL 0x58
2175980bb9cSBorislav Petkov
218cfe40fdbSDoug Thompson #define F10_ONLINE_SPARE 0xB0
219cfe40fdbSDoug Thompson #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
220614ec9d8SBorislav Petkov #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
221614ec9d8SBorislav Petkov
222cfe40fdbSDoug Thompson #define F10_NB_ARRAY_ADDR 0xB8
223cfe40fdbSDoug Thompson #define F10_NB_ARRAY_DRAM BIT(31)
2246e71a870SBorislav Petkov
225cfe40fdbSDoug Thompson /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
226cfe40fdbSDoug Thompson #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
2276e71a870SBorislav Petkov
228cfe40fdbSDoug Thompson #define F10_NB_ARRAY_DATA 0xBC
229cfe40fdbSDoug Thompson #define F10_NB_ARR_ECC_WR_REQ BIT(17)
23066fed2d4SBorislav Petkov #define SET_NB_DRAM_INJECTION_WRITE(inj) \
2316e71a870SBorislav Petkov (BIT(((inj.word) & 0xF) + 20) | \
2326e71a870SBorislav Petkov F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
23366fed2d4SBorislav Petkov #define SET_NB_DRAM_INJECTION_READ(inj) \
2346e71a870SBorislav Petkov (BIT(((inj.word) & 0xF) + 20) | \
2356e71a870SBorislav Petkov BIT(16) | inj.bit_map)
2366e71a870SBorislav Petkov
2376e71a870SBorislav Petkov
238cfe40fdbSDoug Thompson #define NBCAP 0xE8
2395980bb9cSBorislav Petkov #define NBCAP_CHIPKILL BIT(4)
2405980bb9cSBorislav Petkov #define NBCAP_SECDED BIT(3)
2415980bb9cSBorislav Petkov #define NBCAP_DCT_DUAL BIT(0)
2425980bb9cSBorislav Petkov
243cfe40fdbSDoug Thompson #define EXT_NB_MCA_CFG 0x180
244ad6a32e9SBorislav Petkov
245ad6a32e9SBorislav Petkov /* MSRs */
246f6d6ae96SBorislav Petkov #define MSR_MCGCTL_NBE BIT(4)
2475980bb9cSBorislav Petkov
248cfe40fdbSDoug Thompson /* F17h */
249b64ce7cdSYazen Ghannam
250b64ce7cdSYazen Ghannam /* F0: */
251b64ce7cdSYazen Ghannam #define DF_DHAR 0x104
252b64ce7cdSYazen Ghannam
253b64ce7cdSYazen Ghannam /* UMC CH register offsets */
254196b79fcSYazen Ghannam #define UMCCH_BASE_ADDR 0x0
255b64ce7cdSYazen Ghannam #define UMCCH_BASE_ADDR_SEC 0x10
2567574729eSYazen Ghannam #define UMCCH_ADDR_MASK 0x20
257b64ce7cdSYazen Ghannam #define UMCCH_ADDR_MASK_SEC 0x28
2587574729eSYazen Ghannam #define UMCCH_ADDR_MASK_SEC_DDR5 0x30
2592151c84eSYazen Ghannam #define UMCCH_ADDR_CFG 0x30
26007ed82efSYazen Ghannam #define UMCCH_ADDR_CFG_DDR5 0x40
2612151c84eSYazen Ghannam #define UMCCH_DIMM_CFG 0x80
262b64ce7cdSYazen Ghannam #define UMCCH_DIMM_CFG_DDR5 0x90
2632151c84eSYazen Ghannam #define UMCCH_UMC_CFG 0x100
26407ed82efSYazen Ghannam #define UMCCH_SDP_CTRL 0x104
265196b79fcSYazen Ghannam #define UMCCH_ECC_CTRL 0x14C
266b64ce7cdSYazen Ghannam #define UMCCH_ECC_BAD_SYMBOL 0xD90
26707ed82efSYazen Ghannam #define UMCCH_UMC_CAP 0xDF0
26807ed82efSYazen Ghannam #define UMCCH_UMC_CAP_HI 0xDF4
269196b79fcSYazen Ghannam
270196b79fcSYazen Ghannam /* UMC CH bitfields */
271196b79fcSYazen Ghannam #define UMC_ECC_CHIPKILL_CAP BIT(31)
272b64ce7cdSYazen Ghannam #define UMC_ECC_ENABLED BIT(30)
273196b79fcSYazen Ghannam
274b64ce7cdSYazen Ghannam #define UMC_SDP_INIT BIT(31)
275196b79fcSYazen Ghannam
276196b79fcSYazen Ghannam /* Error injection control structure */
277cfe40fdbSDoug Thompson struct error_injection {
278cfe40fdbSDoug Thompson u32 section;
279cfe40fdbSDoug Thompson u32 word;
280cfe40fdbSDoug Thompson u32 bit_map;
281cfe40fdbSDoug Thompson };
282cfe40fdbSDoug Thompson
283cfe40fdbSDoug Thompson /* low and high part of PCI config space regs */
2847f19bf75SBorislav Petkov struct reg_pair {
2857f19bf75SBorislav Petkov u32 lo, hi;
2867f19bf75SBorislav Petkov };
2877f19bf75SBorislav Petkov
2887f19bf75SBorislav Petkov /*
2897f19bf75SBorislav Petkov * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
2907f19bf75SBorislav Petkov */
2917f19bf75SBorislav Petkov struct dram_range {
2927f19bf75SBorislav Petkov struct reg_pair base;
2937f19bf75SBorislav Petkov struct reg_pair lim;
2947f19bf75SBorislav Petkov };
2957f19bf75SBorislav Petkov
2967f19bf75SBorislav Petkov /* A DCT chip selects collection */
29711c75eadSBorislav Petkov struct chip_select {
29811c75eadSBorislav Petkov u32 csbases[NUM_CHIPSELECTS];
29911c75eadSBorislav Petkov u32 csbases_sec[NUM_CHIPSELECTS];
3007574729eSYazen Ghannam u8 b_cnt;
30111c75eadSBorislav Petkov
30211c75eadSBorislav Petkov u32 csmasks[NUM_CHIPSELECTS];
30311c75eadSBorislav Petkov u32 csmasks_sec[NUM_CHIPSELECTS];
3047574729eSYazen Ghannam u8 m_cnt;
30511c75eadSBorislav Petkov };
30611c75eadSBorislav Petkov
30711c75eadSBorislav Petkov struct amd64_umc {
308f1cbbec9SYazen Ghannam u32 dimm_cfg; /* DIMM Configuration reg */
309b64ce7cdSYazen Ghannam u32 umc_cfg; /* Configuration reg */
31007ed82efSYazen Ghannam u32 sdp_ctrl; /* SDP Control reg */
311f1cbbec9SYazen Ghannam u32 ecc_ctrl; /* DRAM ECC Control reg */
312b64ce7cdSYazen Ghannam u32 umc_cap_hi; /* Capabilities High reg */
31307ed82efSYazen Ghannam
31475aeaaf2SYazen Ghannam /* cache the dram_type */
31575aeaaf2SYazen Ghannam enum mem_type dram_type;
31675aeaaf2SYazen Ghannam };
317f1cbbec9SYazen Ghannam
318f1cbbec9SYazen Ghannam struct amd64_family_flags {
319ed623d55SMuralidhara M K /*
320ed623d55SMuralidhara M K * Indicates that the system supports the new register offsets, etc.
321ed623d55SMuralidhara M K * first introduced with Family 19h Model 10h.
322ed623d55SMuralidhara M K */
323ed623d55SMuralidhara M K __u64 zn_regs_v2 : 1,
324ed623d55SMuralidhara M K
325ed623d55SMuralidhara M K __reserved : 63;
326ed623d55SMuralidhara M K };
327ed623d55SMuralidhara M K
328ed623d55SMuralidhara M K struct amd64_pvt {
329cfe40fdbSDoug Thompson struct low_ops *ops;
330b8cfa02fSBorislav Petkov
331b8cfa02fSBorislav Petkov /* pci_device handles which we utilize */
332cfe40fdbSDoug Thompson struct pci_dev *F1, *F2, *F3;
333cf981562SYazen Ghannam
334cfe40fdbSDoug Thompson u16 mc_node_id; /* MC index of this MC node */
335c7e5301aSDaniel J Blueman u8 fam; /* CPU family */
33618b94f66SAravind Gopalakrishnan u8 model; /* ... model */
337a4b4bedcSBorislav Petkov u8 stepping; /* ... stepping */
338a4b4bedcSBorislav Petkov
339a4b4bedcSBorislav Petkov int ext_model; /* extended model value of this node */
340cfe40fdbSDoug Thompson
341cfe40fdbSDoug Thompson /* Raw registers */
342cfe40fdbSDoug Thompson u32 dclr0; /* DRAM Configuration Low DCT0 reg */
343cfe40fdbSDoug Thompson u32 dclr1; /* DRAM Configuration Low DCT1 reg */
344cfe40fdbSDoug Thompson u32 dchr0; /* DRAM Configuration High DCT0 reg */
345cfe40fdbSDoug Thompson u32 dchr1; /* DRAM Configuration High DCT1 reg */
346cfe40fdbSDoug Thompson u32 nbcap; /* North Bridge Capabilities */
347cfe40fdbSDoug Thompson u32 nbcfg; /* F10 North Bridge Configuration */
348cfe40fdbSDoug Thompson u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
349cfe40fdbSDoug Thompson u32 dhar; /* DRAM Hoist reg */
350cfe40fdbSDoug Thompson u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
351cfe40fdbSDoug Thompson u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
352cfe40fdbSDoug Thompson
353cfe40fdbSDoug Thompson /* one for each DCT/UMC */
354d971e28eSYazen Ghannam struct chip_select csels[NUM_CONTROLLERS];
355d971e28eSYazen Ghannam
356cfe40fdbSDoug Thompson /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
3577f19bf75SBorislav Petkov struct dram_range ranges[DRAM_RANGES];
3587f19bf75SBorislav Petkov
359cfe40fdbSDoug Thompson u64 top_mem; /* top of memory below 4GB */
360cfe40fdbSDoug Thompson u64 top_mem2; /* top of memory above 4GB */
361cfe40fdbSDoug Thompson
362cfe40fdbSDoug Thompson u32 dct_sel_lo; /* DRAM Controller Select Low */
36378da121eSBorislav Petkov u32 dct_sel_hi; /* DRAM Controller Select High */
36478da121eSBorislav Petkov u32 online_spare; /* On-Line spare Reg */
365cfe40fdbSDoug Thompson
366cfe40fdbSDoug Thompson /* x4, x8, or x16 syndromes in use */
3677835961dSYazen Ghannam u8 ecc_sym_sz;
368a3b7db09SBorislav Petkov
369ad6a32e9SBorislav Petkov const char *ctl_name;
370ed623d55SMuralidhara M K u16 f1_id, f2_id;
371ed623d55SMuralidhara M K /* Maximum number of memory controllers per die/node. */
372ed623d55SMuralidhara M K u8 max_mcs;
373ed623d55SMuralidhara M K
374ed623d55SMuralidhara M K struct amd64_family_flags flags;
375ed623d55SMuralidhara M K /* place to store error injection parameters prior to issue */
376cfe40fdbSDoug Thompson struct error_injection injection;
377cfe40fdbSDoug Thompson
378a597d2a5SAravind Gopalakrishnan /*
37975aeaaf2SYazen Ghannam * cache the dram_type
38075aeaaf2SYazen Ghannam *
38175aeaaf2SYazen Ghannam * NOTE: Don't use this for Family 17h and later.
38275aeaaf2SYazen Ghannam * Use dram_type in struct amd64_umc instead.
38375aeaaf2SYazen Ghannam */
38475aeaaf2SYazen Ghannam enum mem_type dram_type;
385a597d2a5SAravind Gopalakrishnan
386f1cbbec9SYazen Ghannam struct amd64_umc *umc; /* UMC registers */
387f1cbbec9SYazen Ghannam };
388ae7bb7c6SBorislav Petkov
389ae7bb7c6SBorislav Petkov enum err_codes {
39033ca0643SBorislav Petkov DECODE_OK = 0,
39133ca0643SBorislav Petkov ERR_NODE = -1,
39233ca0643SBorislav Petkov ERR_CSROW = -2,
39333ca0643SBorislav Petkov ERR_CHANNEL = -3,
39433ca0643SBorislav Petkov ERR_SYND = -4,
395713ad546SYazen Ghannam ERR_NORM_ADDR = -5,
396713ad546SYazen Ghannam };
39733ca0643SBorislav Petkov
39833ca0643SBorislav Petkov struct err_info {
39933ca0643SBorislav Petkov int err_code;
40033ca0643SBorislav Petkov struct mem_ctl_info *src_mci;
40133ca0643SBorislav Petkov int csrow;
40233ca0643SBorislav Petkov int channel;
40333ca0643SBorislav Petkov u16 syndrome;
40433ca0643SBorislav Petkov u32 page;
40533ca0643SBorislav Petkov u32 offset;
40633ca0643SBorislav Petkov };
40733ca0643SBorislav Petkov
get_umc_base(u8 channel)40833ca0643SBorislav Petkov static inline u32 get_umc_base(u8 channel)
409196b79fcSYazen Ghannam {
410196b79fcSYazen Ghannam /* chY: 0xY50000 */
411bdcee774SYazen Ghannam return 0x50000 + (channel << 20);
412bdcee774SYazen Ghannam }
413196b79fcSYazen Ghannam
get_dram_base(struct amd64_pvt * pvt,u8 i)414196b79fcSYazen Ghannam static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
415c7e5301aSDaniel J Blueman {
4167f19bf75SBorislav Petkov u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
4177f19bf75SBorislav Petkov
4187f19bf75SBorislav Petkov if (boot_cpu_data.x86 == 0xf)
4197f19bf75SBorislav Petkov return addr;
4207f19bf75SBorislav Petkov
4217f19bf75SBorislav Petkov return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
4227f19bf75SBorislav Petkov }
4237f19bf75SBorislav Petkov
get_dram_limit(struct amd64_pvt * pvt,u8 i)4247f19bf75SBorislav Petkov static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
425c7e5301aSDaniel J Blueman {
4267f19bf75SBorislav Petkov u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
4277f19bf75SBorislav Petkov
4287f19bf75SBorislav Petkov if (boot_cpu_data.x86 == 0xf)
4297f19bf75SBorislav Petkov return lim;
4307f19bf75SBorislav Petkov
4317f19bf75SBorislav Petkov return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
4327f19bf75SBorislav Petkov }
4337f19bf75SBorislav Petkov
extract_syndrome(u64 status)4347f19bf75SBorislav Petkov static inline u16 extract_syndrome(u64 status)
435f192c7b1SBorislav Petkov {
436f192c7b1SBorislav Petkov return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
437f192c7b1SBorislav Petkov }
438f192c7b1SBorislav Petkov
dct_sel_interleave_addr(struct amd64_pvt * pvt)439f192c7b1SBorislav Petkov static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
44018b94f66SAravind Gopalakrishnan {
44118b94f66SAravind Gopalakrishnan if (pvt->fam == 0x15 && pvt->model >= 0x30)
44218b94f66SAravind Gopalakrishnan return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
44318b94f66SAravind Gopalakrishnan ((pvt->dct_sel_lo >> 6) & 0x3);
44418b94f66SAravind Gopalakrishnan
44518b94f66SAravind Gopalakrishnan return ((pvt)->dct_sel_lo >> 6) & 0x3;
44618b94f66SAravind Gopalakrishnan }
44718b94f66SAravind Gopalakrishnan /*
448ae7bb7c6SBorislav Petkov * per-node ECC settings descriptor
449ae7bb7c6SBorislav Petkov */
450ae7bb7c6SBorislav Petkov struct ecc_settings {
451ae7bb7c6SBorislav Petkov u32 old_nbctl;
452ae7bb7c6SBorislav Petkov bool nbctl_valid;
453ae7bb7c6SBorislav Petkov
454ae7bb7c6SBorislav Petkov struct flags {
455cfe40fdbSDoug Thompson unsigned long nb_mce_enable:1;
456d95cf4deSBorislav Petkov unsigned long nb_ecc_prev:1;
457d95cf4deSBorislav Petkov } flags;
458cfe40fdbSDoug Thompson };
459cfe40fdbSDoug Thompson
460cfe40fdbSDoug Thompson /*
461cfe40fdbSDoug Thompson * Each of the PCI Device IDs types have their own set of hardware accessor
462cfe40fdbSDoug Thompson * functions and per device encoding/decoding logic.
463cfe40fdbSDoug Thompson */
464cfe40fdbSDoug Thompson struct low_ops {
465cfe40fdbSDoug Thompson void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci, u64 sys_addr,
466f192c7b1SBorislav Petkov struct err_info *err);
467ed623d55SMuralidhara M K int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
468a597d2a5SAravind Gopalakrishnan unsigned int cs_mode, int cs_mask_nr);
469ed623d55SMuralidhara M K int (*hw_info_get)(struct amd64_pvt *pvt);
4709a97a7f4SYazen Ghannam bool (*ecc_enabled)(struct amd64_pvt *pvt);
471eb2bcdfcSMuralidhara M K void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci);
4720a42a37fSMuralidhara M K void (*dump_misc_regs)(struct amd64_pvt *pvt);
473f6f36382SMuralidhara M K void (*get_err_info)(struct mce *m, struct err_info *err);
474b3ece3a6SMuralidhara M K };
475cfe40fdbSDoug Thompson
476cfe40fdbSDoug Thompson int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
47766fed2d4SBorislav Petkov u32 *val, const char *func);
47866fed2d4SBorislav Petkov int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
479b2b0c605SBorislav Petkov u32 val, const char *func);
480b2b0c605SBorislav Petkov
4816ba5dcdcSBorislav Petkov #define amd64_read_pci_cfg(pdev, offset, val) \
4826ba5dcdcSBorislav Petkov __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
483b2b0c605SBorislav Petkov
484b2b0c605SBorislav Petkov #define amd64_write_pci_cfg(pdev, offset, val) \
485b2b0c605SBorislav Petkov __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
486b2b0c605SBorislav Petkov
487b2b0c605SBorislav Petkov #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
488c5608759SMauro Carvalho Chehab
48966fed2d4SBorislav Petkov /* Injection helpers */
disable_caches(void * dummy)49066fed2d4SBorislav Petkov static inline void disable_caches(void *dummy)
49166fed2d4SBorislav Petkov {
49266fed2d4SBorislav Petkov write_cr0(read_cr0() | X86_CR0_CD);
49366fed2d4SBorislav Petkov wbinvd();
49466fed2d4SBorislav Petkov }
49566fed2d4SBorislav Petkov
enable_caches(void * dummy)49666fed2d4SBorislav Petkov static inline void enable_caches(void *dummy)
49766fed2d4SBorislav Petkov {
49866fed2d4SBorislav Petkov write_cr0(read_cr0() & ~X86_CR0_CD);
49966fed2d4SBorislav Petkov }
50066fed2d4SBorislav Petkov
dram_intlv_en(struct amd64_pvt * pvt,unsigned int i)50118b94f66SAravind Gopalakrishnan static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
50218b94f66SAravind Gopalakrishnan {
50318b94f66SAravind Gopalakrishnan if (pvt->fam == 0x15 && pvt->model >= 0x30) {
50418b94f66SAravind Gopalakrishnan u32 tmp;
50518b94f66SAravind Gopalakrishnan amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
50618b94f66SAravind Gopalakrishnan return (u8) tmp & 0xF;
50718b94f66SAravind Gopalakrishnan }
50818b94f66SAravind Gopalakrishnan return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
50918b94f66SAravind Gopalakrishnan }
51018b94f66SAravind Gopalakrishnan
dhar_valid(struct amd64_pvt * pvt)51118b94f66SAravind Gopalakrishnan static inline u8 dhar_valid(struct amd64_pvt *pvt)
51218b94f66SAravind Gopalakrishnan {
51318b94f66SAravind Gopalakrishnan if (pvt->fam == 0x15 && pvt->model >= 0x30) {
51418b94f66SAravind Gopalakrishnan u32 tmp;
51518b94f66SAravind Gopalakrishnan amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
51618b94f66SAravind Gopalakrishnan return (tmp >> 1) & BIT(0);
51718b94f66SAravind Gopalakrishnan }
51818b94f66SAravind Gopalakrishnan return (pvt)->dhar & BIT(0);
51918b94f66SAravind Gopalakrishnan }
52018b94f66SAravind Gopalakrishnan
dct_sel_baseaddr(struct amd64_pvt * pvt)52118b94f66SAravind Gopalakrishnan static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
52218b94f66SAravind Gopalakrishnan {
52318b94f66SAravind Gopalakrishnan if (pvt->fam == 0x15 && pvt->model >= 0x30) {
52418b94f66SAravind Gopalakrishnan u32 tmp;
52518b94f66SAravind Gopalakrishnan amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
52618b94f66SAravind Gopalakrishnan return (tmp >> 11) & 0x1FFF;
52718b94f66SAravind Gopalakrishnan }
52818b94f66SAravind Gopalakrishnan return (pvt)->dct_sel_lo & 0xFFFFF800;
52918b94f66SAravind Gopalakrishnan }
53018b94f66SAravind Gopalakrishnan