| /openbmc/qemu/qga/installer/ |
| H A D | qemu-ga.wxs | 4 <?define ArchLib=libgcc_s_seh-1.dll?>
8 <?define ArchLib=libgcc_s_dw2-1.dll?>
62 …<File Id="libstdc++-6.lib" Name="libstdc++-6.dll" Source="$(var.BIN_DIR)/libstdc++-6.dll" KeyPath=…
65 …<File Id="qga_vss.dll" Name="qga-vss.dll" Source="$(var.BUILD_DIR)/qga/vss-win32/qga-vss.dll" KeyP…
88 … <File Id="iconv.dll" Name="iconv.dll" Source="$(var.BIN_DIR)/iconv.dll" KeyPath="yes" DiskId="1"/>
94 …<File Id="libglib_2.0_0.dll" Name="libglib-2.0-0.dll" Source="$(var.BIN_DIR)/libglib-2.0-0.dll" Ke…
97 …<File Id="libintl_8.dll" Name="libintl-8.dll" Source="$(var.BIN_DIR)/libintl-8.dll" KeyPath="yes" …
100 …<File Id="libssp_0.dll" Name="libssp-0.dll" Source="$(var.BIN_DIR)/libssp-0.dll" KeyPath="yes" Dis…
103 …<File Id="libwinpthread_1.dll" Name="libwinpthread-1.dll" Source="$(var.BIN_DIR)/libwinpthread-1.d…
107 …<File Id="libpcre_1.dll" Name="libpcre-1.dll" Source="$(var.BIN_DIR)/libpcre-1.dll" KeyPath="yes" …
[all …]
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| /openbmc/openbmc/poky/meta/recipes-devtools/binutils/binutils/ |
| H A D | 0014-Remove-duplicate-pe-dll.o-entry-deom-targ_extra_ofil.patch | 4 Subject: [PATCH] Remove duplicate pe-dll.o entry deom targ_extra_ofiles
7 aarch64-pe which introduced wrapper over pep-dll.c for x86_64 as well as
8 aarch64, on x86_64 it was added but the old object pe-dll.o needs to be
9 removed too, otherwise build fails with duplicate symbols from pe-dll.o
10 and pep-dll-x86_64.o
28 - targ_extra_ofiles="deffilep.o pdb.o pep-dll.o pe-dll.o"
29 + targ_extra_ofiles="deffilep.o pdb.o pe-dll.o"
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| /openbmc/qemu/scripts/ |
| H A D | nsis.py | 29 dep = line.split("DLL Name: ")[1].strip()
33 dll = os.path.join(search_path, dep)
34 if not os.path.exists(dll):
35 # assume it's a Windows provided dll, skip it
39 # locate the dll dependencies recursively
40 rdeps = find_deps(dll, search_path, analyzed_deps)
92 dlldir = os.path.join(destdir + prefix, "dll")
98 # find all dll dependencies
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | sleep24xx.S | 31 * R0 : DLL ctrl value pre-Sleep
36 * when we get called, but the DLL probably isn't. We will wait a bit more in
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
48 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
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| H A D | sram243x.S | 45 /* dll lock mode */
52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
55 bl i_dll_wait @ wait for dll to lock
57 /* get dll value */
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
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| H A D | sram242x.S | 45 /* dll lock mode */
52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
55 bl i_dll_wait @ wait for dll to lock
57 /* get dll value */
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
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| H A D | sdrc2xxx.c | 30 /* Memory timing, DLL mode flags */
56 * Check the DLL lock state, and return tue if running in unlock mode.
57 * This is needed to compensate for the shifted DLL value in unlock mode.
131 /* With DDR we need to determine the low frequency DLL value */ in omap2xxx_sdrc_init_params()
148 /* set fast timings with DLL filter disabled */ in omap2xxx_sdrc_init_params()
162 /* 90 degree phase for anything below 133MHz + disable DLL filter */ in omap2xxx_sdrc_init_params()
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| /openbmc/linux/include/soc/at91/ |
| H A D | sama7-ddr.h | 16 #define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
18 #define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
19 #define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */
29 #define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
30 #define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */
49 #define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register */
50 #define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register */
51 #define DDR3PHY_DXDLLCR_DLLDIS (1 << 31) /* DLL Disable */
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| /openbmc/u-boot/arch/arm/mach-at91/ |
| H A D | mpddrc.c | 84 * Issue an extended mode register set(EMRS1) to enable DLL and in ddr2_init()
90 /* Enable DLL reset */ in ddr2_init()
94 /* A mode register set(MRS) cycle is issued to reset DLL */ in ddr2_init()
104 /* Disable DLL reset */ in ddr2_init()
108 /* A mode register set (MRS) cycle is issued to disable DLL reset */ in ddr2_init()
201 * Write a one to the DLL bit (enable DLL reset) in the MPDDRC in ddr3_init()
205 /* A Mode Register Set (MRS) cycle is issued to reset DLL. */ in ddr3_init()
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | cdns,sdhci.yaml | 34 # PHY DLL input delays:
84 # PHY DLL clock delays:
92 cdns,phy-dll-delay-sdclk:
100 cdns,phy-dll-delay-sdclk-hsmmc:
108 cdns,phy-dll-delay-strobe:
155 cdns,phy-dll-delay-sdclk = <0>;
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| /openbmc/linux/arch/x86/boot/ |
| H A D | early_serial_console.c | 21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
104 unsigned char lcr, dll, dlh; in probe_baud() local
109 dll = inb(port + DLL); in probe_baud()
112 quot = (dlh << 8) | dll; in probe_baud()
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| /openbmc/linux/drivers/phy/intel/ |
| H A D | phy-intel-keembay-emmc.c | 76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
131 /* Set the frequency of the DLL operation */ in keembay_emmc_phy_power()
135 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in keembay_emmc_phy_power()
139 /* Turn on the DLL */ in keembay_emmc_phy_power()
143 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in keembay_emmc_phy_power()
148 * We turned on the DLL even though the rate was 0 because we the in keembay_emmc_phy_power()
149 * clock might be turned on later. ...but we can't wait for the DLL in keembay_emmc_phy_power()
160 * After enabling analog DLL circuits docs say that we need 10.2 us if in keembay_emmc_phy_power()
168 * NOTE: There appear to be corner cases where the DLL seems to take in keembay_emmc_phy_power()
|
| H A D | phy-intel-lgm-emmc.c | 110 /* Set the frequency of the DLL operation */ in intel_emmc_phy_power()
114 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in intel_emmc_phy_power()
118 /* Turn on the DLL */ in intel_emmc_phy_power()
122 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in intel_emmc_phy_power()
127 * After enabling analog DLL circuits docs say that we need 10.2 us if in intel_emmc_phy_power()
135 * NOTE: There appear to be corner cases where the DLL seems to take in intel_emmc_phy_power()
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | udbg_16550.c | 98 unsigned int dll, base_bauds; in udbg_uart_setup() local
109 dll = base_bauds / speed; in udbg_uart_setup()
115 udbg_uart_out(UART_DLL, dll & 0xff); in udbg_uart_setup()
116 udbg_uart_out(UART_DLM, dll >> 8); in udbg_uart_setup()
127 unsigned int dll, dlm, divisor, prescaler, speed; in udbg_probe_uart_speed() local
136 dll = udbg_uart_in(UART_DLL); in udbg_probe_uart_speed()
138 divisor = dlm << 8 | dll; in udbg_probe_uart_speed()
|
| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun4i.h | 23 u32 gdllcr; /* 0x20 global dll control register */
44 u32 dllctr; /* 0x200 dll control register */
45 u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
46 /* 0x208 dll control register 1(byte 1) */
47 /* 0x20c dll control register 2(byte 2) */
48 /* 0x210 dll control register 3(byte 3) */
49 /* 0x214 dll control register 4(byte 4) */
|
| /openbmc/u-boot/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 136 /* Enable DLL, Full strength, ODT Disabled */ in ddr_init()
142 /* Reset DLL */ in ddr_init()
160 /* Enable OCD defaults, Enable DLL, Reduced Drive Strength */ in ddr_init()
166 /* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */ in ddr_init()
194 /* Reset DLL, Burst Length 8, CAS Latency 3 */ in ddr_init()
200 /* Enable DLL, Full strength */ in ddr_init()
209 /* Normal DLL, Burst Length 8, CAS Latency 3 */ in ddr_init()
|
| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | dmc_init_exynos4.c | 83 * DLL Parameter Setting: in dmc_init()
98 * Update DLL Information: in dmc_init()
99 * Force DLL Resyncronization in dmc_init()
104 /* Set DLL Parameters */ in dmc_init()
107 /* DLL Start */ in dmc_init()
|
| /openbmc/qemu/qga/ |
| H A D | vss-win32.c | 21 #define QGA_VSS_DLL "qga-vss.dll"
25 /* Call a function in qga-vss.dll with the specified name */
74 /* Load qga-vss.dll */
109 /* Unload qga-provider.dll */
|
| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-multimedia/jack/jack/ |
| H A D | 0002-Fix-all-DeprecationWarning-invalid-escape-sequence.patch | 175 dll=dllnames[0].lower()
176 - dll=re.sub('\.dll$', '', dll)
177 + dll=re.sub(r'\.dll$', '', dll)
178 return (lt_libdir, dll, False)
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | sdhci-esdhc.h | 89 /* DLL Config 0 Register */
95 /* DLL Config 1 Register */
99 /* DLL Status 0 Register */
|
| H A D | sdhci-pci-o2micro.c | 187 * This function is used to detect dll lock status.
188 * Since the dll lock status bit will toggle randomly
238 * This function is used to fix o2 dll shift issue.
281 * need wait at least 5ms for dll status stable, in sdhci_o2_dll_recovery()
291 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", in sdhci_o2_dll_recovery()
304 pr_err("%s: DLL adjust over max times\n", in sdhci_o2_dll_recovery()
361 /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ in sdhci_o2_execute_tuning()
382 /* wait DLL lock, timeout value 5ms */ in sdhci_o2_execute_tuning()
385 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", in sdhci_o2_execute_tuning()
388 * Judge the tuning reason, whether caused by dll shift in sdhci_o2_execute_tuning()
[all …]
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| /openbmc/linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-emmc.c | 150 * pretty spot on for the DLL range, so warn if we're too in rockchip_emmc_phy_power()
186 /* Set the frequency of the DLL operation */ in rockchip_emmc_phy_power()
192 /* Turn on the DLL */ in rockchip_emmc_phy_power()
200 * We turned on the DLL even though the rate was 0 because we the in rockchip_emmc_phy_power()
201 * clock might be turned on later. ...but we can't wait for the DLL in rockchip_emmc_phy_power()
212 * After enabling analog DLL circuits docs say that we need 10.2 us if in rockchip_emmc_phy_power()
220 * NOTE: There appear to be corner cases where the DLL seems to take in rockchip_emmc_phy_power()
|
| /openbmc/u-boot/arch/mips/mach-ath79/qca953x/ |
| H A D | ddr.c | 257 /* ODT disable, Full strength, Enable DLL */ in ddr_init()
265 /* Reset DLL, CAS Latency 3, Burst Length 8 */ in ddr_init()
283 /* Normal DLL, CAS Latency 3, Burst Length 8 */ in ddr_init()
347 /* 150 ohm, Reduced strength, Enable DLL */ in ddr_init()
355 /* Reset DLL, CAS Latency 4, Burst Length 8 */ in ddr_init()
373 /* Normal DLL, CAS Latency 4, Burst Length 8 */ in ddr_init()
381 /* Enable OCD, Enable DLL, Reduced Drive Strength */ in ddr_init()
389 /* OCD diable, Enable DLL, Reduced Drive Strength */ in ddr_init()
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
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| /openbmc/u-boot/arch/arm/cpu/arm1136/mx35/ |
| H A D | mx35_sdram.c | 91 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ in mx3_setup_sdram_bank()
92 writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */ in mx3_setup_sdram_bank()
111 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ in mx3_setup_sdram_bank()
|