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/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sdm845-mdss.yaml76 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
88 power-domains = <&dispcc MDSS_GDSC>;
91 <&dispcc DISP_CC_MDSS_MDP_CLK>;
109 <&dispcc DISP_CC_MDSS_AHB_CLK>,
110 <&dispcc DISP_CC_MDSS_AXI_CLK>,
111 <&dispcc DISP_CC_MDSS_MDP_CLK>,
112 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
148 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
149 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
150 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
[all …]
H A Dqcom,sc7280-mdss.yaml26 - description: Display AHB clock from dispcc
86 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
99 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
101 <&dispcc DISP_CC_MDSS_AHB_CLK>,
102 <&dispcc DISP_CC_MDSS_MDP_CLK>;
126 <&dispcc DISP_CC_MDSS_AHB_CLK>,
127 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
128 <&dispcc DISP_CC_MDSS_MDP_CLK>,
129 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
177 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
[all …]
H A Dqcom,sm6350-mdss.yaml68 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
79 power-domains = <&dispcc MDSS_GDSC>;
83 <&dispcc DISP_CC_MDSS_MDP_CLK>;
102 <&dispcc DISP_CC_MDSS_AHB_CLK>,
103 <&dispcc DISP_CC_MDSS_ROT_CLK>,
104 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
105 <&dispcc DISP_CC_MDSS_MDP_CLK>,
106 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
110 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
111 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
[all …]
H A Dqcom,sc7180-mdss.yaml26 - description: Display AHB clock from dispcc
78 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
91 power-domains = <&dispcc MDSS_GDSC>;
93 <&dispcc DISP_CC_MDSS_AHB_CLK>,
94 <&dispcc DISP_CC_MDSS_MDP_CLK>;
115 <&dispcc DISP_CC_MDSS_AHB_CLK>,
116 <&dispcc DISP_CC_MDSS_ROT_CLK>,
117 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
118 <&dispcc DISP_CC_MDSS_MDP_CLK>,
119 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm8550-mdss.yaml74 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
90 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
92 power-domains = <&dispcc MDSS_GDSC>;
94 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
97 <&dispcc DISP_CC_MDSS_MDP_CLK>;
118 <&dispcc DISP_CC_MDSS_AHB_CLK>,
119 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
120 <&dispcc DISP_CC_MDSS_MDP_CLK>,
121 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
129 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm8450-mdss.yaml74 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
90 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
92 power-domains = <&dispcc MDSS_GDSC>;
94 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
97 <&dispcc DISP_CC_MDSS_MDP_CLK>;
118 <&dispcc DISP_CC_MDSS_AHB_CLK>,
119 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
120 <&dispcc DISP_CC_MDSS_MDP_CLK>,
121 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
129 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm8250-mdss.yaml74 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
90 power-domains = <&dispcc MDSS_GDSC>;
92 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
114 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
116 <&dispcc DISP_CC_MDSS_MDP_CLK>,
117 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
120 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
181 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
182 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,sm8150-mdss.yaml72 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
88 power-domains = <&dispcc MDSS_GDSC>;
90 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
93 <&dispcc DISP_CC_MDSS_MDP_CLK>;
112 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_CLK>,
115 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
118 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
179 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
180 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,sm6375-mdss.yaml70 #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
79 power-domains = <&dispcc MDSS_GDSC>;
82 <&dispcc DISP_CC_MDSS_AHB_CLK>,
83 <&dispcc DISP_CC_MDSS_MDP_CLK>;
102 <&dispcc DISP_CC_MDSS_AHB_CLK>,
103 <&dispcc DISP_CC_MDSS_ROT_CLK>,
104 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
105 <&dispcc DISP_CC_MDSS_MDP_CLK>,
106 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
116 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm6125-mdss.yaml68 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
84 <&dispcc DISP_CC_MDSS_AHB_CLK>,
85 <&dispcc DISP_CC_MDSS_MDP_CLK>;
90 power-domains = <&dispcc MDSS_GDSC>;
108 <&dispcc DISP_CC_MDSS_AHB_CLK>,
109 <&dispcc DISP_CC_MDSS_ROT_CLK>,
110 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
111 <&dispcc DISP_CC_MDSS_MDP_CLK>,
112 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
121 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm6115-mdss.yaml64 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
76 power-domains = <&dispcc MDSS_GDSC>;
79 <&dispcc DISP_CC_MDSS_MDP_CLK>;
96 <&dispcc DISP_CC_MDSS_AHB_CLK>,
97 <&dispcc DISP_CC_MDSS_MDP_CLK>,
98 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
99 <&dispcc DISP_CC_MDSS_ROT_CLK>,
100 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
130 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
131 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,sm8350-mdss.yaml79 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
95 power-domains = <&dispcc MDSS_GDSC>;
96 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
98 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
101 <&dispcc DISP_CC_MDSS_MDP_CLK>;
122 <&dispcc DISP_CC_MDSS_AHB_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
124 <&dispcc DISP_CC_MDSS_MDP_CLK>,
125 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
133 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,qcm2290-mdss.yaml70 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
83 power-domains = <&dispcc MDSS_GDSC>;
86 <&dispcc DISP_CC_MDSS_MDP_CLK>;
107 <&dispcc DISP_CC_MDSS_AHB_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>,
109 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
110 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
140 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
141 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
142 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
[all …]
H A Dqcom,qcm2290-dpu.yaml31 - description: Display AHB clock from dispcc
32 - description: Display core clock from dispcc
33 - description: Display lut clock from dispcc
34 - description: Display vsync clock from dispcc
55 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
66 <&dispcc DISP_CC_MDSS_AHB_CLK>,
67 <&dispcc DISP_CC_MDSS_MDP_CLK>,
68 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
69 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm6115-dpu.yaml57 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
68 <&dispcc DISP_CC_MDSS_AHB_CLK>,
69 <&dispcc DISP_CC_MDSS_MDP_CLK>,
70 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
71 <&dispcc DISP_CC_MDSS_ROT_CLK>,
72 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sc7180-dpu.yaml81 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
93 <&dispcc DISP_CC_MDSS_AHB_CLK>,
94 <&dispcc DISP_CC_MDSS_ROT_CLK>,
95 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
96 <&dispcc DISP_CC_MDSS_MDP_CLK>,
97 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Ddp-controller.yaml178 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
190 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
191 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
192 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
193 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
194 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
199 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
200 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
H A Dqcom,sm8550-dpu.yaml57 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
70 <&dispcc DISP_CC_MDSS_AHB_CLK>,
71 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
72 <&dispcc DISP_CC_MDSS_MDP_CLK>,
73 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
81 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm8350-dpu.yaml50 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
64 <&dispcc DISP_CC_MDSS_AHB_CLK>,
65 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
66 <&dispcc DISP_CC_MDSS_MDP_CLK>,
67 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
75 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm8450-dpu.yaml57 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
71 <&dispcc DISP_CC_MDSS_AHB_CLK>,
72 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
73 <&dispcc DISP_CC_MDSS_MDP_CLK>,
74 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
82 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sc7280-dpu.yaml57 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
70 <&dispcc DISP_CC_MDSS_AHB_CLK>,
71 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
72 <&dispcc DISP_CC_MDSS_MDP_CLK>,
73 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm8150-dpu.yaml46 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
58 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
60 <&dispcc DISP_CC_MDSS_MDP_CLK>,
61 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
64 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,dispcc-sm8x50.yaml4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
25 - qcom,sm8150-dispcc
26 - qcom,sm8250-dispcc
27 - qcom,sm8350-dispcc
87 compatible = "qcom,sm8250-dispcc";
H A Dqcom,qcm2290-dispcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
16 See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
20 const: qcom,qcm2290-dispcc
65 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
69 compatible = "qcom,qcm2290-dispcc";
/openbmc/linux/drivers/clk/qcom/
H A DMakefile64 obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
71 obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
72 obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
73 obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
91 obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
105 obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
106 obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
107 obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
108 obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o
109 obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
[all …]

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