Home
last modified time | relevance | path

Searched +full:designware +full:- +full:pcie (Results 1 – 25 of 111) sorted by relevance

12345

/openbmc/linux/drivers/pci/controller/dwc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
27 required only for DT-based platforms. ACPI platforms with the
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
37 SoCs. The PCI controller on Amlogic is based on DesignWare hardware
38 and therefore the driver re-uses the DesignWare core functions to
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
7 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
8 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
9 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
10 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
[all …]
H A Dpcie-designware-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe RC driver for Synopsys DesignWare Core
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
21 #include "pcie-designware.h"
58 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in dw_plat_pcie_ep_raise_irq()
85 struct dw_pcie *pci = dw_plat_pcie->pci; in dw_plat_add_pcie_port()
86 struct dw_pcie_rp *pp = &pci->pp; in dw_plat_add_pcie_port()
87 struct device *dev = &pdev->dev; in dw_plat_add_pcie_port()
90 pp->irq = platform_get_irq(pdev, 1); in dw_plat_add_pcie_port()
91 if (pp->irq < 0) in dw_plat_add_pcie_port()
[all …]
/openbmc/linux/drivers/usb/dwc3/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 tristate "DesignWare USB3 DRD Core Support"
11 USB controller based on the DesignWare USB3 IP Core.
74 Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
78 tristate "PCIe-based Platforms"
82 If you're using the DesignWare Core IP with a PCIe (but not HAPS
86 tristate "Synopsys PCIe-based HAPS Platforms"
90 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
126 STMicroelectronics SoCs with one DesignWare Core USB3 IP
137 Some Qualcomm SoCs use DesignWare Core IP for USB2/3
[all …]
/openbmc/linux/drivers/dma/dw-edma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 tristate "Synopsys DesignWare eDMA controller driver"
9 Support the Synopsys DesignWare eDMA controller, normally
15 tristate "Synopsys DesignWare eDMA PCIe driver"
18 Provides a glue-logic between the Synopsys DesignWare
19 eDMA controller and an endpoint PCIe device. This also serves
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
[all …]
H A Dspear1340.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
16 compatible = "st,spear-spics-gpio";
18 st-spics,peripcfg-reg = <0x42c>;
19 st-spics,sw-enable-bit = <21>;
20 st-spics,cs-value-bit = <20>;
21 st-spics,cs-enable-mask = <3>;
22 st-spics,cs-enable-shift = <18>;
23 gpio-controller;
24 #gpio-cells = <2>;
29 compatible = "st,spear1340-miphy";
[all …]
/openbmc/linux/Documentation/misc-devices/
H A Ddw-xdata-pcie.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Driver for Synopsys DesignWare PCIe traffic generator (also known as xData)
8 Synopsys DesignWare PCIe prototype solution
17 -----------
19 This driver should be used as a host-side (Root Complex) driver and Synopsys
20 DesignWare prototype that includes this IP.
22 The dw-xdata-pcie driver can be used to enable/disable PCIe traffic
24 PCIe link performance analysis.
31 -------
33 Write TLPs traffic generation - Root Complex to Endpoint direction
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dpcie-al.txt1 * Amazon Annapurna Labs PCIe host bridge
3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
5 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
[all …]
H A Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
[all …]
H A Dhisilicon-histb-pcie.txt1 HiSilicon STB PCIe host bridge DT description
3 The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
4 It shares common functions with the DesignWare PCIe core driver and inherits
6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
15 "control": control registers of PCIe controller;
16 "rc-dbi": configuration space of PCIe controller;
[all …]
H A Dlayerscape-pci.txt1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
[all …]
H A Dsocionext,uniphier-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe host controller
10 UniPhier PCIe host controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
[all …]
H A Dsifive,fu740-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive FU740 PCIe host controller
10 SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Paul Walmsley <paul.walmsley@sifive.com>
17 - Greentime Hu <greentime.hu@sifive.com>
[all …]
H A Dti-pci.txt3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
[all …]
H A Drockchip-dw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common properties defined in
[all …]
H A Dhisilicon,kirin-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin SoCs PCIe host DT description
10 - Xiaowei Song <songxiaowei@hisilicon.com>
11 - Binghui Wang <wangbinghui@hisilicon.com>
14 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15 It shares common functions with the PCIe DesignWare core driver and
17 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
[all …]
H A Dspear13xx-pcie.txt1 SPEAr13XX PCIe DT detail:
4 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
8 - compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
9 - phys : phandle to PHY node associated with PCIe controller
10 - phy-names : must be "pcie-phy"
11 - All other definitions as per generic PCI bindings
14 - st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
[all …]
H A Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe endpoint interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
[all …]
H A Daxis,artpec6-pcie.txt1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pci/
H A Darmada8k-pcie.txt1 Armada-8K PCIe DT details:
4 Armada-8k uses synopsis designware PCIe controller.
7 - compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
8 - reg: base addresses and lengths of the pcie control and global control registers.
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
11 - interrupt-map-mask and interrupt-map, standard PCI properties to
12 define the mapping of the PCIe interface to interrupt numbers.
13 - All other definitions as per generic PCI bindings
15 "Documentation/devicetree/bindings/pci/designware-pcie.txt"
18 PHY support is still not supported for armada-8k, once it will, the following parameters can be use…
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Ddesignware.h4 * Designware PCIe IP block emulation
28 #define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
31 #define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
/openbmc/u-boot/drivers/pci/
H A DKconfig16 orgnising devices in U-Boot. For PCI, driver model keeps track of
30 bool "Enable Aardvark PCIe driver"
35 Say Y here if you want to enable PCIe controller support on
36 Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on
47 bool "Enable Aspeed PCIe driver"
51 Say Y here if you want to enable PCIe controller support on
55 bool "Generic ECAM-based PCI host controller support"
59 Say Y here if you want to enable support for generic ECAM-based
60 PCIe host controllers, such as the one emulated by QEMU.
63 bool "Enable Armada-8K PCIe driver (DesignWare core)"
[all …]
/openbmc/qemu/hw/pci-host/
H A Ddesignware.c4 * Designware PCIe IP block emulation
29 #include "hw/qdev-properties.h"
32 #include "hw/pci-host/designware.h"
64 return DESIGNWARE_PCIE_HOST(bus->parent); in designware_pcie_root_to_host()
75 * AHB/AXI bus like any other PCI-device-initiated DMA read. in designware_pcie_root_msi_read()
77 * well-behaved guests won't ever ask a PCI device to DMA from in designware_pcie_root_msi_read()
90 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; in designware_pcie_root_msi_write()
92 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { in designware_pcie_root_msi_write()
93 qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1); in designware_pcie_root_msi_write()
110 MemoryRegion *mem = &root->msi.iomem; in designware_pcie_root_update_msi_mapping()
[all …]

12345