bindings/pci/rockchip-dw-pcie.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe controller on Rockchip SoCs
10   - Shawn Lin <shawn.lin@rock-chips.com>
11   - Simon Xue <xxm@rock-chips.com>
12   - Heiko Stuebner <heiko@sntech.de>
15   RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16   PCIe IP and thus inherits all the common properties defined in
17   snps,dw-pcie.yaml.
20   - $ref: /schemas/pci/snps,dw-pcie.yaml#
25       - const: rockchip,rk3568-pcie
26       - items:
27           - enum:
28               - rockchip,rk3588-pcie
29           - const: rockchip,rk3568-pcie
33       - description: Data Bus Interface (DBI) registers
34       - description: Rockchip designed configuration registers
35       - description: Config registers
37   reg-names:
39       - const: dbi
40       - const: apb
41       - const: config
46       - description: AHB clock for PCIe master
47       - description: AHB clock for PCIe slave
48       - description: AHB clock for PCIe dbi
49       - description: APB clock for PCIe
50       - description: Auxiliary clock for PCIe
51       - description: PIPE clock
53   clock-names:
56       - const: aclk_mst
57       - const: aclk_slv
58       - const: aclk_dbi
59       - const: pclk
60       - const: aux
61       - const: pipe
65       - description:
67           interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
70       - description:
72           interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
75       - description:
77           interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
79       - description:
81           interrupts - inta, intb, intc, intd
82       - description:
84           interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
88   interrupt-names:
90       - const: sys
91       - const: pmc
92       - const: msg
93       - const: legacy
94       - const: err
96   legacy-interrupt-controller:
101       "#address-cells":
104       "#interrupt-cells":
107       interrupt-controller: true
111           - description: combined legacy interrupt
113       - "#address-cells"
114       - "#interrupt-cells"
115       - interrupt-controller
116       - interrupts
118   msi-map: true
120   num-lanes: true
125   phy-names:
126     const: pcie-phy
128   power-domains:
139   reset-names:
141       - const: pipe
142       - items:
143           - const: pwr
144           - const: pipe
146   vpcie3v3-supply: true
149   - compatible
150   - reg
151   - reg-names
152   - clocks
153   - clock-names
154   - msi-map
155   - num-lanes
156   - phys
157   - phy-names
158   - power-domains
159   - resets
160   - reset-names
165   - |
166     #include <dt-bindings/interrupt-controller/arm-gic.h>
169         #address-cells = <2>;
170         #size-cells = <2>;
172         pcie3x2: pcie@fe280000 {
173             compatible = "rockchip,rk3568-pcie";
177             reg-names = "dbi", "apb", "config";
178             bus-range = <0x20 0x2f>;
182             clock-names = "aclk_mst", "aclk_slv",
191             interrupt-names = "sys", "pmc", "msg", "legacy", "err";
192             linux,pci-domain = <2>;
193             max-link-speed = <2>;
194             msi-map = <0x2000 &its 0x2000 0x1000>;
195             num-lanes = <2>;
197             phy-names = "pcie-phy";
198             power-domains = <&power 15>;
202             reset-names = "pipe";
203             #address-cells = <3>;
204             #size-cells = <2>;
206             legacy-interrupt-controller {
207                 interrupt-controller;
208                 #address-cells = <0>;
209                 #interrupt-cells = <1>;
210                 interrupt-parent = <&gic>;