1d9a64c5eSKunihiko Hayashi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2d9a64c5eSKunihiko Hayashi%YAML 1.2 3d9a64c5eSKunihiko Hayashi--- 4d9a64c5eSKunihiko Hayashi$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml# 5d9a64c5eSKunihiko Hayashi$schema: http://devicetree.org/meta-schemas/core.yaml# 6d9a64c5eSKunihiko Hayashi 7d9a64c5eSKunihiko Hayashititle: Socionext UniPhier PCIe host controller 8d9a64c5eSKunihiko Hayashi 9d9a64c5eSKunihiko Hayashidescription: | 10d9a64c5eSKunihiko Hayashi UniPhier PCIe host controller is based on the Synopsys DesignWare 11d9a64c5eSKunihiko Hayashi PCI core. It shares common features with the PCIe DesignWare core and 12d9a64c5eSKunihiko Hayashi inherits common properties defined in 13d9a64c5eSKunihiko Hayashi Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 14d9a64c5eSKunihiko Hayashi 15d9a64c5eSKunihiko Hayashimaintainers: 16d9a64c5eSKunihiko Hayashi - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 17d9a64c5eSKunihiko Hayashi 18d9a64c5eSKunihiko HayashiallOf: 19d9a64c5eSKunihiko Hayashi - $ref: /schemas/pci/snps,dw-pcie.yaml# 20d9a64c5eSKunihiko Hayashi 21d9a64c5eSKunihiko Hayashiproperties: 22d9a64c5eSKunihiko Hayashi compatible: 23d9a64c5eSKunihiko Hayashi enum: 24d9a64c5eSKunihiko Hayashi - socionext,uniphier-pcie 25d9a64c5eSKunihiko Hayashi 26d9a64c5eSKunihiko Hayashi reg: 27d9a64c5eSKunihiko Hayashi minItems: 3 28d9a64c5eSKunihiko Hayashi maxItems: 4 29d9a64c5eSKunihiko Hayashi 30d9a64c5eSKunihiko Hayashi reg-names: 31d9a64c5eSKunihiko Hayashi minItems: 3 32d9a64c5eSKunihiko Hayashi items: 33d9a64c5eSKunihiko Hayashi - const: dbi 34d9a64c5eSKunihiko Hayashi - const: link 35d9a64c5eSKunihiko Hayashi - const: config 36d9a64c5eSKunihiko Hayashi - const: atu 37d9a64c5eSKunihiko Hayashi 38d9a64c5eSKunihiko Hayashi clocks: 39d9a64c5eSKunihiko Hayashi maxItems: 1 40d9a64c5eSKunihiko Hayashi 41d9a64c5eSKunihiko Hayashi resets: 42d9a64c5eSKunihiko Hayashi maxItems: 1 43d9a64c5eSKunihiko Hayashi 44d9a64c5eSKunihiko Hayashi num-viewport: true 45d9a64c5eSKunihiko Hayashi 46d9a64c5eSKunihiko Hayashi num-lanes: true 47d9a64c5eSKunihiko Hayashi 48d9a64c5eSKunihiko Hayashi phys: 49d9a64c5eSKunihiko Hayashi maxItems: 1 50d9a64c5eSKunihiko Hayashi 51d9a64c5eSKunihiko Hayashi phy-names: 52d9a64c5eSKunihiko Hayashi const: pcie-phy 53d9a64c5eSKunihiko Hayashi 54*bcd7ec2cSRob Herring interrupt-controller: 55*bcd7ec2cSRob Herring type: object 56*bcd7ec2cSRob Herring additionalProperties: false 57*bcd7ec2cSRob Herring 58*bcd7ec2cSRob Herring properties: 59*bcd7ec2cSRob Herring interrupt-controller: true 60*bcd7ec2cSRob Herring 61*bcd7ec2cSRob Herring '#interrupt-cells': 62*bcd7ec2cSRob Herring const: 1 63*bcd7ec2cSRob Herring 64*bcd7ec2cSRob Herring interrupts: 65*bcd7ec2cSRob Herring maxItems: 1 66*bcd7ec2cSRob Herring 67d9a64c5eSKunihiko Hayashirequired: 68d9a64c5eSKunihiko Hayashi - compatible 69d9a64c5eSKunihiko Hayashi - reg 70d9a64c5eSKunihiko Hayashi - reg-names 71d9a64c5eSKunihiko Hayashi - clocks 72d9a64c5eSKunihiko Hayashi - resets 73d9a64c5eSKunihiko Hayashi 74d9a64c5eSKunihiko HayashiunevaluatedProperties: false 75d9a64c5eSKunihiko Hayashi 76d9a64c5eSKunihiko Hayashiexamples: 77d9a64c5eSKunihiko Hayashi - | 78*bcd7ec2cSRob Herring bus { 79*bcd7ec2cSRob Herring gic: interrupt-controller { 80*bcd7ec2cSRob Herring interrupt-controller; 81*bcd7ec2cSRob Herring #interrupt-cells = <3>; 82*bcd7ec2cSRob Herring }; 83*bcd7ec2cSRob Herring }; 84*bcd7ec2cSRob Herring 85d9a64c5eSKunihiko Hayashi pcie: pcie@66000000 { 86d9a64c5eSKunihiko Hayashi compatible = "socionext,uniphier-pcie"; 87d9a64c5eSKunihiko Hayashi reg-names = "dbi", "link", "config"; 88d9a64c5eSKunihiko Hayashi reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>; 89d9a64c5eSKunihiko Hayashi #address-cells = <3>; 90d9a64c5eSKunihiko Hayashi #size-cells = <2>; 91d9a64c5eSKunihiko Hayashi clocks = <&sys_clk 24>; 92d9a64c5eSKunihiko Hayashi resets = <&sys_rst 24>; 93d9a64c5eSKunihiko Hayashi num-lanes = <1>; 94d9a64c5eSKunihiko Hayashi num-viewport = <1>; 95d9a64c5eSKunihiko Hayashi bus-range = <0x0 0xff>; 96d9a64c5eSKunihiko Hayashi device_type = "pci"; 97d9a64c5eSKunihiko Hayashi ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 98d9a64c5eSKunihiko Hayashi <0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>; 99d9a64c5eSKunihiko Hayashi phy-names = "pcie-phy"; 100d9a64c5eSKunihiko Hayashi phys = <&pcie_phy>; 101d9a64c5eSKunihiko Hayashi #interrupt-cells = <1>; 102d9a64c5eSKunihiko Hayashi interrupt-names = "dma", "msi"; 103*bcd7ec2cSRob Herring interrupt-parent = <&gic>; 104d9a64c5eSKunihiko Hayashi interrupts = <0 224 4>, <0 225 4>; 105d9a64c5eSKunihiko Hayashi interrupt-map-mask = <0 0 0 7>; 106d9a64c5eSKunihiko Hayashi interrupt-map = <0 0 0 1 &pcie_intc 0>, 107d9a64c5eSKunihiko Hayashi <0 0 0 2 &pcie_intc 1>, 108d9a64c5eSKunihiko Hayashi <0 0 0 3 &pcie_intc 2>, 109d9a64c5eSKunihiko Hayashi <0 0 0 4 &pcie_intc 3>; 110d9a64c5eSKunihiko Hayashi 111*bcd7ec2cSRob Herring pcie_intc: interrupt-controller { 112d9a64c5eSKunihiko Hayashi interrupt-controller; 113d9a64c5eSKunihiko Hayashi #interrupt-cells = <1>; 114d9a64c5eSKunihiko Hayashi interrupt-parent = <&gic>; 115d9a64c5eSKunihiko Hayashi interrupts = <0 226 4>; 116d9a64c5eSKunihiko Hayashi }; 117d9a64c5eSKunihiko Hayashi }; 118