Home
last modified time | relevance | path

Searched full:dclk (Results 1 – 25 of 205) sorted by relevance

123456789

/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon_dclk.c28 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_disable() local
30 regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, in sun4i_dclk_disable()
36 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_enable() local
38 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, in sun4i_dclk_enable()
45 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_is_enabled() local
48 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); in sun4i_dclk_is_enabled()
56 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_recalc_rate() local
59 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); in sun4i_dclk_recalc_rate()
73 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_round_rate() local
74 struct sun4i_tcon *tcon = dclk->tcon; in sun4i_dclk_round_rate()
[all …]
/openbmc/linux/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c49 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_recalc_rate() local
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
55 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in hi6220_clkdiv_recalc_rate()
61 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_round_rate() local
63 return divider_round_rate(hw, rate, prate, dclk->table, in hi6220_clkdiv_round_rate()
64 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in hi6220_clkdiv_round_rate()
73 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_set_rate() local
75 value = divider_get_val(rate, parent_rate, dclk->table, in hi6220_clkdiv_set_rate()
[all …]
/openbmc/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1-divider.c33 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_recalc_rate() local
35 val = readl_relaxed(dclk->reg) >> dclk->shift; in ma35d1_clkdiv_recalc_rate()
36 val &= clk_div_mask(dclk->width); in ma35d1_clkdiv_recalc_rate()
38 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in ma35d1_clkdiv_recalc_rate()
39 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in ma35d1_clkdiv_recalc_rate()
44 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_round_rate() local
46 return divider_round_rate(hw, rate, prate, dclk->table, in ma35d1_clkdiv_round_rate()
47 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_round_rate()
55 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_set_rate() local
57 value = divider_get_val(rate, parent_rate, dclk->table, in ma35d1_clkdiv_set_rate()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dsolomon,ssd1307fb.yaml113 solomon,dclk-div:
120 solomon,dclk-frq:
164 solomon,dclk-div:
166 solomon,dclk-frq:
182 solomon,dclk-div:
184 solomon,dclk-frq:
200 solomon,dclk-div:
202 solomon,dclk-frq:
218 solomon,dclk-div:
220 solomon,dclk-frq:
[all …]
/openbmc/linux/drivers/siox/
H A Dsiox-bus-gpio.c20 struct gpio_desc *dclk; member
38 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
60 gpiod_set_value_cansleep(ddata->dclk, 1); in siox_gpio_pushpull()
62 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
117 ddata->dclk = devm_gpiod_get(dev, "dclk", GPIOD_OUT_LOW); in siox_gpio_probe()
118 if (IS_ERR(ddata->dclk)) { in siox_gpio_probe()
119 ret = dev_err_probe(dev, PTR_ERR(ddata->dclk), in siox_gpio_probe()
120 "Failed to get dclk GPIO\n"); in siox_gpio_probe()
/openbmc/linux/drivers/clk/
H A Dclk-lmk04832.c246 * @dclk: list of internal device clock references.
267 struct lmk_dclk *dclk; member
715 * and dclk
1013 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); in lmk04832_dclk_is_enabled() local
1014 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_is_enabled()
1018 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_is_enabled()
1028 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); in lmk04832_dclk_prepare() local
1029 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_prepare()
1032 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_prepare()
1038 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); in lmk04832_dclk_unprepare() local
[all …]
/openbmc/linux/sound/soc/meson/
H A Daxg-pdm.c94 struct clk *dclk; member
186 /* Max sample counter value per half period of dclk */ in axg_pdm_set_sample_pointer()
188 clk_get_rate(priv->dclk) * 2); in axg_pdm_set_sample_pointer()
253 ret = clk_set_rate(priv->dclk, rate * os); in axg_pdm_hw_params()
255 dev_err(dai->dev, "failed to set dclk\n"); in axg_pdm_hw_params()
276 ret = clk_prepare_enable(priv->dclk); in axg_pdm_startup()
278 dev_err(dai->dev, "enabling dclk failed\n"); in axg_pdm_startup()
294 clk_disable_unprepare(priv->dclk); in axg_pdm_shutdown()
618 priv->dclk = devm_clk_get(dev, "dclk"); in axg_pdm_probe()
619 if (IS_ERR(priv->dclk)) in axg_pdm_probe()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_bw.c22 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; member
53 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); in dg1_mchbar_read_qgv_point_info()
57 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
59 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
80 u16 dclk; in icl_pcode_read_qgv_point_info() local
89 dclk = val & 0xffff; in icl_pcode_read_qgv_point_info()
90 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000); in icl_pcode_read_qgv_point_info()
178 u16 dclk; in mtl_read_qgv_point_info() local
184 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); in mtl_read_qgv_point_info()
185 sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); in mtl_read_qgv_point_info()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/siox/
H A Deckelmann,siox-gpio.txt5 - din-gpios, dout-gpios, dclk-gpios, dld-gpios: references gpios for the
17 dclk-gpios = <&gpio6 9 0>;
/openbmc/linux/drivers/video/fbdev/riva/
H A Dnv_driver.c276 unsigned long dclk = 0; in riva_get_maxdclk() local
286 dclk = 800000; in riva_get_maxdclk()
288 dclk = 1000000; in riva_get_maxdclk()
294 dclk = 1000000; in riva_get_maxdclk()
303 dclk = 800000; in riva_get_maxdclk()
306 dclk = 1000000; in riva_get_maxdclk()
311 return dclk; in riva_get_maxdclk()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drs780_dpm.c571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Damlogic,axg-pdm.yaml37 - const: dclk
81 clock-names = "pclk", "dclk", "sysclk";
/openbmc/u-boot/board/freescale/common/
H A Dics307_clk.c142 in_8(&fpga_reg->dclk[0]), in get_board_ddr_clk()
143 in_8(&fpga_reg->dclk[1]), in get_board_ddr_clk()
144 in_8(&fpga_reg->dclk[2])); in get_board_ddr_clk()
H A Dngpixis.c143 printf("dclk=%02x%02x%02x\n", in pixis_dump_regs()
144 PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2])); in pixis_dump_regs()
H A Dqixis.c186 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), in qixis_dump_regs()
187 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); in qixis_dump_regs()
H A Dpixis.h34 u8 dclk[3]; member
97 u8 dclk[3]; member
/openbmc/linux/drivers/video/fbdev/core/
H A Dfbmon.c546 DPRINTK(" mode exceed max DCLK\n"); in get_std_timing()
770 DPRINTK(" H: %d-%dKHz V: %d-%dHz DCLK: %dMHz\n", in fb_get_monitor_limits()
1017 u32 dclk; member
1087 * @dclk: pixelclock in Hz
1099 * where: h_period = SQRT(100 - C + (0.4 * xres * M)/dclk) + C - 100
1105 static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres) in fb_get_hblank_by_dclk() argument
1109 dclk /= 1000; in fb_get_hblank_by_dclk()
1112 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk); in fb_get_hblank_by_dclk()
1156 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1167 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
[all …]
/openbmc/linux/drivers/fpga/
H A Dsocfpga-a10.c136 /* Issue the DCLK regmap. */ in socfpga_a10_fpga_generate_dclks()
317 /* Set cfg_ctrl to enable s2f dclk and data */ in socfpga_a10_fpga_write_init()
332 /* Enable override for data, dclk, nce, and pr_request to CSS */ in socfpga_a10_fpga_write_init()
408 /* Disable s2f dclk and data */ in socfpga_a10_fpga_write_complete()
417 /* Disable data, dclk, nce, and pr_request override to CSS */ in socfpga_a10_fpga_write_complete()
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7xx-clocks.dtsi353 mpu_dclk_div: clock-mpu-dclk-div {
446 iva_dclk: clock-iva-dclk {
500 core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
567 video2_dclk_div: clock-video2-dclk-div {
576 video1_dclk_div: clock-video1-dclk-div {
585 hdmi_dclk_div: clock-hdmi-dclk-div {
650 eve_dclk_div: clock-eve-dclk-div {
991 sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
1001 sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
1011 per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
[all …]
/openbmc/linux/sound/soc/intel/skylake/
H A Dskl-ssp-clk.c278 static void unregister_src_clk(struct skl_clk_data *dclk) in unregister_src_clk() argument
280 while (dclk->avail_clk_cnt--) in unregister_src_clk()
281 clkdev_drop(dclk->clk[dclk->avail_clk_cnt]->lookup); in unregister_src_clk()
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop.c176 /* vop dclk */
177 struct clk *dclk; member
181 /* vop dclk reset */
619 ret = clk_enable(vop->dclk); in vop_enable()
687 clk_disable(vop->dclk); in vop_enable()
760 clk_disable(vop->dclk); in vop_crtc_atomic_disable()
1226 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); in vop_crtc_mode_fixup()
1228 rate = clk_round_rate(vop->dclk, in vop_crtc_mode_fixup()
1460 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); in vop_crtc_atomic_enable()
2005 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); in vop_initial()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml70 - const: dclk
117 reset-names = "axi", "ahb", "dclk";
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_5_ppsmc.h52 #define PPSMC_MSG_SetSoftMaxVcn 17 ///< Set soft max for VCN clocks (VCLK and DCLK)
59 #define PPSMC_MSG_SetSoftMinVcn 24 ///< Set soft min for VCN clocks (VCLK and DCLK)
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h145 uint32_t DCLK; member
185 unsigned long dclk; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h39 uint32_t dclk; member
120 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk

123456789