xref: /openbmc/linux/drivers/gpu/drm/radeon/rs780_dpm.c (revision d86a4126)
1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 
25 #include <linux/pci.h>
26 #include <linux/seq_file.h>
27 
28 #include "atom.h"
29 #include "r600_dpm.h"
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "rs780_dpm.h"
33 #include "rs780d.h"
34 
rs780_get_ps(struct radeon_ps * rps)35 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
36 {
37 	struct igp_ps *ps = rps->ps_priv;
38 
39 	return ps;
40 }
41 
rs780_get_pi(struct radeon_device * rdev)42 static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev)
43 {
44 	struct igp_power_info *pi = rdev->pm.dpm.priv;
45 
46 	return pi;
47 }
48 
rs780_get_pm_mode_parameters(struct radeon_device * rdev)49 static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
50 {
51 	struct igp_power_info *pi = rs780_get_pi(rdev);
52 	struct radeon_mode_info *minfo = &rdev->mode_info;
53 	struct drm_crtc *crtc;
54 	struct radeon_crtc *radeon_crtc;
55 	int i;
56 
57 	/* defaults */
58 	pi->crtc_id = 0;
59 	pi->refresh_rate = 60;
60 
61 	for (i = 0; i < rdev->num_crtc; i++) {
62 		crtc = (struct drm_crtc *)minfo->crtcs[i];
63 		if (crtc && crtc->enabled) {
64 			radeon_crtc = to_radeon_crtc(crtc);
65 			pi->crtc_id = radeon_crtc->crtc_id;
66 			if (crtc->mode.htotal && crtc->mode.vtotal)
67 				pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);
68 			break;
69 		}
70 	}
71 }
72 
73 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
74 
rs780_initialize_dpm_power_state(struct radeon_device * rdev,struct radeon_ps * boot_ps)75 static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
76 					    struct radeon_ps *boot_ps)
77 {
78 	struct atom_clock_dividers dividers;
79 	struct igp_ps *default_state = rs780_get_ps(boot_ps);
80 	int i, ret;
81 
82 	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
83 					     default_state->sclk_low, false, &dividers);
84 	if (ret)
85 		return ret;
86 
87 	r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
88 	r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
89 	r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
90 
91 	if (dividers.enable_post_div)
92 		r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
93 	else
94 		r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
95 
96 	r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
97 	r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
98 
99 	r600_engine_clock_entry_enable(rdev, 0, true);
100 	for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
101 		r600_engine_clock_entry_enable(rdev, i, false);
102 
103 	r600_enable_mclk_control(rdev, false);
104 	r600_voltage_control_enable_pins(rdev, 0);
105 
106 	return 0;
107 }
108 
rs780_initialize_dpm_parameters(struct radeon_device * rdev,struct radeon_ps * boot_ps)109 static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
110 					   struct radeon_ps *boot_ps)
111 {
112 	int ret = 0;
113 	int i;
114 
115 	r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
116 
117 	r600_set_at(rdev, 0, 0, 0, 0);
118 
119 	r600_set_git(rdev, R600_GICST_DFLT);
120 
121 	for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
122 		r600_set_tc(rdev, i, 0, 0);
123 
124 	r600_select_td(rdev, R600_TD_DFLT);
125 	r600_set_vrc(rdev, 0);
126 
127 	r600_set_tpu(rdev, R600_TPU_DFLT);
128 	r600_set_tpc(rdev, R600_TPC_DFLT);
129 
130 	r600_set_sstu(rdev, R600_SSTU_DFLT);
131 	r600_set_sst(rdev, R600_SST_DFLT);
132 
133 	r600_set_fctu(rdev, R600_FCTU_DFLT);
134 	r600_set_fct(rdev, R600_FCT_DFLT);
135 
136 	r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
137 	r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
138 	r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
139 	r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
140 	r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
141 
142 	r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
143 	r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
144 	r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
145 
146 	ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
147 
148 	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,     0);
149 	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,  0);
150 	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,    0);
151 
152 	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,    0);
153 	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
154 	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,   0);
155 
156 	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,    0);
157 	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
158 	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,   0);
159 
160 	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,    R600_DISPLAY_WATERMARK_HIGH);
161 	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
162 	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,   R600_DISPLAY_WATERMARK_HIGH);
163 
164 	r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
165 	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
166 	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
167 	r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
168 
169 	r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
170 
171 	r600_set_vrc(rdev, RS780_CGFTV_DFLT);
172 
173 	return ret;
174 }
175 
rs780_start_dpm(struct radeon_device * rdev)176 static void rs780_start_dpm(struct radeon_device *rdev)
177 {
178 	r600_enable_sclk_control(rdev, false);
179 	r600_enable_mclk_control(rdev, false);
180 
181 	r600_dynamicpm_enable(rdev, true);
182 
183 	radeon_wait_for_vblank(rdev, 0);
184 	radeon_wait_for_vblank(rdev, 1);
185 
186 	r600_enable_spll_bypass(rdev, true);
187 	r600_wait_for_spll_change(rdev);
188 	r600_enable_spll_bypass(rdev, false);
189 	r600_wait_for_spll_change(rdev);
190 
191 	r600_enable_spll_bypass(rdev, true);
192 	r600_wait_for_spll_change(rdev);
193 	r600_enable_spll_bypass(rdev, false);
194 	r600_wait_for_spll_change(rdev);
195 
196 	r600_enable_sclk_control(rdev, true);
197 }
198 
199 
rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device * rdev)200 static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
201 {
202 	WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
203 		 ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
204 
205 	WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
206 		 RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
207 		 ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
208 }
209 
rs780_preset_starting_fbdiv(struct radeon_device * rdev)210 static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
211 {
212 	u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
213 
214 	WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
215 		 ~STARTING_FEEDBACK_DIV_MASK);
216 
217 	WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
218 		 ~FORCED_FEEDBACK_DIV_MASK);
219 
220 	WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
221 }
222 
rs780_voltage_scaling_init(struct radeon_device * rdev)223 static void rs780_voltage_scaling_init(struct radeon_device *rdev)
224 {
225 	struct igp_power_info *pi = rs780_get_pi(rdev);
226 	u32 fv_throt_pwm_fb_div_range[3];
227 	u32 fv_throt_pwm_range[4];
228 
229 	if (rdev->pdev->device == 0x9614) {
230 		fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
231 		fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
232 		fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
233 	} else if ((rdev->pdev->device == 0x9714) ||
234 		   (rdev->pdev->device == 0x9715)) {
235 		fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
236 		fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
237 		fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
238 	} else {
239 		fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
240 		fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
241 		fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
242 	}
243 
244 	if (pi->pwm_voltage_control) {
245 		fv_throt_pwm_range[0] = pi->min_voltage;
246 		fv_throt_pwm_range[1] = pi->min_voltage;
247 		fv_throt_pwm_range[2] = pi->max_voltage;
248 		fv_throt_pwm_range[3] = pi->max_voltage;
249 	} else {
250 		fv_throt_pwm_range[0] = pi->invert_pwm_required ?
251 			RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
252 		fv_throt_pwm_range[1] = pi->invert_pwm_required ?
253 			RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
254 		fv_throt_pwm_range[2] = pi->invert_pwm_required ?
255 			RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
256 		fv_throt_pwm_range[3] = pi->invert_pwm_required ?
257 			RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
258 	}
259 
260 	WREG32_P(FVTHROT_PWM_CTRL_REG0,
261 		 STARTING_PWM_HIGHTIME(pi->max_voltage),
262 		 ~STARTING_PWM_HIGHTIME_MASK);
263 
264 	WREG32_P(FVTHROT_PWM_CTRL_REG0,
265 		 NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
266 		 ~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
267 
268 	WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
269 		 ~FORCE_STARTING_PWM_HIGHTIME);
270 
271 	if (pi->invert_pwm_required)
272 		WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
273 	else
274 		WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
275 
276 	rs780_voltage_scaling_enable(rdev, true);
277 
278 	WREG32(FVTHROT_PWM_CTRL_REG1,
279 	       (MIN_PWM_HIGHTIME(pi->min_voltage) |
280 		MAX_PWM_HIGHTIME(pi->max_voltage)));
281 
282 	WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
283 	WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
284 	WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
285 	WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
286 
287 	WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
288 		 RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
289 		 ~RANGE0_PWM_FEEDBACK_DIV_MASK);
290 
291 	WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
292 	       (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) |
293 		RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
294 
295 	WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
296 	       (RANGE0_PWM(fv_throt_pwm_range[1]) |
297 		RANGE1_PWM(fv_throt_pwm_range[2])));
298 	WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
299 	       (RANGE2_PWM(fv_throt_pwm_range[1]) |
300 		RANGE3_PWM(fv_throt_pwm_range[2])));
301 }
302 
rs780_clk_scaling_enable(struct radeon_device * rdev,bool enable)303 static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
304 {
305 	if (enable)
306 		WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
307 			 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
308 	else
309 		WREG32_P(FVTHROT_CNTRL_REG, 0,
310 			 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
311 }
312 
rs780_voltage_scaling_enable(struct radeon_device * rdev,bool enable)313 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
314 {
315 	if (enable)
316 		WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
317 	else
318 		WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
319 }
320 
rs780_set_engine_clock_wfc(struct radeon_device * rdev)321 static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
322 {
323 	WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
324 	WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
325 	WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
326 	WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
327 	WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
328 
329 	WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
330 	WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
331 	WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
332 	WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
333 	WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
334 }
335 
rs780_set_engine_clock_sc(struct radeon_device * rdev)336 static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
337 {
338 	WREG32_P(FVTHROT_FBDIV_REG2,
339 		 FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
340 		 ~FB_DIV_TIMER_VAL_MASK);
341 
342 	WREG32_P(FVTHROT_CNTRL_REG,
343 		 REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf),
344 		 ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK));
345 }
346 
rs780_set_engine_clock_tdc(struct radeon_device * rdev)347 static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
348 {
349 	WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
350 }
351 
rs780_set_engine_clock_ssc(struct radeon_device * rdev)352 static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
353 {
354 	WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
355 	WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
356 	WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
357 	WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
358 
359 	WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
360 }
361 
rs780_program_at(struct radeon_device * rdev)362 static void rs780_program_at(struct radeon_device *rdev)
363 {
364 	struct igp_power_info *pi = rs780_get_pi(rdev);
365 
366 	WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
367 	WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
368 	WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
369 	WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
370 	WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
371 }
372 
rs780_disable_vbios_powersaving(struct radeon_device * rdev)373 static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
374 {
375 	WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
376 }
377 
rs780_force_voltage(struct radeon_device * rdev,u16 voltage)378 static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage)
379 {
380 	struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
381 
382 	if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
383 	    (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
384 		return;
385 
386 	WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
387 
388 	udelay(1);
389 
390 	WREG32_P(FVTHROT_PWM_CTRL_REG0,
391 		 STARTING_PWM_HIGHTIME(voltage),
392 		 ~STARTING_PWM_HIGHTIME_MASK);
393 
394 	WREG32_P(FVTHROT_PWM_CTRL_REG0,
395 		 FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
396 
397 	WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
398 		~RANGE_PWM_FEEDBACK_DIV_EN);
399 
400 	udelay(1);
401 
402 	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
403 }
404 
rs780_force_fbdiv(struct radeon_device * rdev,u32 fb_div)405 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)
406 {
407 	struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
408 
409 	if (current_state->sclk_low == current_state->sclk_high)
410 		return;
411 
412 	WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
413 
414 	WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
415 		 ~FORCED_FEEDBACK_DIV_MASK);
416 	WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
417 		 ~STARTING_FEEDBACK_DIV_MASK);
418 	WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
419 
420 	udelay(100);
421 
422 	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
423 }
424 
rs780_set_engine_clock_scaling(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)425 static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
426 					  struct radeon_ps *new_ps,
427 					  struct radeon_ps *old_ps)
428 {
429 	struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
430 	struct igp_ps *new_state = rs780_get_ps(new_ps);
431 	struct igp_ps *old_state = rs780_get_ps(old_ps);
432 	int ret;
433 
434 	if ((new_state->sclk_high == old_state->sclk_high) &&
435 	    (new_state->sclk_low == old_state->sclk_low))
436 		return 0;
437 
438 	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
439 					     new_state->sclk_low, false, &min_dividers);
440 	if (ret)
441 		return ret;
442 
443 	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
444 					     new_state->sclk_high, false, &max_dividers);
445 	if (ret)
446 		return ret;
447 
448 	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
449 					     old_state->sclk_high, false, &current_max_dividers);
450 	if (ret)
451 		return ret;
452 
453 	if ((min_dividers.ref_div != max_dividers.ref_div) ||
454 	    (min_dividers.post_div != max_dividers.post_div) ||
455 	    (max_dividers.ref_div != current_max_dividers.ref_div) ||
456 	    (max_dividers.post_div != current_max_dividers.post_div))
457 		return -EINVAL;
458 
459 	rs780_force_fbdiv(rdev, max_dividers.fb_div);
460 
461 	if (max_dividers.fb_div > min_dividers.fb_div) {
462 		WREG32_P(FVTHROT_FBDIV_REG0,
463 			 MIN_FEEDBACK_DIV(min_dividers.fb_div) |
464 			 MAX_FEEDBACK_DIV(max_dividers.fb_div),
465 			 ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK));
466 
467 		WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
468 	}
469 
470 	return 0;
471 }
472 
rs780_set_engine_clock_spc(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)473 static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
474 				       struct radeon_ps *new_ps,
475 				       struct radeon_ps *old_ps)
476 {
477 	struct igp_ps *new_state = rs780_get_ps(new_ps);
478 	struct igp_ps *old_state = rs780_get_ps(old_ps);
479 	struct igp_power_info *pi = rs780_get_pi(rdev);
480 
481 	if ((new_state->sclk_high == old_state->sclk_high) &&
482 	    (new_state->sclk_low == old_state->sclk_low))
483 		return;
484 
485 	if (pi->crtc_id == 0)
486 		WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
487 	else
488 		WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
489 
490 }
491 
rs780_activate_engine_clk_scaling(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)492 static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
493 					      struct radeon_ps *new_ps,
494 					      struct radeon_ps *old_ps)
495 {
496 	struct igp_ps *new_state = rs780_get_ps(new_ps);
497 	struct igp_ps *old_state = rs780_get_ps(old_ps);
498 
499 	if ((new_state->sclk_high == old_state->sclk_high) &&
500 	    (new_state->sclk_low == old_state->sclk_low))
501 		return;
502 
503 	if (new_state->sclk_high == new_state->sclk_low)
504 		return;
505 
506 	rs780_clk_scaling_enable(rdev, true);
507 }
508 
rs780_get_voltage_for_vddc_level(struct radeon_device * rdev,enum rs780_vddc_level vddc)509 static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
510 					    enum rs780_vddc_level vddc)
511 {
512 	struct igp_power_info *pi = rs780_get_pi(rdev);
513 
514 	if (vddc == RS780_VDDC_LEVEL_HIGH)
515 		return pi->max_voltage;
516 	else if (vddc == RS780_VDDC_LEVEL_LOW)
517 		return pi->min_voltage;
518 	else
519 		return pi->max_voltage;
520 }
521 
rs780_enable_voltage_scaling(struct radeon_device * rdev,struct radeon_ps * new_ps)522 static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
523 					 struct radeon_ps *new_ps)
524 {
525 	struct igp_ps *new_state = rs780_get_ps(new_ps);
526 	struct igp_power_info *pi = rs780_get_pi(rdev);
527 	enum rs780_vddc_level vddc_high, vddc_low;
528 
529 	udelay(100);
530 
531 	if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
532 	    (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
533 		return;
534 
535 	vddc_high = rs780_get_voltage_for_vddc_level(rdev,
536 						     new_state->max_voltage);
537 	vddc_low = rs780_get_voltage_for_vddc_level(rdev,
538 						    new_state->min_voltage);
539 
540 	WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
541 
542 	udelay(1);
543 	if (vddc_high > vddc_low) {
544 		WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
545 			 RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
546 
547 		WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
548 	} else if (vddc_high == vddc_low) {
549 		if (pi->max_voltage != vddc_high) {
550 			WREG32_P(FVTHROT_PWM_CTRL_REG0,
551 				 STARTING_PWM_HIGHTIME(vddc_high),
552 				 ~STARTING_PWM_HIGHTIME_MASK);
553 
554 			WREG32_P(FVTHROT_PWM_CTRL_REG0,
555 				 FORCE_STARTING_PWM_HIGHTIME,
556 				 ~FORCE_STARTING_PWM_HIGHTIME);
557 		}
558 	}
559 
560 	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
561 }
562 
rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)563 static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
564 						     struct radeon_ps *new_ps,
565 						     struct radeon_ps *old_ps)
566 {
567 	struct igp_ps *new_state = rs780_get_ps(new_ps);
568 	struct igp_ps *current_state = rs780_get_ps(old_ps);
569 
570 	if ((new_ps->vclk == old_ps->vclk) &&
571 	    (new_ps->dclk == old_ps->dclk))
572 		return;
573 
574 	if (new_state->sclk_high >= current_state->sclk_high)
575 		return;
576 
577 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
578 }
579 
rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)580 static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
581 						    struct radeon_ps *new_ps,
582 						    struct radeon_ps *old_ps)
583 {
584 	struct igp_ps *new_state = rs780_get_ps(new_ps);
585 	struct igp_ps *current_state = rs780_get_ps(old_ps);
586 
587 	if ((new_ps->vclk == old_ps->vclk) &&
588 	    (new_ps->dclk == old_ps->dclk))
589 		return;
590 
591 	if (new_state->sclk_high < current_state->sclk_high)
592 		return;
593 
594 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
595 }
596 
rs780_dpm_enable(struct radeon_device * rdev)597 int rs780_dpm_enable(struct radeon_device *rdev)
598 {
599 	struct igp_power_info *pi = rs780_get_pi(rdev);
600 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
601 	int ret;
602 
603 	rs780_get_pm_mode_parameters(rdev);
604 	rs780_disable_vbios_powersaving(rdev);
605 
606 	if (r600_dynamicpm_enabled(rdev))
607 		return -EINVAL;
608 	ret = rs780_initialize_dpm_parameters(rdev, boot_ps);
609 	if (ret)
610 		return ret;
611 	rs780_start_dpm(rdev);
612 
613 	rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
614 	rs780_preset_starting_fbdiv(rdev);
615 	if (pi->voltage_control)
616 		rs780_voltage_scaling_init(rdev);
617 	rs780_clk_scaling_enable(rdev, true);
618 	rs780_set_engine_clock_sc(rdev);
619 	rs780_set_engine_clock_wfc(rdev);
620 	rs780_program_at(rdev);
621 	rs780_set_engine_clock_tdc(rdev);
622 	rs780_set_engine_clock_ssc(rdev);
623 
624 	if (pi->gfx_clock_gating)
625 		r600_gfx_clockgating_enable(rdev, true);
626 
627 	return 0;
628 }
629 
rs780_dpm_disable(struct radeon_device * rdev)630 void rs780_dpm_disable(struct radeon_device *rdev)
631 {
632 	struct igp_power_info *pi = rs780_get_pi(rdev);
633 
634 	r600_dynamicpm_enable(rdev, false);
635 
636 	rs780_clk_scaling_enable(rdev, false);
637 	rs780_voltage_scaling_enable(rdev, false);
638 
639 	if (pi->gfx_clock_gating)
640 		r600_gfx_clockgating_enable(rdev, false);
641 
642 	if (rdev->irq.installed &&
643 	    (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
644 		rdev->irq.dpm_thermal = false;
645 		radeon_irq_set(rdev);
646 	}
647 }
648 
rs780_dpm_set_power_state(struct radeon_device * rdev)649 int rs780_dpm_set_power_state(struct radeon_device *rdev)
650 {
651 	struct igp_power_info *pi = rs780_get_pi(rdev);
652 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
653 	struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
654 	int ret;
655 
656 	rs780_get_pm_mode_parameters(rdev);
657 
658 	rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
659 
660 	if (pi->voltage_control) {
661 		rs780_force_voltage(rdev, pi->max_voltage);
662 		mdelay(5);
663 	}
664 
665 	ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps);
666 	if (ret)
667 		return ret;
668 	rs780_set_engine_clock_spc(rdev, new_ps, old_ps);
669 
670 	rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps);
671 
672 	if (pi->voltage_control)
673 		rs780_enable_voltage_scaling(rdev, new_ps);
674 
675 	rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
676 
677 	return 0;
678 }
679 
rs780_dpm_setup_asic(struct radeon_device * rdev)680 void rs780_dpm_setup_asic(struct radeon_device *rdev)
681 {
682 
683 }
684 
rs780_dpm_display_configuration_changed(struct radeon_device * rdev)685 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
686 {
687 	rs780_get_pm_mode_parameters(rdev);
688 	rs780_program_at(rdev);
689 }
690 
691 union igp_info {
692 	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
693 	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
694 };
695 
696 union power_info {
697 	struct _ATOM_POWERPLAY_INFO info;
698 	struct _ATOM_POWERPLAY_INFO_V2 info_2;
699 	struct _ATOM_POWERPLAY_INFO_V3 info_3;
700 	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
701 	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
702 	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
703 };
704 
705 union pplib_clock_info {
706 	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
707 	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
708 	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
709 	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
710 };
711 
712 union pplib_power_state {
713 	struct _ATOM_PPLIB_STATE v1;
714 	struct _ATOM_PPLIB_STATE_V2 v2;
715 };
716 
rs780_parse_pplib_non_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)717 static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
718 					     struct radeon_ps *rps,
719 					     struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
720 					     u8 table_rev)
721 {
722 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
723 	rps->class = le16_to_cpu(non_clock_info->usClassification);
724 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
725 
726 	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
727 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
728 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
729 	} else {
730 		rps->vclk = 0;
731 		rps->dclk = 0;
732 	}
733 
734 	if (r600_is_uvd_state(rps->class, rps->class2)) {
735 		if ((rps->vclk == 0) || (rps->dclk == 0)) {
736 			rps->vclk = RS780_DEFAULT_VCLK_FREQ;
737 			rps->dclk = RS780_DEFAULT_DCLK_FREQ;
738 		}
739 	}
740 
741 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
742 		rdev->pm.dpm.boot_ps = rps;
743 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
744 		rdev->pm.dpm.uvd_ps = rps;
745 }
746 
rs780_parse_pplib_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,union pplib_clock_info * clock_info)747 static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
748 					 struct radeon_ps *rps,
749 					 union pplib_clock_info *clock_info)
750 {
751 	struct igp_ps *ps = rs780_get_ps(rps);
752 	u32 sclk;
753 
754 	sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
755 	sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
756 	ps->sclk_low = sclk;
757 	sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
758 	sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
759 	ps->sclk_high = sclk;
760 	switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
761 	case ATOM_PPLIB_RS780_VOLTAGE_NONE:
762 	default:
763 		ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
764 		ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
765 		break;
766 	case ATOM_PPLIB_RS780_VOLTAGE_LOW:
767 		ps->min_voltage = RS780_VDDC_LEVEL_LOW;
768 		ps->max_voltage = RS780_VDDC_LEVEL_LOW;
769 		break;
770 	case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
771 		ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
772 		ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
773 		break;
774 	case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
775 		ps->min_voltage = RS780_VDDC_LEVEL_LOW;
776 		ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
777 		break;
778 	}
779 	ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
780 
781 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
782 		ps->sclk_low = rdev->clock.default_sclk;
783 		ps->sclk_high = rdev->clock.default_sclk;
784 		ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
785 		ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
786 	}
787 }
788 
rs780_parse_power_table(struct radeon_device * rdev)789 static int rs780_parse_power_table(struct radeon_device *rdev)
790 {
791 	struct radeon_mode_info *mode_info = &rdev->mode_info;
792 	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
793 	union pplib_power_state *power_state;
794 	int i;
795 	union pplib_clock_info *clock_info;
796 	union power_info *power_info;
797 	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
798 	u16 data_offset;
799 	u8 frev, crev;
800 	struct igp_ps *ps;
801 
802 	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
803 				   &frev, &crev, &data_offset))
804 		return -EINVAL;
805 	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
806 
807 	rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
808 				  sizeof(struct radeon_ps),
809 				  GFP_KERNEL);
810 	if (!rdev->pm.dpm.ps)
811 		return -ENOMEM;
812 
813 	for (i = 0; i < power_info->pplib.ucNumStates; i++) {
814 		power_state = (union pplib_power_state *)
815 			(mode_info->atom_context->bios + data_offset +
816 			 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
817 			 i * power_info->pplib.ucStateEntrySize);
818 		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
819 			(mode_info->atom_context->bios + data_offset +
820 			 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
821 			 (power_state->v1.ucNonClockStateIndex *
822 			  power_info->pplib.ucNonClockSize));
823 		if (power_info->pplib.ucStateEntrySize - 1) {
824 			clock_info = (union pplib_clock_info *)
825 				(mode_info->atom_context->bios + data_offset +
826 				 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
827 				 (power_state->v1.ucClockStateIndices[0] *
828 				  power_info->pplib.ucClockInfoSize));
829 			ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
830 			if (ps == NULL) {
831 				kfree(rdev->pm.dpm.ps);
832 				return -ENOMEM;
833 			}
834 			rdev->pm.dpm.ps[i].ps_priv = ps;
835 			rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
836 							 non_clock_info,
837 							 power_info->pplib.ucNonClockSize);
838 			rs780_parse_pplib_clock_info(rdev,
839 						     &rdev->pm.dpm.ps[i],
840 						     clock_info);
841 		}
842 	}
843 	rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
844 	return 0;
845 }
846 
rs780_dpm_init(struct radeon_device * rdev)847 int rs780_dpm_init(struct radeon_device *rdev)
848 {
849 	struct igp_power_info *pi;
850 	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
851 	union igp_info *info;
852 	u16 data_offset;
853 	u8 frev, crev;
854 	int ret;
855 
856 	pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
857 	if (pi == NULL)
858 		return -ENOMEM;
859 	rdev->pm.dpm.priv = pi;
860 
861 	ret = r600_get_platform_caps(rdev);
862 	if (ret)
863 		return ret;
864 
865 	ret = rs780_parse_power_table(rdev);
866 	if (ret)
867 		return ret;
868 
869 	pi->voltage_control = false;
870 	pi->gfx_clock_gating = true;
871 
872 	if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
873 				   &frev, &crev, &data_offset)) {
874 		info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
875 
876 		/* Get various system informations from bios */
877 		switch (crev) {
878 		case 1:
879 			pi->num_of_cycles_in_period =
880 				info->info.ucNumberOfCyclesInPeriod;
881 			pi->num_of_cycles_in_period |=
882 				info->info.ucNumberOfCyclesInPeriodHi << 8;
883 			pi->invert_pwm_required =
884 				(pi->num_of_cycles_in_period & 0x8000) ? true : false;
885 			pi->boot_voltage = info->info.ucStartingPWM_HighTime;
886 			pi->max_voltage = info->info.ucMaxNBVoltage;
887 			pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;
888 			pi->min_voltage = info->info.ucMinNBVoltage;
889 			pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;
890 			pi->inter_voltage_low =
891 				le16_to_cpu(info->info.usInterNBVoltageLow);
892 			pi->inter_voltage_high =
893 				le16_to_cpu(info->info.usInterNBVoltageHigh);
894 			pi->voltage_control = true;
895 			pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
896 			break;
897 		case 2:
898 			pi->num_of_cycles_in_period =
899 				le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
900 			pi->invert_pwm_required =
901 				(pi->num_of_cycles_in_period & 0x8000) ? true : false;
902 			pi->boot_voltage =
903 				le16_to_cpu(info->info_2.usBootUpNBVoltage);
904 			pi->max_voltage =
905 				le16_to_cpu(info->info_2.usMaxNBVoltage);
906 			pi->min_voltage =
907 				le16_to_cpu(info->info_2.usMinNBVoltage);
908 			pi->system_config =
909 				le32_to_cpu(info->info_2.ulSystemConfig);
910 			pi->pwm_voltage_control =
911 				(pi->system_config & 0x4) ? true : false;
912 			pi->voltage_control = true;
913 			pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
914 			break;
915 		default:
916 			DRM_ERROR("No integrated system info for your GPU\n");
917 			return -EINVAL;
918 		}
919 		if (pi->min_voltage > pi->max_voltage)
920 			pi->voltage_control = false;
921 		if (pi->pwm_voltage_control) {
922 			if ((pi->num_of_cycles_in_period == 0) ||
923 			    (pi->max_voltage == 0) ||
924 			    (pi->min_voltage == 0))
925 				pi->voltage_control = false;
926 		} else {
927 			if ((pi->num_of_cycles_in_period == 0) ||
928 			    (pi->max_voltage == 0))
929 				pi->voltage_control = false;
930 		}
931 
932 		return 0;
933 	}
934 	radeon_dpm_fini(rdev);
935 	return -EINVAL;
936 }
937 
rs780_dpm_print_power_state(struct radeon_device * rdev,struct radeon_ps * rps)938 void rs780_dpm_print_power_state(struct radeon_device *rdev,
939 				 struct radeon_ps *rps)
940 {
941 	struct igp_ps *ps = rs780_get_ps(rps);
942 
943 	r600_dpm_print_class_info(rps->class, rps->class2);
944 	r600_dpm_print_cap_info(rps->caps);
945 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
946 	printk("\t\tpower level 0    sclk: %u vddc_index: %d\n",
947 	       ps->sclk_low, ps->min_voltage);
948 	printk("\t\tpower level 1    sclk: %u vddc_index: %d\n",
949 	       ps->sclk_high, ps->max_voltage);
950 	r600_dpm_print_ps_status(rdev, rps);
951 }
952 
rs780_dpm_fini(struct radeon_device * rdev)953 void rs780_dpm_fini(struct radeon_device *rdev)
954 {
955 	int i;
956 
957 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
958 		kfree(rdev->pm.dpm.ps[i].ps_priv);
959 	}
960 	kfree(rdev->pm.dpm.ps);
961 	kfree(rdev->pm.dpm.priv);
962 }
963 
rs780_dpm_get_sclk(struct radeon_device * rdev,bool low)964 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
965 {
966 	struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
967 
968 	if (low)
969 		return requested_state->sclk_low;
970 	else
971 		return requested_state->sclk_high;
972 }
973 
rs780_dpm_get_mclk(struct radeon_device * rdev,bool low)974 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
975 {
976 	struct igp_power_info *pi = rs780_get_pi(rdev);
977 
978 	return pi->bootup_uma_clk;
979 }
980 
rs780_dpm_debugfs_print_current_performance_level(struct radeon_device * rdev,struct seq_file * m)981 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
982 						       struct seq_file *m)
983 {
984 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;
985 	struct igp_ps *ps = rs780_get_ps(rps);
986 	u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
987 	u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
988 	u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
989 	u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
990 		((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
991 	u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
992 		(post_div * ref_div);
993 
994 	seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
995 
996 	/* guess based on the current sclk */
997 	if (sclk < (ps->sclk_low + 500))
998 		seq_printf(m, "power level 0    sclk: %u vddc_index: %d\n",
999 			   ps->sclk_low, ps->min_voltage);
1000 	else
1001 		seq_printf(m, "power level 1    sclk: %u vddc_index: %d\n",
1002 			   ps->sclk_high, ps->max_voltage);
1003 }
1004 
1005 /* get the current sclk in 10 khz units */
rs780_dpm_get_current_sclk(struct radeon_device * rdev)1006 u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev)
1007 {
1008 	u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
1009 	u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1010 	u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
1011 	u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
1012 		((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
1013 	u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
1014 		(post_div * ref_div);
1015 
1016 	return sclk;
1017 }
1018 
1019 /* get the current mclk in 10 khz units */
rs780_dpm_get_current_mclk(struct radeon_device * rdev)1020 u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev)
1021 {
1022 	struct igp_power_info *pi = rs780_get_pi(rdev);
1023 
1024 	return pi->bootup_uma_clk;
1025 }
1026 
rs780_dpm_force_performance_level(struct radeon_device * rdev,enum radeon_dpm_forced_level level)1027 int rs780_dpm_force_performance_level(struct radeon_device *rdev,
1028 				      enum radeon_dpm_forced_level level)
1029 {
1030 	struct igp_power_info *pi = rs780_get_pi(rdev);
1031 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1032 	struct igp_ps *ps = rs780_get_ps(rps);
1033 	struct atom_clock_dividers dividers;
1034 	int ret;
1035 
1036 	rs780_clk_scaling_enable(rdev, false);
1037 	rs780_voltage_scaling_enable(rdev, false);
1038 
1039 	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1040 		if (pi->voltage_control)
1041 			rs780_force_voltage(rdev, pi->max_voltage);
1042 
1043 		ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1044 						     ps->sclk_high, false, &dividers);
1045 		if (ret)
1046 			return ret;
1047 
1048 		rs780_force_fbdiv(rdev, dividers.fb_div);
1049 	} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1050 		ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1051 						     ps->sclk_low, false, &dividers);
1052 		if (ret)
1053 			return ret;
1054 
1055 		rs780_force_fbdiv(rdev, dividers.fb_div);
1056 
1057 		if (pi->voltage_control)
1058 			rs780_force_voltage(rdev, pi->min_voltage);
1059 	} else {
1060 		if (pi->voltage_control)
1061 			rs780_force_voltage(rdev, pi->max_voltage);
1062 
1063 		if (ps->sclk_high != ps->sclk_low) {
1064 			WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
1065 			rs780_clk_scaling_enable(rdev, true);
1066 		}
1067 
1068 		if (pi->voltage_control) {
1069 			rs780_voltage_scaling_enable(rdev, true);
1070 			rs780_enable_voltage_scaling(rdev, rps);
1071 		}
1072 	}
1073 
1074 	rdev->pm.dpm.forced_level = level;
1075 
1076 	return 0;
1077 }
1078