| /openbmc/linux/arch/alpha/lib/ |
| H A D | ev6-csum_ipv6_magic.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
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| /openbmc/linux/include/linux/ |
| H A D | timecounter.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CYCLECOUNTER_MASK(bits) (u64)((bits) < 64 ? ((1ULL<<(bits))-1) : -1)
17 * struct cyclecounter - hardware abstraction for a free running counter
18 * Provides completely state-free accessors to the underlying hardware.
19 * Depending on which hardware it reads, the cycle counter may wrap
23 * @read: returns the current cycle value
27 * @mult: cycle to nanosecond multiplier
28 * @shift: cycle to nanosecond divisor (power of two)
38 * struct timecounter - layer above a %struct cyclecounter which counts nanoseconds
40 * cycle counter wrap around. Initialize with
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | floating-point.json | 5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | dme1737.rst | 18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
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| H A D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
50 capabilities. It monitors 2 dedicated temperature sensor inputs (temp1 and
51 temp2), 1 dedicated voltage (in5) and 2 fans. Additionally, the chip
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
[all …]
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| H A D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
37 * vccp_limit_type: integer array (2)
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
[all …]
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| /openbmc/openbmc/meta-facebook/meta-minerva/recipes-phosphor/state/phosphor-state-manager/ |
| H A D | chassis-powercycle | 3 # shellcheck source=meta-facebook/meta-minerva/recipes-minerva/plat-tool/files/minerva-common-funct…
4 source /usr/libexec/minerva-common-functions
6 # Minerva CMM Sled Power Cycle and Chassis Power Cycle
8 cmm-hsc-power-cycle() {
12 # [2:0]
13 …# RBT_DL 100 Configures Auto-Reboot turn-on Delay (tDL(RBT)) after the REBOOT bit is set to 1
14 # RBT_DL[2:0] DELAY
23 ret1=$(i2cset -y -f 0 0x44 0xfd 0x00)
24 ret2=$(i2cset -y -f 0 0x44 0xfd 0x0b)
27 ret3=$(i2cset -f -y 0 0x43 0xec)
[all …]
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| /openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/ |
| H A D | chassis-powercycle | 3 # shellcheck source=meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/power-cmd
4 source /usr/libexec/phosphor-state-manager/power-cmd
6 #Sled cycle
[all...] |
| /openbmc/linux/drivers/staging/vme_user/ |
| H A D | vme_fake.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
49 u32 cycle; member
57 u32 cycle; member
99 bridge = fake_bridge->driver_priv; in fake_VIRQ_tasklet()
101 vme_irq_handler(fake_bridge, bridge->int_level, bridge->int_statid); in fake_VIRQ_tasklet()
132 bridge = fake_bridge->driver_priv; in fake_irq_generate()
134 mutex_lock(&bridge->vme_int); in fake_irq_generate()
136 bridge->int_level = level; in fake_irq_generate()
138 bridge->int_statid = statid; in fake_irq_generate()
144 tasklet_schedule(&bridge->int_tasklet); in fake_irq_generate()
[all …]
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| H A D | vme_tsi148.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for the Tundra TSI148 VME-PCI Bridge Chip
20 #include <linux/dma-mapping.h>
80 wake_up(&bridge->dma_queue[0]); in tsi148_DMA_irqhandler()
84 wake_up(&bridge->dma_queue[1]); in tsi148_DMA_irqhandler()
102 bridge->lm_callback[i](bridge->lm_data[i]); in tsi148_LM_irqhandler()
122 bridge = tsi148_bridge->driver_priv; in tsi148_MB_irqhandler()
126 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); in tsi148_MB_irqhandler()
127 dev_err(tsi148_bridge->parent, "VME Mailbox %d received: 0x%x\n", in tsi148_MB_irqhandler()
143 bridge = tsi148_bridge->driver_priv; in tsi148_PERR_irqhandler()
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | floating-point.json | 6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th…
19 "BriefDescription": "Total number uOps assigned to pipe 2.",
20 …- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric o…
27 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num…
52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
[all …]
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| /openbmc/linux/drivers/ata/ |
| H A D | libata-pata-timings.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2004 Jeff Garzik
15 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
18 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
19 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
57 #define ENOUGH(v, unit) (((v)-1)/(unit)+1)
63 q->setup = EZ(t->setup, T); in ata_timing_quantize()
64 q->act8b = EZ(t->act8b, T); in ata_timing_quantize()
65 q->rec8b = EZ(t->rec8b, T); in ata_timing_quantize()
[all …]
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| /openbmc/u-boot/board/d-link/dns325/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
36 # bit4: 0, addr/cmd in smame cycle
[all …]
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| /openbmc/u-boot/board/buffalo/lsxl/ |
| H A D | kwbimage-lschl.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
38 # bit4: 0, addr/cmd in same cycle
41 # bit11-7: 0 required
[all …]
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| H A D | kwbimage-lsxhl.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
[all …]
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| /openbmc/linux/kernel/locking/ |
| H A D | test-ww_mutex.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Module-based API test facility for ww_mutexes
22 (a)->deadlock_inject_countdown = ~0U; \
37 #define TEST_MTX_CTX BIT(2)
44 complete(&mtx->ready); in test_mutex_work()
45 wait_for_completion(&mtx->go); in test_mutex_work()
47 if (mtx->flags & TEST_MTX_TRY) { in test_mutex_work()
48 while (!ww_mutex_trylock(&mtx->mutex, NULL)) in test_mutex_work()
51 ww_mutex_lock(&mtx->mutex, NULL); in test_mutex_work()
53 complete(&mtx->done); in test_mutex_work()
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| /openbmc/linux/drivers/pwm/ |
| H A D | pwm-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
7 * with the old duty cycle and the new period. This is because the counters
9 * automatically reloaded at the end of a cycle. If this automatic reload
11 * bad cycle. This could probably be fixed by reading TCR0 just before
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
14 * possible by stopping the counters at an appropriate point in the cycle,
16 * - Only produces "normal" output.
17 * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
[all …]
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| /openbmc/openbmc/meta-facebook/meta-ventura/recipes-phosphor/state/phosphor-state-manager/ |
| H A D | chassis-powercycle | 3 # Ventura RMC Sled Power Cycle
5 rmc-hsc-power-cycle() {
9 # [2:0]
10 …# RBT_DL 100 Configures Auto-Reboot turn-on Delay (tDL(RBT)) after the REBOOT bit is set to 1
11 # RBT_DL[2:0] DELAY
20 ret1=$(i2cget -y -f 10 0x44)
21 ret2=$(i2cget -y -f 10 0x14)
23 if [[ "$ret1" =~ ^0x[0-9A-Fa-f]+$ ]]; then
25 i2cset -y -f 10 0x44 0xfd 0x00
26 i2cset -y -f 10 0x44 0xfd 0x0b
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | renesas,sh-msiof.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/input/ |
| H A D | pwm-vibrator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/pwm-vibrator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
23 const: pwm-vibrator
25 pwm-names:
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/regulator/ |
| H A D | pwm-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
15 Currently supports 2 modes of operation:
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
[all …]
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| /openbmc/linux/include/linux/mfd/ |
| H A D | rz-mtu3.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
34 #define RZ_MTU3_TSR 2 /* Timer status register */
36 #define RZ_MTU3_TCR2 4 /* Timer control register 2 */
[all …]
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| /openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/ |
| H A D | chassis-powercycle | 6 # shellcheck source=meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/powe…
7 source /usr/libexec/phosphor-state-manager/power-cmd
8 # shellcheck source=meta-facebook/meta-yosemite4/recipes-yosemite4/plat-tool/files/yosemite4-common…
9 source /usr/libexec/yosemite4-common-functions
14 IO_EXP_SLOT_PWR_STATUS=$((CHASSIS_ID - 1))
21 if [ -z "$MANAGEMENT_BOARD_VERSION" ]; then
22 echo "Failed to check management board fru info, sled cycle keep default setting"
25 GPIOCHIP_IO_EXP_SLOT_PWR_CTRL=$(basename "/sys/bus/i2c/devices/$SPIDER_BOARD_IO_EXP_BUS_NUM-00$IO_E…
26 GPIOCHIP_IO_EXP_SLED_PWR_CTRL=$(basename "/sys/bus/i2c/devices/$MANAGEMENT_BOARD_IO_EXP_BUS_NUM-00$…
27 #GPIOCHIP_IO_EXP_BIC_PWR_CTRL=$(basename "/sys/bus/i2c/devices/$IO_EXP_SLOT_PWR_STATUS-00$IO_EXP_BI…
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | mvebu-devbus.txt | 9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | pipeline.json | 79 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
147 …ed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
154 …ed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
243 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
265 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
279 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
294 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by …
300 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
307 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
314 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
[all …]
|