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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-dhcom-drc02.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 stdout-path = "serial0:115200n8";
13 * Special SoM hardware required which uses the pins from micro SD card. The
14 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
16 * card must be disabled and the uart1 rts/cts must be output on other DHCOM
17 * pins, see uart1 and usdhc3 node below.
30 rs485-rx-en-hog {
31 gpio-hog;
33 line-name = "rs485-rx-en";
[all …]
H A Dimx6ul-ccimx6ulsbcpro.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
13 #include "imx6ul-ccimx6ulsom.dtsi"
20 compatible = "pwm-backlight";
22 brightness-levels = <0 4 8 16 32 64 128 255>;
23 default-brightness-level = <6>;
29 power-supply = <&ldo4_ext>;
34 remote-endpoint = <&display_out>;
[all …]
H A Dimx6ull-dhcom-drc02.dts1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
7 * DHCOR PCB number: 578-200 or newer
8 * DHCOM PCB number: 579-200 or newer
9 * DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM)
11 /dts-v1/;
13 #include "imx6ull-dhcom-som.dtsi"
14 #include "imx6ull-dhcom-som-cfg-sdcard.dtsi"
18 compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som",
19 "dh,imx6ull-dhcor-som", "fsl,imx6ull";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
16 name pins functions
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
23 uart1(cts), lcd-spi(cs1), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
[all …]
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
16 Available mpp pins/groups and functions:
22 name pins functions
34 mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
[all …]
H A Dmarvell,armada-370-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
20 mpp4 4 gpio, vdd(cpu-pd)
26 mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
48 mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
59 mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
73 mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
[all …]
H A Dmarvell,armada-xp-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
19 name pins functions
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
61 mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0),
63 mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
65 mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer)
[all …]
H A Dmarvell,armada-38x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
23 mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts)
37 mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts)
42 mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
57 mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
[all …]
H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio)
37 mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda)
43 mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
58 mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2)
[all …]
H A Dimg,pistachio-pinctrl.txt6 controller on Pistachio has 99 pins, 90 of which are MFIOs which can be
8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
17 - reg: Address range of the pinctrl registers.
19 Required properties for GPIO bank sub-nodes:
20 --------------------------------------------
21 - interrupts: Interrupt line for the GPIO bank.
[all …]
H A Dlantiq,pinctrl-xway.txt4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
19 pin, a group, or a list of pins or groups. This configuration can include the
21 pull-up and open-drain
36 Required subnode-properties:
37 - lantiq,groups : An array of strings. Each string contains the name of a group.
39 - lantiq,function: A string containing the name of the function to mux to the
57 spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
69 spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
[all …]
H A Dmarvell,orion-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
16 Available mpp pins/groups and functions:
22 name pins functions
26 mpp2 2 gpio, pci(req3), pci-1(pme)
30 mpp6 6 gpio, pci(req5), pci-1(clk)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
32 the UART's CTS line.
34 dcd-gpios:
40 dsr-gpios:
[all …]
H A Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
34 st,hw-flow-ctrl:
38 rx-tx-swap: true
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192-asurada-hayato-r1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
6 #include "mt8192-asurada.dtsi"
7 #include "mt8192-asurada-audio-rt1015p-rt5682.dtsi"
11 compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";
15 function-row-physmap = <
44 bt_pins: bt-pins {
45 pins-bt-kill {
47 output-low;
50 pins-bt-wake {
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-dbx5x0-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "ste-nomadik-pinctrl.dtsi"
17 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
21 pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
28 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
32 pins = "GPIO1_AJ3"; /* RTS */
36 pins = "GPIO3_AH3"; /* TXD */
49 pins = "GPIO4_AH6"; /* RXD */
53 pins = "GPIO5_AG6"; /* TXD */
60 pins = "GPIO4_AH6"; /* RXD */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3188.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 enable-method = "rockchip,rk3066-smp";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
25 operating-points = <
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
13 interrupt-parent = <&gic>;
32 arm-pmu {
33 compatible = "arm,cortex-a7-pmu";
36 interrupt-affinity = <&cpu0>, <&cpu1>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-hummingboard-pulse.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
6 /dts-v1/;
8 #include "dt-bindings/usb/pd.h"
9 #include "imx8mq-sr-som.dtsi"
13 compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq";
16 stdout-path = &uart1;
19 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
20 compatible = "regulator-fixed";
21 pinctrl-names = "default";
[all …]
H A Dimx8mm-venice-gw73xx-0x-rs232-rts.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * GW73xx RS232 with RTS/CTS hardware flow control:
6 * - GPIO4_0 rs485_en needs to be driven low (in-active)
7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 compatible = "gw,imx8mm-gw73xx-0x";
24 gpio-hog;
[all …]
H A Dimx8mm-venice-gw72xx-0x-rs232-rts.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * GW72xx RS232 with RTS/CTS hardware flow control:
6 * - GPIO4_0 rs485_en needs to be driven low (in-active)
7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 compatible = "gw,imx8mm-gw72xx-0x";
24 gpio-hog;
[all …]
H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
27 stdout-path = &uart2;
36 compatible = "fixed-clock";
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-netcom-plus-2xx.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
13 #include "am335x-baltos.dtsi"
14 #include "am335x-baltos-leds.dtsi"
21 uart1_pins: uart1-pins {
22 pinctrl-single,pins = <
25 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */
34 uart2_pins: uart2-pins {
35 pinctrl-single,pins = <
[all …]
/openbmc/u-boot/board/silica/pengwyn/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0+
15 /* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
19 {-1},
22 /* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
24 /* I2C pins C16(scl)/C17(sda) */
30 {-1},
33 /* MMC0 pins */
42 {-1},
45 /* MII pins */
62 {-1},
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-artpec6.c2 * Driver for the Axis ARTPEC-6 pin controller
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 #define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */
59 struct pinctrl_pin_desc *pins; member
69 const unsigned int *pins; member
80 /* pins */
215 .pins = cpuclkout_pins0,
221 .pins = udlclkout_pins0,
227 .pins = i2c1_pins0,
[all …]

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