Lines Matching +full:cts +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 enable-method = "rockchip,rk3066-smp";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
25 operating-points = <
36 clock-latency = <40000>;
41 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
53 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
60 compatible = "mmio-sram";
62 #address-cells = <1>;
63 #size-cells = <1>;
66 smp-sram@0 {
67 compatible = "rockchip,rk3066-smp-sram";
73 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
76 #address-cells = <1>;
77 #size-cells = <0>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&i2s0_bus>;
81 dma-names = "tx", "rx";
82 clock-names = "i2s_hclk", "i2s_clk";
84 rockchip,playback-channels = <2>;
85 rockchip,capture-channels = <2>;
90 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
92 #sound-dai-cells = <0>;
93 clock-names = "hclk", "mclk";
96 dma-names = "tx";
98 pinctrl-names = "default";
99 pinctrl-0 = <&spdif_tx>;
103 cru: clock-controller@20000000 {
104 compatible = "rockchip,rk3188-cru";
108 #clock-cells = <1>;
109 #reset-cells = <1>;
113 compatible = "rockchip,rockchip-efuse";
115 #address-cells = <1>;
116 #size-cells = <1>;
118 clock-names = "pclk_efuse";
126 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
132 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
134 #address-cells = <1>;
135 #size-cells = <0>;
138 usbphy0: usb-phy@10c {
139 #phy-cells = <0>;
142 clock-names = "phyclk";
143 #clock-cells = <0>;
146 usbphy1: usb-phy@11c {
147 #phy-cells = <0>;
150 clock-names = "phyclk";
151 #clock-cells = <0>;
156 compatible = "rockchip,rk3188-pinctrl";
160 #address-cells = <1>;
161 #size-cells = <1>;
165 compatible = "rockchip,gpio-bank";
170 gpio-controller;
171 #gpio-cells = <2>;
173 interrupt-controller;
174 #interrupt-cells = <2>;
178 compatible = "rockchip,gpio-bank";
183 gpio-controller;
184 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
191 compatible = "rockchip,gpio-bank";
196 gpio-controller;
197 #gpio-cells = <2>;
199 interrupt-controller;
200 #interrupt-cells = <2>;
204 compatible = "rockchip,gpio-bank";
209 gpio-controller;
210 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
217 bias-pull-up;
221 bias-pull-down;
225 bias-disable;
229 emmc_clk: emmc-clk {
230 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
233 emmc_cmd: emmc-cmd {
234 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
237 emmc_rst: emmc-rst {
238 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
242 * The data pins are shared between nandc and emmc and
245 * flash/emmc is the boot-device.
250 emac_xfer: emac-xfer {
251 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
261 emac_mdio: emac-mdio {
262 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
268 i2c0_xfer: i2c0-xfer {
269 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
275 i2c1_xfer: i2c1-xfer {
276 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
282 i2c2_xfer: i2c2-xfer {
283 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
289 i2c3_xfer: i2c3-xfer {
290 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
296 i2c4_xfer: i2c4-xfer {
297 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
303 pwm0_out: pwm0-out {
304 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
309 pwm1_out: pwm1-out {
310 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
315 pwm2_out: pwm2-out {
316 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
321 pwm3_out: pwm3-out {
322 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
327 spi0_clk: spi0-clk {
328 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
330 spi0_cs0: spi0-cs0 {
331 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
333 spi0_tx: spi0-tx {
334 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
336 spi0_rx: spi0-rx {
337 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
339 spi0_cs1: spi0-cs1 {
340 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
345 spi1_clk: spi1-clk {
346 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
348 spi1_cs0: spi1-cs0 {
349 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
351 spi1_rx: spi1-rx {
352 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
354 spi1_tx: spi1-tx {
355 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
357 spi1_cs1: spi1-cs1 {
358 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
363 uart0_xfer: uart0-xfer {
364 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
368 uart0_cts: uart0-cts {
369 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
372 uart0_rts: uart0-rts {
373 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
378 uart1_xfer: uart1-xfer {
379 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
383 uart1_cts: uart1-cts {
384 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
387 uart1_rts: uart1-rts {
388 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
393 uart2_xfer: uart2-xfer {
394 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
397 /* no rts / cts for uart2 */
401 uart3_xfer: uart3-xfer {
402 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
406 uart3_cts: uart3-cts {
407 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
410 uart3_rts: uart3-rts {
411 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
416 sd0_clk: sd0-clk {
417 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
420 sd0_cmd: sd0-cmd {
421 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
424 sd0_cd: sd0-cd {
425 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
428 sd0_wp: sd0-wp {
429 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
432 sd0_pwr: sd0-pwr {
433 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
436 sd0_bus1: sd0-bus-width1 {
437 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
440 sd0_bus4: sd0-bus-width4 {
441 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
449 sd1_clk: sd1-clk {
450 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
453 sd1_cmd: sd1-cmd {
454 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
457 sd1_cd: sd1-cd {
458 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
461 sd1_wp: sd1-wp {
462 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
465 sd1_bus1: sd1-bus-width1 {
466 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
469 sd1_bus4: sd1-bus-width4 {
470 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
478 i2s0_bus: i2s0-bus {
479 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
489 spdif_tx: spdif-tx {
490 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
497 compatible = "rockchip,rk3188-emac";
505 compatible = "rockchip,rk3188-grf", "syscon";
513 compatible = "rockchip,rk3188-i2c";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c0_xfer>;
519 compatible = "rockchip,rk3188-i2c";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c1_xfer>;
525 compatible = "rockchip,rk3188-i2c";
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c2_xfer>;
531 compatible = "rockchip,rk3188-i2c";
532 pinctrl-names = "default";
533 pinctrl-0 = <&i2c3_xfer>;
537 compatible = "rockchip,rk3188-i2c";
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c4_xfer>;
543 compatible = "rockchip,rk3188-pmu", "syscon";
547 pinctrl-names = "default";
548 pinctrl-0 = <&pwm0_out>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pwm1_out>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&pwm2_out>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pwm3_out>;
567 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
568 pinctrl-names = "default";
569 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
573 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
574 pinctrl-names = "default";
575 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
579 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
580 pinctrl-names = "default";
581 pinctrl-0 = <&uart0_xfer>;
585 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
586 pinctrl-names = "default";
587 pinctrl-0 = <&uart1_xfer>;
591 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
592 pinctrl-names = "default";
593 pinctrl-0 = <&uart2_xfer>;
597 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
598 pinctrl-names = "default";
599 pinctrl-0 = <&uart3_xfer>;
603 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";