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/openbmc/qemu/hw/xtensa/
H A Dmx_pic.c2 * Copyright (c) 2013 - 2019, Max Filippov, Open Source and Linux Lab.
69 } cpu[MX_MAX_CPU]; member
72 static uint64_t xtensa_mx_pic_ext_reg_read(void *opaque, hwaddr offset, in xtensa_mx_pic_ext_reg_read() argument
76 struct XtensaMxPic *mx = mx_cpu->mx; in xtensa_mx_pic_ext_reg_read()
78 if (offset < MIROUT + MX_MAX_IRQ) { in xtensa_mx_pic_ext_reg_read()
79 return mx->mirout[offset - MIROUT]; in xtensa_mx_pic_ext_reg_read()
80 } else if (offset >= MIPICAUSE && offset < MIPICAUSE + MX_MAX_CPU) { in xtensa_mx_pic_ext_reg_read()
81 return mx->cpu[offset - MIPICAUSE].mipicause; in xtensa_mx_pic_ext_reg_read()
83 switch (offset) { in xtensa_mx_pic_ext_reg_read()
85 return mx->mieng; in xtensa_mx_pic_ext_reg_read()
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/openbmc/qemu/hw/intc/
H A Darm_gic.c4 * Copyright (c) 2006-2007 CodeSourcery.
11 * controller, MPCore distributed interrupt controller and ARMv7-M
26 #include "hw/core/cpu.h"
61 if (!qtest_enabled() && s->num_cpu > 1) { in gic_get_current_cpu()
62 return current_cpu->cpu_index - s->first_cpu_index; in gic_get_current_cpu()
77 return s->revision == 2 || s->security_extn; in gic_has_groups()
80 static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) in gic_cpu_ns_access() argument
82 return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; in gic_cpu_ns_access()
85 static inline void gic_get_best_irq(GICState *s, int cpu, in gic_get_best_irq() argument
89 int cm = 1 << cpu; in gic_get_best_irq()
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H A Dtrace-events35 slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = 0…
36 slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" =…
37 slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d…
38 slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq m…
43 slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d"
45 slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d …
46 slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d"
51 grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
56 xics_icp_check_ipi(int server, uint8_t mfrr) "CPU %d can take IPI mfrr=0x%x"
57 xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr) "icp_accept: XIRR 0x%"PRIx32"->0x%"PRIx32
[all …]
H A Dloongarch_extioi.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #include "system/address-spaces.h"
24 for (i = 0; i < s->num_cpu; i++) { in extioi_get_index_from_archid()
25 if (s->cpu[i].arch_id == arch_id) { in extioi_get_index_from_archid()
30 if ((i < s->num_cpu) && s->cpu[i].cpu) { in extioi_get_index_from_archid()
34 return -1; in extioi_get_index_from_archid()
39 int ipnum, cpu, found, irq_index, irq_mask; in extioi_update_irq() local
41 ipnum = s->sw_ipmap[irq / 32]; in extioi_update_irq()
42 cpu = s->sw_coremap[irq]; in extioi_update_irq()
48 if (((s->enable[irq_index]) & irq_mask) == 0) { in extioi_update_irq()
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H A Dloongarch_extioi_kvm.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
34 kvm_extioi_access_sw_state(les->dev_fd, addr, &lecs->status, write); in kvm_extioi_access_sw_status()
41 int fd = les->dev_fd; in kvm_extioi_access_regs()
42 int addr, offset, cpu; in kvm_extioi_access_regs() local
45 offset = (addr - EXTIOI_NODETYPE_START) / 4; in kvm_extioi_access_regs()
46 kvm_extioi_access_reg(fd, addr, &lecs->nodetype[offset], write); in kvm_extioi_access_regs()
50 offset = (addr - EXTIOI_IPMAP_START) / 4; in kvm_extioi_access_regs()
51 kvm_extioi_access_reg(fd, addr, &lecs->ipmap[offset], write); in kvm_extioi_access_regs()
55 offset = (addr - EXTIOI_ENABLE_START) / 4; in kvm_extioi_access_regs()
56 kvm_extioi_access_reg(fd, addr, &lecs->enable[offset], write); in kvm_extioi_access_regs()
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H A Darm_gic_kvm.c2 * ARM Generic Interrupt Controller using KVM in-kernel support
32 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
47 * [0..N-1] : external interrupts in kvm_arm_gic_set_irq()
48 * [N..N+31] : PPI (internal) interrupts for CPU 0 in kvm_arm_gic_set_irq()
49 * [N+32..N+63] : PPI (internal interrupts for CPU 1 in kvm_arm_gic_set_irq()
53 * CPU number and interrupt number. in kvm_arm_gic_set_irq()
55 int irqtype, cpu; in kvm_arm_gic_set_irq() local
57 if (irq < (num_irq - GIC_INTERNAL)) { in kvm_arm_gic_set_irq()
63 cpu = 0; in kvm_arm_gic_set_irq()
66 /* Internal interrupt: decode into (cpu, interrupt id) */ in kvm_arm_gic_set_irq()
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H A Darm_gicv3_kvm.c2 * ARM Generic Interrupt Controller using KVM in-kernel support
26 #include "qemu/error-report.h"
47 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3"
89 kvm_arm_gic_set_irq(s->num_irq, irq, level); in kvm_arm_gicv3_set_irq()
95 static inline void kvm_gicd_access(GICv3State *s, int offset, in kvm_gicd_access() argument
98 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, in kvm_gicd_access()
99 KVM_VGIC_ATTR(offset, 0), in kvm_gicd_access()
103 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, in kvm_gicr_access() argument
106 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, in kvm_gicr_access()
107 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), in kvm_gicr_access()
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H A Darmv7m_nvic.c4 * Copyright (c) 2006-2007 CodeSourcery.
20 #include "hw/qdev-properties.h"
23 #include "target/arm/cpu.h"
24 #include "target/arm/cpu-features.h"
33 * the num-irq property counts the number of external IRQ lines
44 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
56 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
58 /* Effective running priority of the CPU when no exception is active
62 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
71 if (qemu_irq_is_connected(s->sysresetreq)) { in signal_sysresetreq()
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/openbmc/qemu/hw/misc/
H A Dallwinner-cpucfg.c2 * Allwinner CPU Configuration Module emulation
26 #include "qemu/error-report.h"
28 #include "hw/core/cpu.h"
29 #include "target/arm/arm-powerctl.h"
30 #include "target/arm/cpu.h"
31 #include "hw/misc/allwinner-cpucfg.h"
37 REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
38 REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
39 REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
40 REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
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H A Darmsse-cpu-pwrctrl.c2 * Arm SSE CPU PWRCTRL register block
13 * This is a model of the "CPU<N>_PWRCTRL block" which is part of the
14 * Arm Corstone SSE-300 Example Subsystem and documented in
26 #include "hw/misc/armsse-cpu-pwrctrl.h"
49 static uint64_t pwrctrl_read(void *opaque, hwaddr offset, unsigned size) in pwrctrl_read() argument
54 switch (offset) { in pwrctrl_read()
56 r = s->cpupwrcfg; in pwrctrl_read()
59 r = cpu_pwrctrl_id[(offset - A_PID4) / 4]; in pwrctrl_read()
63 "SSE CPU_PWRCTRL read: bad offset %x\n", (int)offset); in pwrctrl_read()
67 trace_armsse_cpu_pwrctrl_read(offset, r, size); in pwrctrl_read()
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/openbmc/qemu/docs/specs/
H A Dacpi_cpu_hotplug.rst1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
11 Legacy ACPI CPU hotplug interface registers
12 -------------------------------------------
14 CPU present bitmap for:
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
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/openbmc/qemu/hw/ppc/
H A Dpnv_core.c2 * QEMU PowerPC PowerNV CPU Core model
25 #include "target/ppc/cpu.h"
32 #include "hw/qdev-properties.h"
38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); in pnv_core_cpu_typename()
45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) in pnv_core_cpu_reset() argument
47 CPUState *cs = CPU(cpu); in pnv_core_cpu_reset()
48 CPUPPCState *env = &cpu->env; in pnv_core_cpu_reset()
49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_reset()
57 env->gpr[3] = PNV_FDT_ADDR; in pnv_core_cpu_reset()
58 env->nip = 0x10; in pnv_core_cpu_reset()
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/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dspin_table.c1 // SPDX-License-Identifier: GPL-2.0+
13 int cpus_offset, offset; in spin_table_update_dt() local
17 unsigned long rsv_size = &spin_table_reserve_end - in spin_table_update_dt()
22 return -ENODEV; in spin_table_update_dt()
24 for (offset = fdt_first_subnode(fdt, cpus_offset); in spin_table_update_dt()
25 offset >= 0; in spin_table_update_dt()
26 offset = fdt_next_subnode(fdt, offset)) { in spin_table_update_dt()
27 prop = fdt_getprop(fdt, offset, "device_type", NULL); in spin_table_update_dt()
28 if (!prop || strcmp(prop, "cpu")) in spin_table_update_dt()
32 * In the first loop, we check if every CPU node specifies in spin_table_update_dt()
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-kernel/trace-cmd/files/
H A D0001-Replace-LFS64-interfaces-off64_t-and-lseek64.patch3 Date: Fri, 6 Jan 2023 16:53:06 -0800
6 Musl does not define these interfaces unless -D_LARGEFILE64_SOURCE is
7 defined and that too it is transitional until apps switch to using 64-bit
8 off_t. We pass -D_FILE_OFFSET_BITS=64 in makefiles already therefore
13 [1] https://git.musl-libc.org/cgit/musl/commit/?id=246f1c811448f37a44b41cd8df8d0ef9736d95f4i
15 Upstream-Status: Submitted [https://lore.kernel.org/linux-trace-devel/20230109225315.1284538-1-raj.…
16 Signed-off-by: Khem Raj <raj.khem@gmail.com>
17 ---
18 .../include/private/trace-cmd-private.h | 12 +-
19 lib/trace-cmd/include/trace-cmd-local.h | 4 +-
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/openbmc/qemu/system/
H A Dtrace-events7 # dma-helpers.c
8 dma_blk_io(void *dbs, void *bs, int64_t offset, bool to_dev) "dbs=%p bs=%p offset=%" PRId64 " to_de…
19 …void *mr, uint64_t addr, uint64_t value, unsigned size, const char *name) "cpu %d mr %p addr 0x%"P…
20 …void *mr, uint64_t addr, uint64_t value, unsigned size, const char *name) "cpu %d mr %p addr 0x%"P…
21 …subpage_read(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %…
22 …ubpage_write(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %…
23 …ad(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"P…
24 …te(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"P…
33 find_ram_offset(uint64_t size, uint64_t offset) "size: 0x%" PRIx64 " @ 0x%" PRIx64
34 …, uint64_t candidate, uint64_t offset, uint64_t next, uint64_t mingap) "trying size: 0x%" PRIx64 "…
[all …]
/openbmc/smbios-mdr/src/
H A Dcpu.cpp8 // http://www.apache.org/licenses/LICENSE-2.0
17 #include "cpu.hpp"
27 void Cpu::socket(const uint8_t positionNum, const uint8_t structLen, in socket()
38 void Cpu::family(const uint8_t family, const uint16_t family2) in family()
46 else if (it->first == processorFamily2Indicator) in family()
56 processor::family(it2->second); in family()
62 processor::family(it->second); in family()
67 void Cpu::manufacturer(const uint8_t positionNum, const uint8_t structLen, in manufacturer()
75 void Cpu::partNumber(const uint8_t positionNum, const uint8_t structLen, in partNumber()
83 void Cpu::serialNumber(const uint8_t positionNum, const uint8_t structLen, in serialNumber()
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/openbmc/qemu/hw/m68k/
H A Dmcf_intc.c13 #include "cpu.h"
17 #include "hw/qdev-properties.h"
20 #define TYPE_MCF_INTC "mcf-intc"
32 M68kCPU *cpu; member
43 active = (s->ipr | s->ifr) & s->enabled & ~s->imr; in mcf_intc_update()
48 if ((active & 1) != 0 && s->icr[i] >= best_level) { in mcf_intc_update()
49 best_level = s->icr[i]; in mcf_intc_update()
55 s->active_vector = ((best == 64) ? 24 : (best + 64)); in mcf_intc_update()
56 m68k_set_irq_level(s->cpu, best_level, s->active_vector); in mcf_intc_update()
62 int offset; in mcf_intc_read() local
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/openbmc/qemu/hw/s390x/
H A Ds390-pci-inst.c10 * your option) any later version. See the COPYING file in the top-level
18 #include "qemu/error-report.h"
23 #include "hw/s390x/s390-pci-inst.h"
24 #include "hw/s390x/s390-pci-bus.h"
25 #include "hw/s390x/s390-pci-kvm.h"
26 #include "hw/s390x/s390-pci-vfio.h"
33 if (iommu->dma_limit) { in inc_dma_avail()
34 iommu->dma_limit->avail++; in inc_dma_avail()
40 if (iommu->dma_limit) { in dec_dma_avail()
41 iommu->dma_limit->avail--; in dec_dma_avail()
[all …]
/openbmc/qemu/hw/arm/
H A Dimx8mp-evk.c6 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "system/address-spaces.h"
12 #include "hw/arm/fsl-imx8mp.h"
14 #include "hw/qdev-properties.h"
16 #include "qemu/error-report.h"
22 int i, offset; in imx8mp_evk_modify_dtb() local
26 "nxp,imx8mp-fspi", in imx8mp_evk_modify_dtb()
32 offset = fdt_node_offset_by_compatible(fdt, -1, dev_str); in imx8mp_evk_modify_dtb()
33 while (offset >= 0) { in imx8mp_evk_modify_dtb()
34 fdt_nop_node(fdt, offset); in imx8mp_evk_modify_dtb()
[all …]
H A Dhighbank.c4 * Copyright (c) 2010-2012 Calxeda
31 #include "qemu/error-report.h"
33 #include "hw/ide/ahci-sysbus.h"
34 #include "hw/cpu/a9mpcore.h"
35 #include "hw/cpu/a15mpcore.h"
38 #include "cpu.h"
39 #include "target/arm/cpu-qom.h"
48 #define GIC_EXT_IRQS 128 /* EnergyCore ECX-1000 & ECX-2000 */
53 static void hb_regs_write(void *opaque, hwaddr offset, in hb_regs_write() argument
58 if (offset == 0xf00) { in hb_regs_write()
[all …]
/openbmc/qemu/target/i386/hvf/
H A Dhvf-cpu.c2 * x86 HVF CPU type initialization
7 * See the COPYING file in the top-level directory.
11 #include "cpu.h"
12 #include "host-cpu.h"
17 #include "accel/accel-cpu-target.h"
18 #include "hvf-i386.h"
20 static void hvf_cpu_max_instance_init(X86CPU *cpu) in hvf_cpu_max_instance_init() argument
22 CPUX86State *env = &cpu->env; in hvf_cpu_max_instance_init()
24 env->cpuid_min_level = in hvf_cpu_max_instance_init()
26 env->cpuid_min_xlevel = in hvf_cpu_max_instance_init()
[all …]
/openbmc/u-boot/board/freescale/m547xevb/
H A DREADME4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
13 - board/freescale/m547xevb/mii.c MII init
14 - board/freescale/m547xevb/Makefile Makefile
15 - board/freescale/m547xevb/config.mk config make
16 - board/freescale/m547xevb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
20 - arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
[all …]
/openbmc/qemu/gdbstub/
H A Duser-target.c2 * Target specific user-mode handling
4 * Copyright (c) 2003-2005 Fabrice Bellard
7 * SPDX-License-Identifier: LGPL-2.0-or-later
16 #include "linux-user/loader.h"
17 #include "linux-user/qemu.h"
34 -1, /* SIGEMT */
56 -1, /* SIGLOST */
62 -1,
64 -1, /* SIGPOLL */
65 -1,
[all …]
/openbmc/qemu/contrib/elf2dmp/
H A Dqemu_elf.c9 #include "qemu/host-utils.h"
16 #define ROUND_UP(n, d) (((n) + (d) - 1) & -(0 ? (n) : (d)))
21 return s->gs.base >> 63; in is_system()
27 Elf64_Phdr *phdr = (void *)((uint8_t *)map + ehdr->e_phoff); in elf64_getphdr()
36 return ehdr->e_phnum; in elf_getphdrnum()
41 uint64_t offset = *offsetp; in advance_note_offset() local
43 if (uadd64_overflow(offset, size, &offset) || offset > UINT64_MAX - 3) { in advance_note_offset()
47 offset = ROUND_UP(offset, 4); in advance_note_offset()
49 if (offset > end) { in advance_note_offset()
53 *offsetp = offset; in advance_note_offset()
[all …]
/openbmc/qemu/include/exec/
H A Dcpu-common.h2 * CPU interfaces that are target independent.
6 * SPDX-License-Identifier: LGPL-2.1+
13 #include "hw/core/cpu.h"
14 #include "tcg/debug-assert.h"
15 #include "exec/page-protection.h"
19 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
20 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
21 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
22 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
25 void cpu_exec_step_atomic(CPUState *cpu);
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