| /openbmc/qemu/hw/intc/ |
| H A D | arm_gic.c | 4 * Copyright (c) 2006-2007 CodeSourcery.
11 * controller, MPCore distributed interrupt controller and ARMv7-M
26 #include "hw/core/cpu.h"
61 if (!qtest_enabled() && s->num_cpu > 1) { in gic_get_current_cpu()
62 return current_cpu->cpu_index; in gic_get_current_cpu()
77 return s->revision == 2 || s->security_extn; in gic_has_groups()
80 static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) in gic_cpu_ns_access() argument
82 return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; in gic_cpu_ns_access()
85 static inline void gic_get_best_irq(GICState *s, int cpu, in gic_get_best_irq() argument
89 int cm = 1 << cpu; in gic_get_best_irq()
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| H A D | trace-events | 35 slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = 0…
36 slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" =…
37 slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d…
38 slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq m…
43 slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d"
45 slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d …
46 slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d"
51 grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
56 xics_icp_check_ipi(int server, uint8_t mfrr) "CPU %d can take IPI mfrr=0x%x"
57 xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr) "icp_accept: XIRR 0x%"PRIx32"->0x%"PRIx32
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| H A D | loongarch_extioi.c | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #include "hw/qdev-properties.h"
16 #include "exec/address-spaces.h"
24 int ipnum, cpu, found, irq_index, irq_mask; in extioi_update_irq() local
26 ipnum = s->sw_ipmap[irq / 32]; in extioi_update_irq()
27 cpu = s->sw_coremap[irq]; in extioi_update_irq()
33 if (((s->enable[irq_index]) & irq_mask) == 0) { in extioi_update_irq()
36 s->cpu[cpu].coreisr[irq_index] |= irq_mask; in extioi_update_irq()
37 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); in extioi_update_irq()
38 set_bit(irq, s->cpu[cpu].sw_isr[ipnum]); in extioi_update_irq()
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| H A D | arm_gic_kvm.c | 2 * ARM Generic Interrupt Controller using KVM in-kernel support
32 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
47 * [0..N-1] : external interrupts in kvm_arm_gic_set_irq()
48 * [N..N+31] : PPI (internal) interrupts for CPU 0 in kvm_arm_gic_set_irq()
49 * [N+32..N+63] : PPI (internal interrupts for CPU 1 in kvm_arm_gic_set_irq()
53 * CPU number and interrupt number. in kvm_arm_gic_set_irq()
55 int irqtype, cpu; in kvm_arm_gic_set_irq() local
57 if (irq < (num_irq - GIC_INTERNAL)) { in kvm_arm_gic_set_irq()
63 cpu = 0; in kvm_arm_gic_set_irq()
66 /* Internal interrupt: decode into (cpu, interrupt id) */ in kvm_arm_gic_set_irq()
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| /openbmc/qemu/hw/xtensa/ |
| H A D | mx_pic.c | 2 * Copyright (c) 2013 - 2019, Max Filippov, Open Source and Linux Lab.
69 } cpu[MX_MAX_CPU]; member
72 static uint64_t xtensa_mx_pic_ext_reg_read(void *opaque, hwaddr offset, in xtensa_mx_pic_ext_reg_read() argument
76 struct XtensaMxPic *mx = mx_cpu->mx; in xtensa_mx_pic_ext_reg_read()
78 if (offset < MIROUT + MX_MAX_IRQ) { in xtensa_mx_pic_ext_reg_read()
79 return mx->mirout[offset - MIROUT]; in xtensa_mx_pic_ext_reg_read()
80 } else if (offset >= MIPICAUSE && offset < MIPICAUSE + MX_MAX_CPU) { in xtensa_mx_pic_ext_reg_read()
81 return mx->cpu[offset - MIPICAUSE].mipicause; in xtensa_mx_pic_ext_reg_read()
83 switch (offset) { in xtensa_mx_pic_ext_reg_read()
85 return mx->mieng; in xtensa_mx_pic_ext_reg_read()
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| /openbmc/linux/drivers/thermal/intel/ |
| H A D | intel_tcc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access
12 * intel_tcc_get_tjmax() - returns the default TCC activation Temperature
13 * @cpu: cpu that the MSR should be run on, nagative value means any cpu.
20 int intel_tcc_get_tjmax(int cpu) in intel_tcc_get_tjmax() argument
25 if (cpu < 0) in intel_tcc_get_tjmax()
28 err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); in intel_tcc_get_tjmax()
34 return val ? val : -ENODATA; in intel_tcc_get_tjmax()
39 * intel_tcc_get_offset() - returns the TCC Offset value to Tjmax
40 * @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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| /openbmc/linux/tools/testing/selftests/rseq/ |
| H A D | param_test.c | 1 // SPDX-License-Identifier: LGPL-2.1
44 static __thread __attribute__((tls_model("initial-exec")))
49 static __thread __attribute__((tls_model("initial-exec"), unused))
113 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
204 "addiu " INJECT_ASM_REG ", -1\n\t" \
226 "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
245 if (loc_nr_loops == -1 && opt_modulo) { \
246 if (yield_mod_cnt == opt_modulo - 1) { \
297 int rseq_membarrier_expedited(int cpu) in rseq_membarrier_expedited() argument
317 int rseq_membarrier_expedited(int cpu) in rseq_membarrier_expedited() argument
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| /openbmc/qemu/hw/misc/ |
| H A D | allwinner-cpucfg.c | 2 * Allwinner CPU Configuration Module emulation
26 #include "qemu/error-report.h"
28 #include "hw/core/cpu.h"
29 #include "target/arm/arm-powerctl.h"
30 #include "target/arm/cpu.h"
31 #include "hw/misc/allwinner-cpucfg.h"
37 REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
38 REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
39 REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
40 REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
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| /openbmc/qemu/hw/ppc/ |
| H A D | pnv_core.c | 2 * QEMU PowerPC PowerNV CPU Core model
25 #include "target/ppc/cpu.h"
32 #include "hw/qdev-properties.h"
38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); in pnv_core_cpu_typename()
45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) in pnv_core_cpu_reset() argument
47 CPUState *cs = CPU(cpu); in pnv_core_cpu_reset()
48 CPUPPCState *env = &cpu->env; in pnv_core_cpu_reset()
49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_reset()
57 env->gpr[3] = PNV_FDT_ADDR; in pnv_core_cpu_reset()
58 env->nip = 0x10; in pnv_core_cpu_reset()
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| /openbmc/linux/arch/arm/mach-zynq/ |
| H A D | slcr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
19 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
41 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
43 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
47 * zynq_slcr_read - Read a register in SLCR block
50 * @offset: Register offset in SLCR block
54 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
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| /openbmc/qemu/docs/specs/ |
| H A D | acpi_cpu_hotplug.rst | 1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
11 Legacy ACPI CPU hotplug interface registers
12 -------------------------------------------
14 CPU present bitmap for:
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
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| /openbmc/linux/Documentation/core-api/ |
| H A D | this_cpu_ops.rst | 8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
65 ------------------------------------
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * - the basic variant, called "orion-gpio", with the simplest
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * - the armadaxp variant for Armada XP systems. This variant keeps
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
77 /* The MV78200 has per-CPU registers for edge mask and level mask */
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-kernel/trace-cmd/files/ |
| H A D | 0001-Replace-LFS64-interfaces-off64_t-and-lseek64.patch | 3 Date: Fri, 6 Jan 2023 16:53:06 -0800
6 Musl does not define these interfaces unless -D_LARGEFILE64_SOURCE is
7 defined and that too it is transitional until apps switch to using 64-bit
8 off_t. We pass -D_FILE_OFFSET_BITS=64 in makefiles already therefore
13 [1] https://git.musl-libc.org/cgit/musl/commit/?id=246f1c811448f37a44b41cd8df8d0ef9736d95f4i
15 Upstream-Status: Submitted [https://lore.kernel.org/linux-trace-devel/20230109225315.1284538-1-raj.…
16 Signed-off-by: Khem Raj <raj.khem@gmail.com>
17 ---
18 .../include/private/trace-cmd-private.h | 12 +-
19 lib/trace-cmd/include/trace-cmd-local.h | 4 +-
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| /openbmc/linux/arch/ia64/include/asm/uv/ |
| H A D | uv_hub.h | 23 * M - The low M bits of a physical address represent the offset
28 * N - Number of bits in the node portion of a socket physical
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
34 * right shift the NASID by 1 to exclude the always-zero bit.
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
45 * +--------------------------------+---------------------+
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
50 * M - number of node offset bits (35 .. 40)
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| /openbmc/linux/arch/x86/include/asm/uv/ |
| H A D | uv_hub.h | 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
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| /openbmc/linux/kernel/time/ |
| H A D | timer_list.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "tick-internal.h"
21 int cpu; member
28 * to the console (on SysRq-Q):
49 SEQ_printf(m, " #%d: <%pK>, %ps", idx, taddr, timer->function); in print_timer()
50 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
52 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
55 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
56 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
73 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
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| /openbmc/linux/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_coherency.c | 2 * SPDX-License-Identifier: MIT
23 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
28 u32 *cpu; in cpu_set() local
31 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
32 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
36 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
38 cpu = map + offset_in_page(offset); in cpu_set()
41 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
43 *cpu = v; in cpu_set()
46 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
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| /openbmc/linux/tools/testing/selftests/kvm/lib/aarch64/ |
| H A D | gic_v3.c | 1 // SPDX-License-Identifier: GPL-2.0
39 GUEST_ASSERT(count--); in gicv3_gicd_wait_for_rwp()
49 GUEST_ASSERT(count--); in gicv3_gicr_wait_for_rwp()
109 * All other fields are read-only, so no need to read CTLR first. In in gicv3_set_eoi_split()
117 uint32_t gicv3_reg_readl(uint32_t cpu_or_dist, uint64_t offset) in gicv3_reg_readl() argument
121 return readl(base + offset); in gicv3_reg_readl()
124 void gicv3_reg_writel(uint32_t cpu_or_dist, uint64_t offset, uint32_t reg_val) in gicv3_reg_writel() argument
128 writel(reg_val, base + offset); in gicv3_reg_writel()
131 uint32_t gicv3_getl_fields(uint32_t cpu_or_dist, uint64_t offset, uint32_t mask) in gicv3_getl_fields() argument
133 return gicv3_reg_readl(cpu_or_dist, offset) & mask; in gicv3_getl_fields()
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | krait-cc.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
16 #include "clk-krait.h"
52 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); in krait_notifier_cb()
53 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
54 mux->reparent = false; in krait_notifier_cb()
61 if (!mux->reparent) in krait_notifier_cb()
62 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
63 mux->old_index); in krait_notifier_cb()
74 mux->clk_nb.notifier_call = krait_notifier_cb; in krait_notifier_register()
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| /openbmc/smbios-mdr/src/ |
| H A D | cpu.cpp | 8 // http://www.apache.org/licenses/LICENSE-2.0
17 #include "cpu.hpp"
27 void Cpu::socket(const uint8_t positionNum, const uint8_t structLen, in socket()
38 void Cpu::family(const uint8_t family, const uint16_t family2) in family()
46 else if (it->first == processorFamily2Indicator) in family()
56 processor::family(it2->second); in family()
62 processor::family(it->second); in family()
67 void Cpu::manufacturer(const uint8_t positionNum, const uint8_t structLen, in manufacturer()
75 void Cpu::partNumber(const uint8_t positionNum, const uint8_t structLen, in partNumber()
83 void Cpu::serialNumber(const uint8_t positionNum, const uint8_t structLen, in serialNumber()
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| /openbmc/qemu/hw/s390x/ |
| H A D | s390-pci-inst.c | 10 * your option) any later version. See the COPYING file in the top-level
17 #include "qemu/error-report.h"
20 #include "hw/s390x/s390-pci-inst.h"
21 #include "hw/s390x/s390-pci-bus.h"
22 #include "hw/s390x/s390-pci-kvm.h"
23 #include "hw/s390x/s390-pci-vfio.h"
30 if (iommu->dma_limit) { in inc_dma_avail()
31 iommu->dma_limit->avail++; in inc_dma_avail()
37 if (iommu->dma_limit) { in dec_dma_avail()
38 iommu->dma_limit->avail--; in dec_dma_avail()
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| /openbmc/u-boot/arch/arm/cpu/armv8/ |
| H A D | spin_table.c | 1 // SPDX-License-Identifier: GPL-2.0+
13 int cpus_offset, offset; in spin_table_update_dt() local
17 unsigned long rsv_size = &spin_table_reserve_end - in spin_table_update_dt()
22 return -ENODEV; in spin_table_update_dt()
24 for (offset = fdt_first_subnode(fdt, cpus_offset); in spin_table_update_dt()
25 offset >= 0; in spin_table_update_dt()
26 offset = fdt_next_subnode(fdt, offset)) { in spin_table_update_dt()
27 prop = fdt_getprop(fdt, offset, "device_type", NULL); in spin_table_update_dt()
28 if (!prop || strcmp(prop, "cpu")) in spin_table_update_dt()
32 * In the first loop, we check if every CPU node specifies in spin_table_update_dt()
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| /openbmc/qemu/hw/m68k/ |
| H A D | mcf_intc.c | 13 #include "cpu.h"
17 #include "hw/qdev-properties.h"
20 #define TYPE_MCF_INTC "mcf-intc"
32 M68kCPU *cpu; member
43 active = (s->ipr | s->ifr) & s->enabled & ~s->imr; in mcf_intc_update()
48 if ((active & 1) != 0 && s->icr[i] >= best_level) { in mcf_intc_update()
49 best_level = s->icr[i]; in mcf_intc_update()
55 s->active_vector = ((best == 64) ? 24 : (best + 64)); in mcf_intc_update()
56 m68k_set_irq_level(s->cpu, best_level, s->active_vector); in mcf_intc_update()
62 int offset; in mcf_intc_read() local
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| /openbmc/linux/drivers/gpu/drm/lima/ |
| H A D | lima_vm.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
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