Lines Matching +full:cpu +full:- +full:offset
2 * QEMU PowerPC PowerNV CPU Core model
25 #include "target/ppc/cpu.h"
32 #include "hw/qdev-properties.h"
38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); in pnv_core_cpu_typename()
45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) in pnv_core_cpu_reset() argument
47 CPUState *cs = CPU(cpu); in pnv_core_cpu_reset()
48 CPUPPCState *env = &cpu->env; in pnv_core_cpu_reset()
49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_reset()
57 env->gpr[3] = PNV_FDT_ADDR; in pnv_core_cpu_reset()
58 env->nip = 0x10; in pnv_core_cpu_reset()
59 env->msr |= MSR_HVB; /* Hypervisor mode */ in pnv_core_cpu_reset()
60 env->spr[SPR_HRMOR] = pc->hrmor; in pnv_core_cpu_reset()
61 if (pc->big_core) { in pnv_core_cpu_reset()
63 env->spr[SPR_PVR] &= ~PPC_BIT(51); in pnv_core_cpu_reset()
70 pcc->intc_reset(pc->chip, cpu); in pnv_core_cpu_reset()
82 uint32_t offset = addr >> 3; in pnv_core_power8_xscom_read() local
86 switch (offset) { in pnv_core_power8_xscom_read()
95 offset); in pnv_core_power8_xscom_read()
104 uint32_t offset = addr >> 3; in pnv_core_power8_xscom_write() local
107 offset); in pnv_core_power8_xscom_write()
132 uint32_t offset = addr >> 3; in pnv_core_power9_xscom_read() local
136 switch (offset) { in pnv_core_power9_xscom_read()
152 offset); in pnv_core_power9_xscom_read()
161 uint32_t offset = addr >> 3; in pnv_core_power9_xscom_write() local
163 switch (offset) { in pnv_core_power9_xscom_write()
169 offset); in pnv_core_power9_xscom_write()
196 int nr_threads = CPU_CORE(pc)->nr_threads; in pnv_core_power10_xscom_read()
198 uint32_t offset = addr >> 3; in pnv_core_power10_xscom_read() local
201 switch (offset) { in pnv_core_power10_xscom_read()
204 PowerPCCPU *cpu = pc->threads[i]; in pnv_core_power10_xscom_read() local
205 CPUState *cs = CPU(cpu); in pnv_core_power10_xscom_read()
207 if (cs->halted) { in pnv_core_power10_xscom_read()
211 if (pc->lpar_per_core) { in pnv_core_power10_xscom_read()
219 PowerPCCPU *cpu = pc->threads[i]; in pnv_core_power10_xscom_read() local
220 CPUPPCState *env = &cpu->env; in pnv_core_power10_xscom_read()
221 if (env->quiesced) { in pnv_core_power10_xscom_read()
228 offset); in pnv_core_power10_xscom_read()
238 int nr_threads = CPU_CORE(pc)->nr_threads; in pnv_core_power10_xscom_write()
240 uint32_t offset = addr >> 3; in pnv_core_power10_xscom_write() local
242 switch (offset) { in pnv_core_power10_xscom_write()
245 PowerPCCPU *cpu = pc->threads[i]; in pnv_core_power10_xscom_write() local
246 CPUState *cs = CPU(cpu); in pnv_core_power10_xscom_write()
247 CPUPPCState *env = &cpu->env; in pnv_core_power10_xscom_write()
252 env->quiesced = true; in pnv_core_power10_xscom_write()
256 env->quiesced = false; in pnv_core_power10_xscom_write()
261 env->quiesced = false; in pnv_core_power10_xscom_write()
265 env->quiesced = false; in pnv_core_power10_xscom_write()
284 offset); in pnv_core_power10_xscom_write()
298 static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, in pnv_core_cpu_realize() argument
301 CPUPPCState *env = &cpu->env; in pnv_core_cpu_realize()
303 ppc_spr_t *pir_spr = &env->spr_cb[SPR_PIR]; in pnv_core_cpu_realize()
304 ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR]; in pnv_core_cpu_realize()
307 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_realize()
309 if (!qdev_realize(DEVICE(cpu), NULL, errp)) { in pnv_core_cpu_realize()
313 pcc->intc_create(pc->chip, cpu, &local_err); in pnv_core_cpu_realize()
321 pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir); in pnv_core_cpu_realize()
322 pir_spr->default_value = pir; in pnv_core_cpu_realize()
323 tir_spr->default_value = tir; in pnv_core_cpu_realize()
325 env->chip_index = pc->chip->chip_id; in pnv_core_cpu_realize()
327 if (pc->big_core) { in pnv_core_cpu_realize()
329 env->core_index = core_hwid >> 1; in pnv_core_cpu_realize()
331 env->core_index = core_hwid; in pnv_core_cpu_realize()
334 if (pc->lpar_per_core) { in pnv_core_cpu_realize()
335 cpu_ppc_set_1lpar(cpu); in pnv_core_cpu_realize()
338 /* Set time-base frequency to 512 MHz */ in pnv_core_cpu_realize()
348 for (i = 0; i < cc->nr_threads; i++) { in pnv_core_reset()
349 pnv_core_cpu_reset(pc, pc->threads[i]); in pnv_core_reset()
364 assert(pc->chip); in pnv_core_realize()
366 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); in pnv_core_realize()
367 for (i = 0; i < cc->nr_threads; i++) { in pnv_core_realize()
368 PowerPCCPU *cpu; in pnv_core_realize() local
372 cpu = POWERPC_CPU(obj); in pnv_core_realize()
374 pc->threads[i] = POWERPC_CPU(obj); in pnv_core_realize()
375 if (cc->nr_threads > 1) { in pnv_core_realize()
376 cpu->env.has_smt_siblings = true; in pnv_core_realize()
382 cpu->machine_data = g_new0(PnvCPUState, 1); in pnv_core_realize()
383 pnv_cpu = pnv_cpu_state(cpu); in pnv_core_realize()
384 pnv_cpu->pnv_core = pc; in pnv_core_realize()
389 for (j = 0; j < cc->nr_threads; j++) { in pnv_core_realize()
390 pnv_core_cpu_realize(pc, pc->threads[j], &local_err, j); in pnv_core_realize()
396 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); in pnv_core_realize()
397 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, in pnv_core_realize()
398 pc, name, pcc->xscom_size); in pnv_core_realize()
404 while (--i >= 0) { in pnv_core_realize()
405 obj = OBJECT(pc->threads[i]); in pnv_core_realize()
408 g_free(pc->threads); in pnv_core_realize()
412 static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu) in pnv_core_cpu_unrealize() argument
414 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); in pnv_core_cpu_unrealize()
415 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_unrealize()
417 pcc->intc_destroy(pc->chip, cpu); in pnv_core_cpu_unrealize()
418 cpu_remove_sync(CPU(cpu)); in pnv_core_cpu_unrealize()
419 cpu->machine_data = NULL; in pnv_core_cpu_unrealize()
421 object_unparent(OBJECT(cpu)); in pnv_core_cpu_unrealize()
432 for (i = 0; i < cc->nr_threads; i++) { in pnv_core_unrealize()
433 pnv_core_cpu_unrealize(pc, pc->threads[i]); in pnv_core_unrealize()
435 g_free(pc->threads); in pnv_core_unrealize()
441 DEFINE_PROP_BOOL("big-core", PnvCore, big_core, false),
442 DEFINE_PROP_BOOL("quirk-tb-big-core", PnvCore, tod_state.big_core_quirk,
444 DEFINE_PROP_BOOL("lpar-per-core", PnvCore, lpar_per_core, false),
453 pcc->xscom_ops = &pnv_core_power8_xscom_ops; in pnv_core_power8_class_init()
454 pcc->xscom_size = PNV_XSCOM_EX_SIZE; in pnv_core_power8_class_init()
461 pcc->xscom_ops = &pnv_core_power9_xscom_ops; in pnv_core_power9_class_init()
462 pcc->xscom_size = PNV_XSCOM_EX_SIZE; in pnv_core_power9_class_init()
469 pcc->xscom_ops = &pnv_core_power10_xscom_ops; in pnv_core_power10_class_init()
470 pcc->xscom_size = PNV10_XSCOM_EC_SIZE; in pnv_core_power10_class_init()
477 dc->realize = pnv_core_realize; in pnv_core_class_init()
478 dc->unrealize = pnv_core_unrealize; in pnv_core_class_init()
480 dc->user_creatable = false; in pnv_core_class_init()
517 uint32_t offset = addr >> 3; in DEFINE_TYPES() local
518 uint64_t val = -1; in DEFINE_TYPES()
520 switch (offset) { in DEFINE_TYPES()
527 offset); in DEFINE_TYPES()
536 uint32_t offset = addr >> 3; in pnv_quad_power9_xscom_write() local
538 switch (offset) { in pnv_quad_power9_xscom_write()
544 offset); in pnv_quad_power9_xscom_write()
565 uint32_t offset = addr >> 3; in pnv_quad_power10_xscom_read() local
566 uint64_t val = -1; in pnv_quad_power10_xscom_read()
568 switch (offset) { in pnv_quad_power10_xscom_read()
571 offset); in pnv_quad_power10_xscom_read()
580 uint32_t offset = addr >> 3; in pnv_quad_power10_xscom_write() local
582 switch (offset) { in pnv_quad_power10_xscom_write()
585 offset); in pnv_quad_power10_xscom_write()
606 uint32_t offset = addr >> 3; in pnv_qme_power10_xscom_read() local
607 uint64_t val = -1; in pnv_qme_power10_xscom_read()
613 switch (offset & ~PPC_BITMASK32(16, 19)) { in pnv_qme_power10_xscom_read()
616 if (eq->special_wakeup_done) { in pnv_qme_power10_xscom_read()
623 offset); in pnv_qme_power10_xscom_read()
633 uint32_t offset = addr >> 3; in pnv_qme_power10_xscom_write() local
637 switch (offset & ~PPC_BITMASK32(16, 19)) { in pnv_qme_power10_xscom_write()
640 eq->special_wakeup_done = set; in pnv_qme_power10_xscom_write()
643 if (offset & PPC_BIT32(16 + i)) { in pnv_qme_power10_xscom_write()
644 eq->special_wakeup[i] = set; in pnv_qme_power10_xscom_write()
650 offset); in pnv_qme_power10_xscom_write()
670 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); in pnv_quad_power9_realize()
671 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), in pnv_quad_power9_realize()
672 pqc->xscom_ops, in pnv_quad_power9_realize()
674 pqc->xscom_size); in pnv_quad_power9_realize()
683 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); in pnv_quad_power10_realize()
684 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), in pnv_quad_power10_realize()
685 pqc->xscom_ops, in pnv_quad_power10_realize()
687 pqc->xscom_size); in pnv_quad_power10_realize()
689 snprintf(name, sizeof(name), "xscom-qme.%d", eq->quad_id); in pnv_quad_power10_realize()
690 pnv_xscom_region_init(&eq->xscom_qme_regs, OBJECT(dev), in pnv_quad_power10_realize()
691 pqc->xscom_qme_ops, in pnv_quad_power10_realize()
693 pqc->xscom_qme_size); in pnv_quad_power10_realize()
697 DEFINE_PROP_UINT32("quad-id", PnvQuad, quad_id, 0),
706 dc->realize = pnv_quad_power9_realize; in pnv_quad_power9_class_init()
708 pqc->xscom_ops = &pnv_quad_power9_xscom_ops; in pnv_quad_power9_class_init()
709 pqc->xscom_size = PNV9_XSCOM_EQ_SIZE; in pnv_quad_power9_class_init()
717 dc->realize = pnv_quad_power10_realize; in pnv_quad_power10_class_init()
719 pqc->xscom_ops = &pnv_quad_power10_xscom_ops; in pnv_quad_power10_class_init()
720 pqc->xscom_size = PNV10_XSCOM_EQ_SIZE; in pnv_quad_power10_class_init()
722 pqc->xscom_qme_ops = &pnv_qme_power10_xscom_ops; in pnv_quad_power10_class_init()
723 pqc->xscom_qme_size = PNV10_XSCOM_QME_SIZE; in pnv_quad_power10_class_init()
731 dc->user_creatable = false; in pnv_quad_class_init()