13bb16560SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2fefe7b09SThomas Petazzoni /*
3fefe7b09SThomas Petazzoni * GPIO driver for Marvell SoCs
4fefe7b09SThomas Petazzoni *
5fefe7b09SThomas Petazzoni * Copyright (C) 2012 Marvell
6fefe7b09SThomas Petazzoni *
7fefe7b09SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8fefe7b09SThomas Petazzoni * Andrew Lunn <andrew@lunn.ch>
9fefe7b09SThomas Petazzoni * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10fefe7b09SThomas Petazzoni *
11fefe7b09SThomas Petazzoni * This driver is a fairly straightforward GPIO driver for the
12fefe7b09SThomas Petazzoni * complete family of Marvell EBU SoC platforms (Orion, Dove,
13fefe7b09SThomas Petazzoni * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
14fefe7b09SThomas Petazzoni * driver is the different register layout that exists between the
15fefe7b09SThomas Petazzoni * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
16fefe7b09SThomas Petazzoni * platforms (MV78200 from the Discovery family and the Armada
17fefe7b09SThomas Petazzoni * XP). Therefore, this driver handles three variants of the GPIO
18fefe7b09SThomas Petazzoni * block:
19fefe7b09SThomas Petazzoni * - the basic variant, called "orion-gpio", with the simplest
20fefe7b09SThomas Petazzoni * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
21fefe7b09SThomas Petazzoni * non-SMP Discovery systems
22fefe7b09SThomas Petazzoni * - the mv78200 variant for MV78200 Discovery systems. This variant
23fefe7b09SThomas Petazzoni * turns the edge mask and level mask registers into CPU0 edge
24fefe7b09SThomas Petazzoni * mask/level mask registers, and adds CPU1 edge mask/level mask
25fefe7b09SThomas Petazzoni * registers.
26fefe7b09SThomas Petazzoni * - the armadaxp variant for Armada XP systems. This variant keeps
27fefe7b09SThomas Petazzoni * the normal cause/edge mask/level mask registers when the global
28fefe7b09SThomas Petazzoni * interrupts are used, but adds per-CPU cause/edge mask/level mask
29fefe7b09SThomas Petazzoni * registers n a separate memory area for the per-CPU GPIO
30fefe7b09SThomas Petazzoni * interrupts.
31fefe7b09SThomas Petazzoni */
32fefe7b09SThomas Petazzoni
33d2cabc4aSRalph Sennhauser #include <linux/bitops.h>
346ec015d6SGregory CLEMENT #include <linux/clk.h>
356ec015d6SGregory CLEMENT #include <linux/err.h>
36ba78d83bSLinus Walleij #include <linux/gpio/driver.h>
37ba78d83bSLinus Walleij #include <linux/gpio/consumer.h>
385923ea6cSLinus Walleij #include <linux/gpio/machine.h>
396ec015d6SGregory CLEMENT #include <linux/init.h>
406ec015d6SGregory CLEMENT #include <linux/io.h>
416ec015d6SGregory CLEMENT #include <linux/irq.h>
426ec015d6SGregory CLEMENT #include <linux/irqchip/chained_irq.h>
436ec015d6SGregory CLEMENT #include <linux/irqdomain.h>
44b6730b20SGregory CLEMENT #include <linux/mfd/syscon.h>
456ec015d6SGregory CLEMENT #include <linux/of_device.h>
466ec015d6SGregory CLEMENT #include <linux/pinctrl/consumer.h>
476ec015d6SGregory CLEMENT #include <linux/platform_device.h>
486ec015d6SGregory CLEMENT #include <linux/pwm.h>
492233bf7aSThomas Petazzoni #include <linux/regmap.h>
506ec015d6SGregory CLEMENT #include <linux/slab.h>
51fefe7b09SThomas Petazzoni
52fefe7b09SThomas Petazzoni /*
53fefe7b09SThomas Petazzoni * GPIO unit register offsets.
54fefe7b09SThomas Petazzoni */
55fefe7b09SThomas Petazzoni #define GPIO_OUT_OFF 0x0000
56fefe7b09SThomas Petazzoni #define GPIO_IO_CONF_OFF 0x0004
57fefe7b09SThomas Petazzoni #define GPIO_BLINK_EN_OFF 0x0008
58fefe7b09SThomas Petazzoni #define GPIO_IN_POL_OFF 0x000c
59fefe7b09SThomas Petazzoni #define GPIO_DATA_IN_OFF 0x0010
60fefe7b09SThomas Petazzoni #define GPIO_EDGE_CAUSE_OFF 0x0014
61fefe7b09SThomas Petazzoni #define GPIO_EDGE_MASK_OFF 0x0018
62fefe7b09SThomas Petazzoni #define GPIO_LEVEL_MASK_OFF 0x001c
63757642f9SAndrew Lunn #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
64757642f9SAndrew Lunn
65757642f9SAndrew Lunn /*
66757642f9SAndrew Lunn * PWM register offsets.
67757642f9SAndrew Lunn */
68757642f9SAndrew Lunn #define PWM_BLINK_ON_DURATION_OFF 0x0
69757642f9SAndrew Lunn #define PWM_BLINK_OFF_DURATION_OFF 0x4
7085b7d8abSBaruch Siach #define PWM_BLINK_COUNTER_B_OFF 0x8
71757642f9SAndrew Lunn
7285b7d8abSBaruch Siach /* Armada 8k variant gpios register offsets */
7385b7d8abSBaruch Siach #define AP80X_GPIO0_OFF_A8K 0x1040
7485b7d8abSBaruch Siach #define CP11X_GPIO0_OFF_A8K 0x100
7585b7d8abSBaruch Siach #define CP11X_GPIO1_OFF_A8K 0x140
76fefe7b09SThomas Petazzoni
77fefe7b09SThomas Petazzoni /* The MV78200 has per-CPU registers for edge mask and level mask */
78fefe7b09SThomas Petazzoni #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
79fefe7b09SThomas Petazzoni #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
80fefe7b09SThomas Petazzoni
817077f4ccSRalph Sennhauser /*
827077f4ccSRalph Sennhauser * The Armada XP has per-CPU registers for interrupt cause, interrupt
8364b19f6aSBaruch Siach * mask and interrupt level mask. Those are in percpu_regs range.
847077f4ccSRalph Sennhauser */
85fefe7b09SThomas Petazzoni #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
86fefe7b09SThomas Petazzoni #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
87fefe7b09SThomas Petazzoni #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
88fefe7b09SThomas Petazzoni
89fefe7b09SThomas Petazzoni #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
90fefe7b09SThomas Petazzoni #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
91fefe7b09SThomas Petazzoni #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
92b6730b20SGregory CLEMENT #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
93fefe7b09SThomas Petazzoni
94fefe7b09SThomas Petazzoni #define MVEBU_MAX_GPIO_PER_BANK 32
95fefe7b09SThomas Petazzoni
96757642f9SAndrew Lunn struct mvebu_pwm {
9748f32a83SBaruch Siach struct regmap *regs;
9885b7d8abSBaruch Siach u32 offset;
99757642f9SAndrew Lunn unsigned long clk_rate;
100757642f9SAndrew Lunn struct gpio_desc *gpiod;
101757642f9SAndrew Lunn struct pwm_chip chip;
102757642f9SAndrew Lunn spinlock_t lock;
103757642f9SAndrew Lunn struct mvebu_gpio_chip *mvchip;
104757642f9SAndrew Lunn
105757642f9SAndrew Lunn /* Used to preserve GPIO/PWM registers across suspend/resume */
106757642f9SAndrew Lunn u32 blink_select;
107757642f9SAndrew Lunn u32 blink_on_duration;
108757642f9SAndrew Lunn u32 blink_off_duration;
109757642f9SAndrew Lunn };
110757642f9SAndrew Lunn
111fefe7b09SThomas Petazzoni struct mvebu_gpio_chip {
112fefe7b09SThomas Petazzoni struct gpio_chip chip;
1132233bf7aSThomas Petazzoni struct regmap *regs;
114b6730b20SGregory CLEMENT u32 offset;
1152233bf7aSThomas Petazzoni struct regmap *percpu_regs;
116d5359226SDan Carpenter int irqbase;
117fefe7b09SThomas Petazzoni struct irq_domain *domain;
118fefe7b09SThomas Petazzoni int soc_variant;
119b5b7b487SThomas Petazzoni
120757642f9SAndrew Lunn /* Used for PWM support */
121757642f9SAndrew Lunn struct clk *clk;
122757642f9SAndrew Lunn struct mvebu_pwm *mvpwm;
123757642f9SAndrew Lunn
124a4319a61SAndrew Lunn /* Used to preserve GPIO registers across suspend/resume */
125b5b7b487SThomas Petazzoni u32 out_reg;
126b5b7b487SThomas Petazzoni u32 io_conf_reg;
127b5b7b487SThomas Petazzoni u32 blink_en_reg;
128b5b7b487SThomas Petazzoni u32 in_pol_reg;
129b5b7b487SThomas Petazzoni u32 edge_mask_regs[4];
130b5b7b487SThomas Petazzoni u32 level_mask_regs[4];
131fefe7b09SThomas Petazzoni };
132fefe7b09SThomas Petazzoni
133fefe7b09SThomas Petazzoni /*
134fefe7b09SThomas Petazzoni * Functions returning addresses of individual registers for a given
135fefe7b09SThomas Petazzoni * GPIO controller.
136fefe7b09SThomas Petazzoni */
137fefe7b09SThomas Petazzoni
mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)1382233bf7aSThomas Petazzoni static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
1392233bf7aSThomas Petazzoni struct regmap **map, unsigned int *offset)
140fefe7b09SThomas Petazzoni {
141fefe7b09SThomas Petazzoni int cpu;
142fefe7b09SThomas Petazzoni
143fefe7b09SThomas Petazzoni switch (mvchip->soc_variant) {
144fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ORION:
145fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_MV78200:
146b6730b20SGregory CLEMENT case MVEBU_GPIO_SOC_VARIANT_A8K:
1472233bf7aSThomas Petazzoni *map = mvchip->regs;
148b6730b20SGregory CLEMENT *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
1492233bf7aSThomas Petazzoni break;
150fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
151fefe7b09SThomas Petazzoni cpu = smp_processor_id();
1522233bf7aSThomas Petazzoni *map = mvchip->percpu_regs;
1532233bf7aSThomas Petazzoni *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
1542233bf7aSThomas Petazzoni break;
155fefe7b09SThomas Petazzoni default:
156fefe7b09SThomas Petazzoni BUG();
157fefe7b09SThomas Petazzoni }
158fefe7b09SThomas Petazzoni }
159fefe7b09SThomas Petazzoni
1602233bf7aSThomas Petazzoni static u32
mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip * mvchip)1612233bf7aSThomas Petazzoni mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
1622233bf7aSThomas Petazzoni {
1632233bf7aSThomas Petazzoni struct regmap *map;
1642233bf7aSThomas Petazzoni unsigned int offset;
1652233bf7aSThomas Petazzoni u32 val;
1662233bf7aSThomas Petazzoni
1672233bf7aSThomas Petazzoni mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
1682233bf7aSThomas Petazzoni regmap_read(map, offset, &val);
1692233bf7aSThomas Petazzoni
1702233bf7aSThomas Petazzoni return val;
1712233bf7aSThomas Petazzoni }
1722233bf7aSThomas Petazzoni
1732233bf7aSThomas Petazzoni static void
mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip * mvchip,u32 val)1742233bf7aSThomas Petazzoni mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
1752233bf7aSThomas Petazzoni {
1762233bf7aSThomas Petazzoni struct regmap *map;
1772233bf7aSThomas Petazzoni unsigned int offset;
1782233bf7aSThomas Petazzoni
1792233bf7aSThomas Petazzoni mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
1802233bf7aSThomas Petazzoni regmap_write(map, offset, val);
1812233bf7aSThomas Petazzoni }
1822233bf7aSThomas Petazzoni
1832233bf7aSThomas Petazzoni static inline void
mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)1842233bf7aSThomas Petazzoni mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
1852233bf7aSThomas Petazzoni struct regmap **map, unsigned int *offset)
186fefe7b09SThomas Petazzoni {
187fefe7b09SThomas Petazzoni int cpu;
188fefe7b09SThomas Petazzoni
189fefe7b09SThomas Petazzoni switch (mvchip->soc_variant) {
190fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ORION:
191b6730b20SGregory CLEMENT case MVEBU_GPIO_SOC_VARIANT_A8K:
1922233bf7aSThomas Petazzoni *map = mvchip->regs;
193b6730b20SGregory CLEMENT *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
1942233bf7aSThomas Petazzoni break;
195fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_MV78200:
196fefe7b09SThomas Petazzoni cpu = smp_processor_id();
1972233bf7aSThomas Petazzoni *map = mvchip->regs;
1982233bf7aSThomas Petazzoni *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
1992233bf7aSThomas Petazzoni break;
200fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
201fefe7b09SThomas Petazzoni cpu = smp_processor_id();
2022233bf7aSThomas Petazzoni *map = mvchip->percpu_regs;
2032233bf7aSThomas Petazzoni *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
2042233bf7aSThomas Petazzoni break;
205fefe7b09SThomas Petazzoni default:
206fefe7b09SThomas Petazzoni BUG();
207fefe7b09SThomas Petazzoni }
208fefe7b09SThomas Petazzoni }
209fefe7b09SThomas Petazzoni
2102233bf7aSThomas Petazzoni static u32
mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip * mvchip)2112233bf7aSThomas Petazzoni mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
2122233bf7aSThomas Petazzoni {
2132233bf7aSThomas Petazzoni struct regmap *map;
2142233bf7aSThomas Petazzoni unsigned int offset;
2152233bf7aSThomas Petazzoni u32 val;
2162233bf7aSThomas Petazzoni
2172233bf7aSThomas Petazzoni mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
2182233bf7aSThomas Petazzoni regmap_read(map, offset, &val);
2192233bf7aSThomas Petazzoni
2202233bf7aSThomas Petazzoni return val;
2212233bf7aSThomas Petazzoni }
2222233bf7aSThomas Petazzoni
2232233bf7aSThomas Petazzoni static void
mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip * mvchip,u32 val)2242233bf7aSThomas Petazzoni mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
2252233bf7aSThomas Petazzoni {
2262233bf7aSThomas Petazzoni struct regmap *map;
2272233bf7aSThomas Petazzoni unsigned int offset;
2282233bf7aSThomas Petazzoni
2292233bf7aSThomas Petazzoni mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
2302233bf7aSThomas Petazzoni regmap_write(map, offset, val);
2312233bf7aSThomas Petazzoni }
2322233bf7aSThomas Petazzoni
2332233bf7aSThomas Petazzoni static void
mvebu_gpioreg_level_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)2342233bf7aSThomas Petazzoni mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
2352233bf7aSThomas Petazzoni struct regmap **map, unsigned int *offset)
236fefe7b09SThomas Petazzoni {
237fefe7b09SThomas Petazzoni int cpu;
238fefe7b09SThomas Petazzoni
239fefe7b09SThomas Petazzoni switch (mvchip->soc_variant) {
240fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ORION:
241b6730b20SGregory CLEMENT case MVEBU_GPIO_SOC_VARIANT_A8K:
2422233bf7aSThomas Petazzoni *map = mvchip->regs;
243b6730b20SGregory CLEMENT *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
2442233bf7aSThomas Petazzoni break;
245fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_MV78200:
246fefe7b09SThomas Petazzoni cpu = smp_processor_id();
2472233bf7aSThomas Petazzoni *map = mvchip->regs;
2482233bf7aSThomas Petazzoni *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
2492233bf7aSThomas Petazzoni break;
250fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
251fefe7b09SThomas Petazzoni cpu = smp_processor_id();
2522233bf7aSThomas Petazzoni *map = mvchip->percpu_regs;
2532233bf7aSThomas Petazzoni *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
2542233bf7aSThomas Petazzoni break;
255fefe7b09SThomas Petazzoni default:
256fefe7b09SThomas Petazzoni BUG();
257fefe7b09SThomas Petazzoni }
258fefe7b09SThomas Petazzoni }
259fefe7b09SThomas Petazzoni
2602233bf7aSThomas Petazzoni static u32
mvebu_gpio_read_level_mask(struct mvebu_gpio_chip * mvchip)2612233bf7aSThomas Petazzoni mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
2622233bf7aSThomas Petazzoni {
2632233bf7aSThomas Petazzoni struct regmap *map;
2642233bf7aSThomas Petazzoni unsigned int offset;
2652233bf7aSThomas Petazzoni u32 val;
2662233bf7aSThomas Petazzoni
2672233bf7aSThomas Petazzoni mvebu_gpioreg_level_mask(mvchip, &map, &offset);
2682233bf7aSThomas Petazzoni regmap_read(map, offset, &val);
2692233bf7aSThomas Petazzoni
2702233bf7aSThomas Petazzoni return val;
2712233bf7aSThomas Petazzoni }
2722233bf7aSThomas Petazzoni
2732233bf7aSThomas Petazzoni static void
mvebu_gpio_write_level_mask(struct mvebu_gpio_chip * mvchip,u32 val)2742233bf7aSThomas Petazzoni mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
2752233bf7aSThomas Petazzoni {
2762233bf7aSThomas Petazzoni struct regmap *map;
2772233bf7aSThomas Petazzoni unsigned int offset;
2782233bf7aSThomas Petazzoni
2792233bf7aSThomas Petazzoni mvebu_gpioreg_level_mask(mvchip, &map, &offset);
2802233bf7aSThomas Petazzoni regmap_write(map, offset, val);
2812233bf7aSThomas Petazzoni }
2822233bf7aSThomas Petazzoni
283fefe7b09SThomas Petazzoni /*
28448f32a83SBaruch Siach * Functions returning offsets of individual registers for a given
285757642f9SAndrew Lunn * PWM controller.
286757642f9SAndrew Lunn */
mvebu_pwmreg_blink_on_duration(struct mvebu_pwm * mvpwm)28748f32a83SBaruch Siach static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
288757642f9SAndrew Lunn {
28985b7d8abSBaruch Siach return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
290757642f9SAndrew Lunn }
291757642f9SAndrew Lunn
mvebu_pwmreg_blink_off_duration(struct mvebu_pwm * mvpwm)29248f32a83SBaruch Siach static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
293757642f9SAndrew Lunn {
29485b7d8abSBaruch Siach return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
295757642f9SAndrew Lunn }
296757642f9SAndrew Lunn
297757642f9SAndrew Lunn /*
298fefe7b09SThomas Petazzoni * Functions implementing the gpio_chip methods
299fefe7b09SThomas Petazzoni */
mvebu_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)300d276de70SRalph Sennhauser static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
301fefe7b09SThomas Petazzoni {
302bbe76004SLinus Walleij struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
303fefe7b09SThomas Petazzoni
304b6730b20SGregory CLEMENT regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
3052233bf7aSThomas Petazzoni BIT(pin), value ? BIT(pin) : 0);
306fefe7b09SThomas Petazzoni }
307fefe7b09SThomas Petazzoni
mvebu_gpio_get(struct gpio_chip * chip,unsigned int pin)308d276de70SRalph Sennhauser static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
309fefe7b09SThomas Petazzoni {
310bbe76004SLinus Walleij struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
311fefe7b09SThomas Petazzoni u32 u;
312fefe7b09SThomas Petazzoni
313b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
3142233bf7aSThomas Petazzoni
3152233bf7aSThomas Petazzoni if (u & BIT(pin)) {
3162233bf7aSThomas Petazzoni u32 data_in, in_pol;
3172233bf7aSThomas Petazzoni
318b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
319b6730b20SGregory CLEMENT &data_in);
320b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
321b6730b20SGregory CLEMENT &in_pol);
3222233bf7aSThomas Petazzoni u = data_in ^ in_pol;
323fefe7b09SThomas Petazzoni } else {
324b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
325fefe7b09SThomas Petazzoni }
326fefe7b09SThomas Petazzoni
327fefe7b09SThomas Petazzoni return (u >> pin) & 1;
328fefe7b09SThomas Petazzoni }
329fefe7b09SThomas Petazzoni
mvebu_gpio_blink(struct gpio_chip * chip,unsigned int pin,int value)330d276de70SRalph Sennhauser static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
331d276de70SRalph Sennhauser int value)
332e9133760SJamie Lentin {
333bbe76004SLinus Walleij struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
334e9133760SJamie Lentin
335b6730b20SGregory CLEMENT regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
3362233bf7aSThomas Petazzoni BIT(pin), value ? BIT(pin) : 0);
337e9133760SJamie Lentin }
338e9133760SJamie Lentin
mvebu_gpio_direction_input(struct gpio_chip * chip,unsigned int pin)339d276de70SRalph Sennhauser static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
340fefe7b09SThomas Petazzoni {
341bbe76004SLinus Walleij struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
342fefe7b09SThomas Petazzoni int ret;
343fefe7b09SThomas Petazzoni
3447077f4ccSRalph Sennhauser /*
3457077f4ccSRalph Sennhauser * Check with the pinctrl driver whether this pin is usable as
3467077f4ccSRalph Sennhauser * an input GPIO
3477077f4ccSRalph Sennhauser */
348fefe7b09SThomas Petazzoni ret = pinctrl_gpio_direction_input(chip->base + pin);
349fefe7b09SThomas Petazzoni if (ret)
350fefe7b09SThomas Petazzoni return ret;
351fefe7b09SThomas Petazzoni
352b6730b20SGregory CLEMENT regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
35343a2dcecSGregory CLEMENT BIT(pin), BIT(pin));
354fefe7b09SThomas Petazzoni
355fefe7b09SThomas Petazzoni return 0;
356fefe7b09SThomas Petazzoni }
357fefe7b09SThomas Petazzoni
mvebu_gpio_direction_output(struct gpio_chip * chip,unsigned int pin,int value)358d276de70SRalph Sennhauser static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
359fefe7b09SThomas Petazzoni int value)
360fefe7b09SThomas Petazzoni {
361bbe76004SLinus Walleij struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
362fefe7b09SThomas Petazzoni int ret;
363fefe7b09SThomas Petazzoni
3647077f4ccSRalph Sennhauser /*
3657077f4ccSRalph Sennhauser * Check with the pinctrl driver whether this pin is usable as
3667077f4ccSRalph Sennhauser * an output GPIO
3677077f4ccSRalph Sennhauser */
368fefe7b09SThomas Petazzoni ret = pinctrl_gpio_direction_output(chip->base + pin);
369fefe7b09SThomas Petazzoni if (ret)
370fefe7b09SThomas Petazzoni return ret;
371fefe7b09SThomas Petazzoni
372e9133760SJamie Lentin mvebu_gpio_blink(chip, pin, 0);
373c57d75c0SThomas Petazzoni mvebu_gpio_set(chip, pin, value);
374c57d75c0SThomas Petazzoni
375b6730b20SGregory CLEMENT regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
3762233bf7aSThomas Petazzoni BIT(pin), 0);
377fefe7b09SThomas Petazzoni
378fefe7b09SThomas Petazzoni return 0;
379fefe7b09SThomas Petazzoni }
380fefe7b09SThomas Petazzoni
mvebu_gpio_get_direction(struct gpio_chip * chip,unsigned int pin)381e8dacf59SBaruch Siach static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
382e8dacf59SBaruch Siach {
383e8dacf59SBaruch Siach struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
384e8dacf59SBaruch Siach u32 u;
385e8dacf59SBaruch Siach
386e8dacf59SBaruch Siach regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
387e8dacf59SBaruch Siach
388e42615ecSMatti Vaittinen if (u & BIT(pin))
389e42615ecSMatti Vaittinen return GPIO_LINE_DIRECTION_IN;
390e42615ecSMatti Vaittinen
391e42615ecSMatti Vaittinen return GPIO_LINE_DIRECTION_OUT;
392e8dacf59SBaruch Siach }
393e8dacf59SBaruch Siach
mvebu_gpio_to_irq(struct gpio_chip * chip,unsigned int pin)394d276de70SRalph Sennhauser static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
395fefe7b09SThomas Petazzoni {
396bbe76004SLinus Walleij struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
397163ad364SRalph Sennhauser
398fefe7b09SThomas Petazzoni return irq_create_mapping(mvchip->domain, pin);
399fefe7b09SThomas Petazzoni }
400fefe7b09SThomas Petazzoni
401fefe7b09SThomas Petazzoni /*
402fefe7b09SThomas Petazzoni * Functions implementing the irq_chip methods
403fefe7b09SThomas Petazzoni */
mvebu_gpio_irq_ack(struct irq_data * d)404fefe7b09SThomas Petazzoni static void mvebu_gpio_irq_ack(struct irq_data *d)
405fefe7b09SThomas Petazzoni {
406fefe7b09SThomas Petazzoni struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
407fefe7b09SThomas Petazzoni struct mvebu_gpio_chip *mvchip = gc->private;
408812d4788SJason Gunthorpe u32 mask = d->mask;
409fefe7b09SThomas Petazzoni
410fefe7b09SThomas Petazzoni irq_gc_lock(gc);
4112233bf7aSThomas Petazzoni mvebu_gpio_write_edge_cause(mvchip, ~mask);
412fefe7b09SThomas Petazzoni irq_gc_unlock(gc);
413fefe7b09SThomas Petazzoni }
414fefe7b09SThomas Petazzoni
mvebu_gpio_edge_irq_mask(struct irq_data * d)415fefe7b09SThomas Petazzoni static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
416fefe7b09SThomas Petazzoni {
417fefe7b09SThomas Petazzoni struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
418fefe7b09SThomas Petazzoni struct mvebu_gpio_chip *mvchip = gc->private;
41961819549SGregory CLEMENT struct irq_chip_type *ct = irq_data_get_chip_type(d);
420812d4788SJason Gunthorpe u32 mask = d->mask;
421fefe7b09SThomas Petazzoni
422fefe7b09SThomas Petazzoni irq_gc_lock(gc);
42361819549SGregory CLEMENT ct->mask_cache_priv &= ~mask;
4242233bf7aSThomas Petazzoni mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
425fefe7b09SThomas Petazzoni irq_gc_unlock(gc);
426fefe7b09SThomas Petazzoni }
427fefe7b09SThomas Petazzoni
mvebu_gpio_edge_irq_unmask(struct irq_data * d)428fefe7b09SThomas Petazzoni static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
429fefe7b09SThomas Petazzoni {
430fefe7b09SThomas Petazzoni struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
431fefe7b09SThomas Petazzoni struct mvebu_gpio_chip *mvchip = gc->private;
43261819549SGregory CLEMENT struct irq_chip_type *ct = irq_data_get_chip_type(d);
433812d4788SJason Gunthorpe u32 mask = d->mask;
434fefe7b09SThomas Petazzoni
435fefe7b09SThomas Petazzoni irq_gc_lock(gc);
436d5331ec2SMaxim Kiselev mvebu_gpio_write_edge_cause(mvchip, ~mask);
43761819549SGregory CLEMENT ct->mask_cache_priv |= mask;
4382233bf7aSThomas Petazzoni mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
439fefe7b09SThomas Petazzoni irq_gc_unlock(gc);
440fefe7b09SThomas Petazzoni }
441fefe7b09SThomas Petazzoni
mvebu_gpio_level_irq_mask(struct irq_data * d)442fefe7b09SThomas Petazzoni static void mvebu_gpio_level_irq_mask(struct irq_data *d)
443fefe7b09SThomas Petazzoni {
444fefe7b09SThomas Petazzoni struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
445fefe7b09SThomas Petazzoni struct mvebu_gpio_chip *mvchip = gc->private;
44661819549SGregory CLEMENT struct irq_chip_type *ct = irq_data_get_chip_type(d);
447812d4788SJason Gunthorpe u32 mask = d->mask;
448fefe7b09SThomas Petazzoni
449fefe7b09SThomas Petazzoni irq_gc_lock(gc);
45061819549SGregory CLEMENT ct->mask_cache_priv &= ~mask;
4512233bf7aSThomas Petazzoni mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
452fefe7b09SThomas Petazzoni irq_gc_unlock(gc);
453fefe7b09SThomas Petazzoni }
454fefe7b09SThomas Petazzoni
mvebu_gpio_level_irq_unmask(struct irq_data * d)455fefe7b09SThomas Petazzoni static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
456fefe7b09SThomas Petazzoni {
457fefe7b09SThomas Petazzoni struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
458fefe7b09SThomas Petazzoni struct mvebu_gpio_chip *mvchip = gc->private;
45961819549SGregory CLEMENT struct irq_chip_type *ct = irq_data_get_chip_type(d);
460812d4788SJason Gunthorpe u32 mask = d->mask;
461fefe7b09SThomas Petazzoni
462fefe7b09SThomas Petazzoni irq_gc_lock(gc);
46361819549SGregory CLEMENT ct->mask_cache_priv |= mask;
4642233bf7aSThomas Petazzoni mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
465fefe7b09SThomas Petazzoni irq_gc_unlock(gc);
466fefe7b09SThomas Petazzoni }
467fefe7b09SThomas Petazzoni
468fefe7b09SThomas Petazzoni /*****************************************************************************
469fefe7b09SThomas Petazzoni * MVEBU GPIO IRQ
470fefe7b09SThomas Petazzoni *
471fefe7b09SThomas Petazzoni * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
472fefe7b09SThomas Petazzoni * value of the line or the opposite value.
473fefe7b09SThomas Petazzoni *
474fefe7b09SThomas Petazzoni * Level IRQ handlers: DATA_IN is used directly as cause register.
475fefe7b09SThomas Petazzoni * Interrupt are masked by LEVEL_MASK registers.
476fefe7b09SThomas Petazzoni * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
477fefe7b09SThomas Petazzoni * Interrupt are masked by EDGE_MASK registers.
478fefe7b09SThomas Petazzoni * Both-edge handlers: Similar to regular Edge handlers, but also swaps
479fefe7b09SThomas Petazzoni * the polarity to catch the next line transaction.
480fefe7b09SThomas Petazzoni * This is a race condition that might not perfectly
481fefe7b09SThomas Petazzoni * work on some use cases.
482fefe7b09SThomas Petazzoni *
483fefe7b09SThomas Petazzoni * Every eight GPIO lines are grouped (OR'ed) before going up to main
484fefe7b09SThomas Petazzoni * cause register.
485fefe7b09SThomas Petazzoni *
486fefe7b09SThomas Petazzoni * EDGE cause mask
487fefe7b09SThomas Petazzoni * data-in /--------| |-----| |----\
488fefe7b09SThomas Petazzoni * -----| |----- ---- to main cause reg
489fefe7b09SThomas Petazzoni * X \----------------| |----/
490fefe7b09SThomas Petazzoni * polarity LEVEL mask
491fefe7b09SThomas Petazzoni *
492fefe7b09SThomas Petazzoni ****************************************************************************/
493fefe7b09SThomas Petazzoni
mvebu_gpio_irq_set_type(struct irq_data * d,unsigned int type)494fefe7b09SThomas Petazzoni static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
495fefe7b09SThomas Petazzoni {
496fefe7b09SThomas Petazzoni struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
497fefe7b09SThomas Petazzoni struct irq_chip_type *ct = irq_data_get_chip_type(d);
498fefe7b09SThomas Petazzoni struct mvebu_gpio_chip *mvchip = gc->private;
499fefe7b09SThomas Petazzoni int pin;
500fefe7b09SThomas Petazzoni u32 u;
501fefe7b09SThomas Petazzoni
502fefe7b09SThomas Petazzoni pin = d->hwirq;
503fefe7b09SThomas Petazzoni
504b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
5052233bf7aSThomas Petazzoni if ((u & BIT(pin)) == 0)
506fefe7b09SThomas Petazzoni return -EINVAL;
507fefe7b09SThomas Petazzoni
508fefe7b09SThomas Petazzoni type &= IRQ_TYPE_SENSE_MASK;
509fefe7b09SThomas Petazzoni if (type == IRQ_TYPE_NONE)
510fefe7b09SThomas Petazzoni return -EINVAL;
511fefe7b09SThomas Petazzoni
512fefe7b09SThomas Petazzoni /* Check if we need to change chip and handler */
513fefe7b09SThomas Petazzoni if (!(ct->type & type))
514fefe7b09SThomas Petazzoni if (irq_setup_alt_chip(d, type))
515fefe7b09SThomas Petazzoni return -EINVAL;
516fefe7b09SThomas Petazzoni
517fefe7b09SThomas Petazzoni /*
518fefe7b09SThomas Petazzoni * Configure interrupt polarity.
519fefe7b09SThomas Petazzoni */
520fefe7b09SThomas Petazzoni switch (type) {
521fefe7b09SThomas Petazzoni case IRQ_TYPE_EDGE_RISING:
522fefe7b09SThomas Petazzoni case IRQ_TYPE_LEVEL_HIGH:
523b6730b20SGregory CLEMENT regmap_update_bits(mvchip->regs,
524b6730b20SGregory CLEMENT GPIO_IN_POL_OFF + mvchip->offset,
5252233bf7aSThomas Petazzoni BIT(pin), 0);
5267cf8c9f7SAxel Lin break;
527fefe7b09SThomas Petazzoni case IRQ_TYPE_EDGE_FALLING:
528fefe7b09SThomas Petazzoni case IRQ_TYPE_LEVEL_LOW:
529b6730b20SGregory CLEMENT regmap_update_bits(mvchip->regs,
530b6730b20SGregory CLEMENT GPIO_IN_POL_OFF + mvchip->offset,
53143a2dcecSGregory CLEMENT BIT(pin), BIT(pin));
5327cf8c9f7SAxel Lin break;
533fefe7b09SThomas Petazzoni case IRQ_TYPE_EDGE_BOTH: {
5342233bf7aSThomas Petazzoni u32 data_in, in_pol, val;
535fefe7b09SThomas Petazzoni
536b6730b20SGregory CLEMENT regmap_read(mvchip->regs,
537b6730b20SGregory CLEMENT GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
538b6730b20SGregory CLEMENT regmap_read(mvchip->regs,
539b6730b20SGregory CLEMENT GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
540fefe7b09SThomas Petazzoni
541fefe7b09SThomas Petazzoni /*
542fefe7b09SThomas Petazzoni * set initial polarity based on current input level
543fefe7b09SThomas Petazzoni */
5442233bf7aSThomas Petazzoni if ((data_in ^ in_pol) & BIT(pin))
5452233bf7aSThomas Petazzoni val = BIT(pin); /* falling */
546fefe7b09SThomas Petazzoni else
5472233bf7aSThomas Petazzoni val = 0; /* raising */
5482233bf7aSThomas Petazzoni
549b6730b20SGregory CLEMENT regmap_update_bits(mvchip->regs,
550b6730b20SGregory CLEMENT GPIO_IN_POL_OFF + mvchip->offset,
5512233bf7aSThomas Petazzoni BIT(pin), val);
5527cf8c9f7SAxel Lin break;
553fefe7b09SThomas Petazzoni }
554fefe7b09SThomas Petazzoni }
555fefe7b09SThomas Petazzoni return 0;
556fefe7b09SThomas Petazzoni }
557fefe7b09SThomas Petazzoni
mvebu_gpio_irq_handler(struct irq_desc * desc)558bd0b9ac4SThomas Gleixner static void mvebu_gpio_irq_handler(struct irq_desc *desc)
559fefe7b09SThomas Petazzoni {
560476f8b4cSJiang Liu struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
56101ca59f1SThomas Petazzoni struct irq_chip *chip = irq_desc_get_chip(desc);
5622233bf7aSThomas Petazzoni u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
563fefe7b09SThomas Petazzoni int i;
564fefe7b09SThomas Petazzoni
565fefe7b09SThomas Petazzoni if (mvchip == NULL)
566fefe7b09SThomas Petazzoni return;
567fefe7b09SThomas Petazzoni
56801ca59f1SThomas Petazzoni chained_irq_enter(chip, desc);
56901ca59f1SThomas Petazzoni
570b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
5712233bf7aSThomas Petazzoni level_mask = mvebu_gpio_read_level_mask(mvchip);
5722233bf7aSThomas Petazzoni edge_cause = mvebu_gpio_read_edge_cause(mvchip);
5732233bf7aSThomas Petazzoni edge_mask = mvebu_gpio_read_edge_mask(mvchip);
5742233bf7aSThomas Petazzoni
5753f13b6a2SGregory CLEMENT cause = (data_in & level_mask) | (edge_cause & edge_mask);
576fefe7b09SThomas Petazzoni
577fefe7b09SThomas Petazzoni for (i = 0; i < mvchip->chip.ngpio; i++) {
578fefe7b09SThomas Petazzoni int irq;
579fefe7b09SThomas Petazzoni
580812d4788SJason Gunthorpe irq = irq_find_mapping(mvchip->domain, i);
581fefe7b09SThomas Petazzoni
582d2cabc4aSRalph Sennhauser if (!(cause & BIT(i)))
583fefe7b09SThomas Petazzoni continue;
584fefe7b09SThomas Petazzoni
585fb90c22aSJavier Martinez Canillas type = irq_get_trigger_type(irq);
586fefe7b09SThomas Petazzoni if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
587fefe7b09SThomas Petazzoni /* Swap polarity (race with GPIO line) */
588fefe7b09SThomas Petazzoni u32 polarity;
589fefe7b09SThomas Petazzoni
590b6730b20SGregory CLEMENT regmap_read(mvchip->regs,
591b6730b20SGregory CLEMENT GPIO_IN_POL_OFF + mvchip->offset,
592b6730b20SGregory CLEMENT &polarity);
593d2cabc4aSRalph Sennhauser polarity ^= BIT(i);
594b6730b20SGregory CLEMENT regmap_write(mvchip->regs,
595b6730b20SGregory CLEMENT GPIO_IN_POL_OFF + mvchip->offset,
596b6730b20SGregory CLEMENT polarity);
597fefe7b09SThomas Petazzoni }
59801ca59f1SThomas Petazzoni
599fefe7b09SThomas Petazzoni generic_handle_irq(irq);
600fefe7b09SThomas Petazzoni }
60101ca59f1SThomas Petazzoni
60201ca59f1SThomas Petazzoni chained_irq_exit(chip, desc);
603fefe7b09SThomas Petazzoni }
604fefe7b09SThomas Petazzoni
60548f32a83SBaruch Siach static const struct regmap_config mvebu_gpio_regmap_config = {
60648f32a83SBaruch Siach .reg_bits = 32,
60748f32a83SBaruch Siach .reg_stride = 4,
60848f32a83SBaruch Siach .val_bits = 32,
60948f32a83SBaruch Siach .fast_io = true,
61048f32a83SBaruch Siach };
61148f32a83SBaruch Siach
612757642f9SAndrew Lunn /*
613757642f9SAndrew Lunn * Functions implementing the pwm_chip methods
614757642f9SAndrew Lunn */
to_mvebu_pwm(struct pwm_chip * chip)615757642f9SAndrew Lunn static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
616757642f9SAndrew Lunn {
617757642f9SAndrew Lunn return container_of(chip, struct mvebu_pwm, chip);
618757642f9SAndrew Lunn }
619757642f9SAndrew Lunn
mvebu_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)620757642f9SAndrew Lunn static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
621757642f9SAndrew Lunn {
622757642f9SAndrew Lunn struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
623757642f9SAndrew Lunn struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
624757642f9SAndrew Lunn struct gpio_desc *desc;
625757642f9SAndrew Lunn unsigned long flags;
626757642f9SAndrew Lunn int ret = 0;
627757642f9SAndrew Lunn
628757642f9SAndrew Lunn spin_lock_irqsave(&mvpwm->lock, flags);
629757642f9SAndrew Lunn
630757642f9SAndrew Lunn if (mvpwm->gpiod) {
631757642f9SAndrew Lunn ret = -EBUSY;
632757642f9SAndrew Lunn } else {
633ba78d83bSLinus Walleij desc = gpiochip_request_own_desc(&mvchip->chip,
6345923ea6cSLinus Walleij pwm->hwpwm, "mvebu-pwm",
6355923ea6cSLinus Walleij GPIO_ACTIVE_HIGH,
6365923ea6cSLinus Walleij GPIOD_OUT_LOW);
637ba78d83bSLinus Walleij if (IS_ERR(desc)) {
638ba78d83bSLinus Walleij ret = PTR_ERR(desc);
639757642f9SAndrew Lunn goto out;
640757642f9SAndrew Lunn }
641757642f9SAndrew Lunn
642757642f9SAndrew Lunn mvpwm->gpiod = desc;
643757642f9SAndrew Lunn }
644757642f9SAndrew Lunn out:
645757642f9SAndrew Lunn spin_unlock_irqrestore(&mvpwm->lock, flags);
646757642f9SAndrew Lunn return ret;
647757642f9SAndrew Lunn }
648757642f9SAndrew Lunn
mvebu_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)649757642f9SAndrew Lunn static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
650757642f9SAndrew Lunn {
651757642f9SAndrew Lunn struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
652757642f9SAndrew Lunn unsigned long flags;
653757642f9SAndrew Lunn
654757642f9SAndrew Lunn spin_lock_irqsave(&mvpwm->lock, flags);
655ba78d83bSLinus Walleij gpiochip_free_own_desc(mvpwm->gpiod);
656757642f9SAndrew Lunn mvpwm->gpiod = NULL;
657757642f9SAndrew Lunn spin_unlock_irqrestore(&mvpwm->lock, flags);
658757642f9SAndrew Lunn }
659757642f9SAndrew Lunn
mvebu_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)6606c452cffSUwe Kleine-König static int mvebu_pwm_get_state(struct pwm_chip *chip,
661757642f9SAndrew Lunn struct pwm_device *pwm,
6626c452cffSUwe Kleine-König struct pwm_state *state)
6636c452cffSUwe Kleine-König {
664757642f9SAndrew Lunn
665757642f9SAndrew Lunn struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
666757642f9SAndrew Lunn struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
667757642f9SAndrew Lunn unsigned long long val;
668757642f9SAndrew Lunn unsigned long flags;
669757642f9SAndrew Lunn u32 u;
670757642f9SAndrew Lunn
671757642f9SAndrew Lunn spin_lock_irqsave(&mvpwm->lock, flags);
672757642f9SAndrew Lunn
67348f32a83SBaruch Siach regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
6740b68d02bSBaruch Siach /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
6750b68d02bSBaruch Siach if (u > 0)
6760b68d02bSBaruch Siach val = u;
677757642f9SAndrew Lunn else
6780b68d02bSBaruch Siach val = UINT_MAX + 1ULL;
6790b68d02bSBaruch Siach state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
6800b68d02bSBaruch Siach mvpwm->clk_rate);
681757642f9SAndrew Lunn
68248f32a83SBaruch Siach regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
6830b68d02bSBaruch Siach /* period = on + off duration */
6840b68d02bSBaruch Siach if (u > 0)
6850b68d02bSBaruch Siach val += u;
686757642f9SAndrew Lunn else
6870b68d02bSBaruch Siach val += UINT_MAX + 1ULL;
6880b68d02bSBaruch Siach state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
689757642f9SAndrew Lunn
690b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
691757642f9SAndrew Lunn if (u)
692757642f9SAndrew Lunn state->enabled = true;
693757642f9SAndrew Lunn else
694757642f9SAndrew Lunn state->enabled = false;
695757642f9SAndrew Lunn
696757642f9SAndrew Lunn spin_unlock_irqrestore(&mvpwm->lock, flags);
6976c452cffSUwe Kleine-König
6986c452cffSUwe Kleine-König return 0;
699757642f9SAndrew Lunn }
700757642f9SAndrew Lunn
mvebu_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)701757642f9SAndrew Lunn static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
70271523d18SUwe Kleine-König const struct pwm_state *state)
703757642f9SAndrew Lunn {
704757642f9SAndrew Lunn struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
705757642f9SAndrew Lunn struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
706757642f9SAndrew Lunn unsigned long long val;
707757642f9SAndrew Lunn unsigned long flags;
708757642f9SAndrew Lunn unsigned int on, off;
709757642f9SAndrew Lunn
7103ecb1017SUwe Kleine-König if (state->polarity != PWM_POLARITY_NORMAL)
7113ecb1017SUwe Kleine-König return -EINVAL;
7123ecb1017SUwe Kleine-König
713757642f9SAndrew Lunn val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
714757642f9SAndrew Lunn do_div(val, NSEC_PER_SEC);
7150b68d02bSBaruch Siach if (val > UINT_MAX + 1ULL)
716757642f9SAndrew Lunn return -EINVAL;
7170b68d02bSBaruch Siach /*
7180b68d02bSBaruch Siach * Zero on/off values don't work as expected. Experimentation shows
7190b68d02bSBaruch Siach * that zero value is treated as 2^32. This behavior is not documented.
7200b68d02bSBaruch Siach */
7210b68d02bSBaruch Siach if (val == UINT_MAX + 1ULL)
7220b68d02bSBaruch Siach on = 0;
7230b68d02bSBaruch Siach else if (val)
724757642f9SAndrew Lunn on = val;
725757642f9SAndrew Lunn else
726757642f9SAndrew Lunn on = 1;
727757642f9SAndrew Lunn
728aa37e27fSBaruch Siach val = (unsigned long long) mvpwm->clk_rate * state->period;
729757642f9SAndrew Lunn do_div(val, NSEC_PER_SEC);
730aa37e27fSBaruch Siach val -= on;
7310b68d02bSBaruch Siach if (val > UINT_MAX + 1ULL)
732757642f9SAndrew Lunn return -EINVAL;
7330b68d02bSBaruch Siach if (val == UINT_MAX + 1ULL)
7340b68d02bSBaruch Siach off = 0;
7350b68d02bSBaruch Siach else if (val)
736757642f9SAndrew Lunn off = val;
737757642f9SAndrew Lunn else
738757642f9SAndrew Lunn off = 1;
739757642f9SAndrew Lunn
740757642f9SAndrew Lunn spin_lock_irqsave(&mvpwm->lock, flags);
741757642f9SAndrew Lunn
74248f32a83SBaruch Siach regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
74348f32a83SBaruch Siach regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
744757642f9SAndrew Lunn if (state->enabled)
745757642f9SAndrew Lunn mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
746757642f9SAndrew Lunn else
747757642f9SAndrew Lunn mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
748757642f9SAndrew Lunn
749757642f9SAndrew Lunn spin_unlock_irqrestore(&mvpwm->lock, flags);
750757642f9SAndrew Lunn
751757642f9SAndrew Lunn return 0;
752757642f9SAndrew Lunn }
753757642f9SAndrew Lunn
754757642f9SAndrew Lunn static const struct pwm_ops mvebu_pwm_ops = {
755757642f9SAndrew Lunn .request = mvebu_pwm_request,
756757642f9SAndrew Lunn .free = mvebu_pwm_free,
757757642f9SAndrew Lunn .get_state = mvebu_pwm_get_state,
758757642f9SAndrew Lunn .apply = mvebu_pwm_apply,
759757642f9SAndrew Lunn .owner = THIS_MODULE,
760757642f9SAndrew Lunn };
761757642f9SAndrew Lunn
mvebu_pwm_suspend(struct mvebu_gpio_chip * mvchip)762757642f9SAndrew Lunn static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
763757642f9SAndrew Lunn {
764757642f9SAndrew Lunn struct mvebu_pwm *mvpwm = mvchip->mvpwm;
765757642f9SAndrew Lunn
766b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
7672233bf7aSThomas Petazzoni &mvpwm->blink_select);
76848f32a83SBaruch Siach regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
76948f32a83SBaruch Siach &mvpwm->blink_on_duration);
77048f32a83SBaruch Siach regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
77148f32a83SBaruch Siach &mvpwm->blink_off_duration);
772757642f9SAndrew Lunn }
773757642f9SAndrew Lunn
mvebu_pwm_resume(struct mvebu_gpio_chip * mvchip)774757642f9SAndrew Lunn static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
775757642f9SAndrew Lunn {
776757642f9SAndrew Lunn struct mvebu_pwm *mvpwm = mvchip->mvpwm;
777757642f9SAndrew Lunn
778b6730b20SGregory CLEMENT regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
7792233bf7aSThomas Petazzoni mvpwm->blink_select);
78048f32a83SBaruch Siach regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
78148f32a83SBaruch Siach mvpwm->blink_on_duration);
78248f32a83SBaruch Siach regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
78348f32a83SBaruch Siach mvpwm->blink_off_duration);
784757642f9SAndrew Lunn }
785757642f9SAndrew Lunn
mvebu_pwm_probe(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip,int id)786757642f9SAndrew Lunn static int mvebu_pwm_probe(struct platform_device *pdev,
787757642f9SAndrew Lunn struct mvebu_gpio_chip *mvchip,
788757642f9SAndrew Lunn int id)
789757642f9SAndrew Lunn {
790757642f9SAndrew Lunn struct device *dev = &pdev->dev;
791757642f9SAndrew Lunn struct mvebu_pwm *mvpwm;
79248f32a83SBaruch Siach void __iomem *base;
79385b7d8abSBaruch Siach u32 offset;
794757642f9SAndrew Lunn u32 set;
795757642f9SAndrew Lunn
7964335417dSPali Rohár if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
7974335417dSPali Rohár int ret = of_property_read_u32(dev->of_node,
7984335417dSPali Rohár "marvell,pwm-offset", &offset);
7994335417dSPali Rohár if (ret < 0)
8004335417dSPali Rohár return 0;
8014335417dSPali Rohár } else {
80219c26d90SSascha Hauer /*
80319c26d90SSascha Hauer * There are only two sets of PWM configuration registers for
80419c26d90SSascha Hauer * all the GPIO lines on those SoCs which this driver reserves
80519c26d90SSascha Hauer * for the first two GPIO chips. So if the resource is missing
80619c26d90SSascha Hauer * we can't treat it as an error.
80719c26d90SSascha Hauer */
80819c26d90SSascha Hauer if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
80919c26d90SSascha Hauer return 0;
81085b7d8abSBaruch Siach offset = 0;
81185b7d8abSBaruch Siach }
81219c26d90SSascha Hauer
813c8da642dSUwe Kleine-König if (IS_ERR(mvchip->clk))
814c8da642dSUwe Kleine-König return PTR_ERR(mvchip->clk);
815c8da642dSUwe Kleine-König
81685b7d8abSBaruch Siach mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
81785b7d8abSBaruch Siach if (!mvpwm)
81885b7d8abSBaruch Siach return -ENOMEM;
81985b7d8abSBaruch Siach mvchip->mvpwm = mvpwm;
82085b7d8abSBaruch Siach mvpwm->mvchip = mvchip;
82185b7d8abSBaruch Siach mvpwm->offset = offset;
82285b7d8abSBaruch Siach
82385b7d8abSBaruch Siach if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
82485b7d8abSBaruch Siach mvpwm->regs = mvchip->regs;
82585b7d8abSBaruch Siach
82685b7d8abSBaruch Siach switch (mvchip->offset) {
82785b7d8abSBaruch Siach case AP80X_GPIO0_OFF_A8K:
82885b7d8abSBaruch Siach case CP11X_GPIO0_OFF_A8K:
82985b7d8abSBaruch Siach /* Blink counter A */
83085b7d8abSBaruch Siach set = 0;
83185b7d8abSBaruch Siach break;
83285b7d8abSBaruch Siach case CP11X_GPIO1_OFF_A8K:
83385b7d8abSBaruch Siach /* Blink counter B */
83485b7d8abSBaruch Siach set = U32_MAX;
83585b7d8abSBaruch Siach mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
83685b7d8abSBaruch Siach break;
83785b7d8abSBaruch Siach default:
83885b7d8abSBaruch Siach return -EINVAL;
83985b7d8abSBaruch Siach }
84085b7d8abSBaruch Siach } else {
84185b7d8abSBaruch Siach base = devm_platform_ioremap_resource_byname(pdev, "pwm");
84285b7d8abSBaruch Siach if (IS_ERR(base))
84385b7d8abSBaruch Siach return PTR_ERR(base);
84485b7d8abSBaruch Siach
84585b7d8abSBaruch Siach mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
84685b7d8abSBaruch Siach &mvebu_gpio_regmap_config);
84785b7d8abSBaruch Siach if (IS_ERR(mvpwm->regs))
84885b7d8abSBaruch Siach return PTR_ERR(mvpwm->regs);
84985b7d8abSBaruch Siach
850757642f9SAndrew Lunn /*
851757642f9SAndrew Lunn * Use set A for lines of GPIO chip with id 0, B for GPIO chip
852757642f9SAndrew Lunn * with id 1. Don't allow further GPIO chips to be used for PWM.
853757642f9SAndrew Lunn */
854757642f9SAndrew Lunn if (id == 0)
855757642f9SAndrew Lunn set = 0;
856757642f9SAndrew Lunn else if (id == 1)
857757642f9SAndrew Lunn set = U32_MAX;
858757642f9SAndrew Lunn else
859757642f9SAndrew Lunn return -EINVAL;
86085b7d8abSBaruch Siach }
86185b7d8abSBaruch Siach
862b6730b20SGregory CLEMENT regmap_write(mvchip->regs,
863c7d28ecaSLinus Torvalds GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
864757642f9SAndrew Lunn
865757642f9SAndrew Lunn mvpwm->clk_rate = clk_get_rate(mvchip->clk);
866757642f9SAndrew Lunn if (!mvpwm->clk_rate) {
867757642f9SAndrew Lunn dev_err(dev, "failed to get clock rate\n");
868757642f9SAndrew Lunn return -EINVAL;
869757642f9SAndrew Lunn }
870757642f9SAndrew Lunn
871757642f9SAndrew Lunn mvpwm->chip.dev = dev;
872757642f9SAndrew Lunn mvpwm->chip.ops = &mvebu_pwm_ops;
873757642f9SAndrew Lunn mvpwm->chip.npwm = mvchip->chip.ngpio;
874757642f9SAndrew Lunn
875757642f9SAndrew Lunn spin_lock_init(&mvpwm->lock);
876757642f9SAndrew Lunn
8771945063eSUwe Kleine-König return devm_pwmchip_add(dev, &mvpwm->chip);
878757642f9SAndrew Lunn }
879757642f9SAndrew Lunn
880a4ba5e1bSSimon Guinot #ifdef CONFIG_DEBUG_FS
881a4ba5e1bSSimon Guinot #include <linux/seq_file.h>
882a4ba5e1bSSimon Guinot
mvebu_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)883a4ba5e1bSSimon Guinot static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
884a4ba5e1bSSimon Guinot {
885bbe76004SLinus Walleij struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
886a4ba5e1bSSimon Guinot u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
88786661fd7SAndy Shevchenko const char *label;
888a4ba5e1bSSimon Guinot int i;
889a4ba5e1bSSimon Guinot
890b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
891b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
892b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
893b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
894b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
8952233bf7aSThomas Petazzoni cause = mvebu_gpio_read_edge_cause(mvchip);
8962233bf7aSThomas Petazzoni edg_msk = mvebu_gpio_read_edge_mask(mvchip);
8972233bf7aSThomas Petazzoni lvl_msk = mvebu_gpio_read_level_mask(mvchip);
898a4ba5e1bSSimon Guinot
89986661fd7SAndy Shevchenko for_each_requested_gpio(chip, i, label) {
900a4ba5e1bSSimon Guinot u32 msk;
901a4ba5e1bSSimon Guinot bool is_out;
902a4ba5e1bSSimon Guinot
903d2cabc4aSRalph Sennhauser msk = BIT(i);
904a4ba5e1bSSimon Guinot is_out = !(io_conf & msk);
905a4ba5e1bSSimon Guinot
906a4ba5e1bSSimon Guinot seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
907a4ba5e1bSSimon Guinot
908a4ba5e1bSSimon Guinot if (is_out) {
909a4ba5e1bSSimon Guinot seq_printf(s, " out %s %s\n",
910a4ba5e1bSSimon Guinot out & msk ? "hi" : "lo",
911a4ba5e1bSSimon Guinot blink & msk ? "(blink )" : "");
912a4ba5e1bSSimon Guinot continue;
913a4ba5e1bSSimon Guinot }
914a4ba5e1bSSimon Guinot
915a4ba5e1bSSimon Guinot seq_printf(s, " in %s (act %s) - IRQ",
916a4ba5e1bSSimon Guinot (data_in ^ in_pol) & msk ? "hi" : "lo",
917a4ba5e1bSSimon Guinot in_pol & msk ? "lo" : "hi");
918a4ba5e1bSSimon Guinot if (!((edg_msk | lvl_msk) & msk)) {
919a4319a61SAndrew Lunn seq_puts(s, " disabled\n");
920a4ba5e1bSSimon Guinot continue;
921a4ba5e1bSSimon Guinot }
922a4ba5e1bSSimon Guinot if (edg_msk & msk)
923a4319a61SAndrew Lunn seq_puts(s, " edge ");
924a4ba5e1bSSimon Guinot if (lvl_msk & msk)
925a4319a61SAndrew Lunn seq_puts(s, " level");
926a4ba5e1bSSimon Guinot seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
927a4ba5e1bSSimon Guinot }
928a4ba5e1bSSimon Guinot }
929a4ba5e1bSSimon Guinot #else
930a4ba5e1bSSimon Guinot #define mvebu_gpio_dbg_show NULL
931a4ba5e1bSSimon Guinot #endif
932a4ba5e1bSSimon Guinot
933271b17b6SJingoo Han static const struct of_device_id mvebu_gpio_of_match[] = {
934fefe7b09SThomas Petazzoni {
935fefe7b09SThomas Petazzoni .compatible = "marvell,orion-gpio",
936fefe7b09SThomas Petazzoni .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
937fefe7b09SThomas Petazzoni },
938fefe7b09SThomas Petazzoni {
939fefe7b09SThomas Petazzoni .compatible = "marvell,mv78200-gpio",
940fefe7b09SThomas Petazzoni .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
941fefe7b09SThomas Petazzoni },
942fefe7b09SThomas Petazzoni {
943fefe7b09SThomas Petazzoni .compatible = "marvell,armadaxp-gpio",
944fefe7b09SThomas Petazzoni .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
945fefe7b09SThomas Petazzoni },
946fefe7b09SThomas Petazzoni {
9476c7515c6SRalph Sennhauser .compatible = "marvell,armada-370-gpio",
948757642f9SAndrew Lunn .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
949757642f9SAndrew Lunn },
950757642f9SAndrew Lunn {
951b6730b20SGregory CLEMENT .compatible = "marvell,armada-8k-gpio",
952b6730b20SGregory CLEMENT .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
953b6730b20SGregory CLEMENT },
954b6730b20SGregory CLEMENT {
955fefe7b09SThomas Petazzoni /* sentinel */
956fefe7b09SThomas Petazzoni },
957fefe7b09SThomas Petazzoni };
958fefe7b09SThomas Petazzoni
mvebu_gpio_suspend(struct platform_device * pdev,pm_message_t state)959b5b7b487SThomas Petazzoni static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
960b5b7b487SThomas Petazzoni {
961b5b7b487SThomas Petazzoni struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
962b5b7b487SThomas Petazzoni int i;
963b5b7b487SThomas Petazzoni
964b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
965b6730b20SGregory CLEMENT &mvchip->out_reg);
966b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
967b6730b20SGregory CLEMENT &mvchip->io_conf_reg);
968b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
969b6730b20SGregory CLEMENT &mvchip->blink_en_reg);
970b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
971b6730b20SGregory CLEMENT &mvchip->in_pol_reg);
972b5b7b487SThomas Petazzoni
973b5b7b487SThomas Petazzoni switch (mvchip->soc_variant) {
974b5b7b487SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ORION:
975b6730b20SGregory CLEMENT case MVEBU_GPIO_SOC_VARIANT_A8K:
976b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
9772233bf7aSThomas Petazzoni &mvchip->edge_mask_regs[0]);
978b6730b20SGregory CLEMENT regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
9792233bf7aSThomas Petazzoni &mvchip->level_mask_regs[0]);
980b5b7b487SThomas Petazzoni break;
981b5b7b487SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_MV78200:
982b5b7b487SThomas Petazzoni for (i = 0; i < 2; i++) {
9832233bf7aSThomas Petazzoni regmap_read(mvchip->regs,
9842233bf7aSThomas Petazzoni GPIO_EDGE_MASK_MV78200_OFF(i),
9852233bf7aSThomas Petazzoni &mvchip->edge_mask_regs[i]);
9862233bf7aSThomas Petazzoni regmap_read(mvchip->regs,
9872233bf7aSThomas Petazzoni GPIO_LEVEL_MASK_MV78200_OFF(i),
9882233bf7aSThomas Petazzoni &mvchip->level_mask_regs[i]);
989b5b7b487SThomas Petazzoni }
990b5b7b487SThomas Petazzoni break;
991b5b7b487SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
992b5b7b487SThomas Petazzoni for (i = 0; i < 4; i++) {
9932233bf7aSThomas Petazzoni regmap_read(mvchip->regs,
9942233bf7aSThomas Petazzoni GPIO_EDGE_MASK_ARMADAXP_OFF(i),
9952233bf7aSThomas Petazzoni &mvchip->edge_mask_regs[i]);
9962233bf7aSThomas Petazzoni regmap_read(mvchip->regs,
9972233bf7aSThomas Petazzoni GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
9982233bf7aSThomas Petazzoni &mvchip->level_mask_regs[i]);
999b5b7b487SThomas Petazzoni }
1000b5b7b487SThomas Petazzoni break;
1001b5b7b487SThomas Petazzoni default:
1002b5b7b487SThomas Petazzoni BUG();
1003b5b7b487SThomas Petazzoni }
1004b5b7b487SThomas Petazzoni
10053101b1e4SUwe Kleine-König if (IS_REACHABLE(CONFIG_PWM))
1006757642f9SAndrew Lunn mvebu_pwm_suspend(mvchip);
1007757642f9SAndrew Lunn
1008b5b7b487SThomas Petazzoni return 0;
1009b5b7b487SThomas Petazzoni }
1010b5b7b487SThomas Petazzoni
mvebu_gpio_resume(struct platform_device * pdev)1011b5b7b487SThomas Petazzoni static int mvebu_gpio_resume(struct platform_device *pdev)
1012b5b7b487SThomas Petazzoni {
1013b5b7b487SThomas Petazzoni struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
1014b5b7b487SThomas Petazzoni int i;
1015b5b7b487SThomas Petazzoni
1016b6730b20SGregory CLEMENT regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
1017b6730b20SGregory CLEMENT mvchip->out_reg);
1018b6730b20SGregory CLEMENT regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
1019b6730b20SGregory CLEMENT mvchip->io_conf_reg);
1020b6730b20SGregory CLEMENT regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
1021b6730b20SGregory CLEMENT mvchip->blink_en_reg);
1022b6730b20SGregory CLEMENT regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
1023b6730b20SGregory CLEMENT mvchip->in_pol_reg);
1024b5b7b487SThomas Petazzoni
1025b5b7b487SThomas Petazzoni switch (mvchip->soc_variant) {
1026b5b7b487SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ORION:
1027b6730b20SGregory CLEMENT case MVEBU_GPIO_SOC_VARIANT_A8K:
1028b6730b20SGregory CLEMENT regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
10292233bf7aSThomas Petazzoni mvchip->edge_mask_regs[0]);
1030b6730b20SGregory CLEMENT regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
10312233bf7aSThomas Petazzoni mvchip->level_mask_regs[0]);
1032b5b7b487SThomas Petazzoni break;
1033b5b7b487SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_MV78200:
1034b5b7b487SThomas Petazzoni for (i = 0; i < 2; i++) {
10352233bf7aSThomas Petazzoni regmap_write(mvchip->regs,
10362233bf7aSThomas Petazzoni GPIO_EDGE_MASK_MV78200_OFF(i),
10372233bf7aSThomas Petazzoni mvchip->edge_mask_regs[i]);
10382233bf7aSThomas Petazzoni regmap_write(mvchip->regs,
10392233bf7aSThomas Petazzoni GPIO_LEVEL_MASK_MV78200_OFF(i),
10402233bf7aSThomas Petazzoni mvchip->level_mask_regs[i]);
1041b5b7b487SThomas Petazzoni }
1042b5b7b487SThomas Petazzoni break;
1043b5b7b487SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1044b5b7b487SThomas Petazzoni for (i = 0; i < 4; i++) {
10452233bf7aSThomas Petazzoni regmap_write(mvchip->regs,
10462233bf7aSThomas Petazzoni GPIO_EDGE_MASK_ARMADAXP_OFF(i),
10472233bf7aSThomas Petazzoni mvchip->edge_mask_regs[i]);
10482233bf7aSThomas Petazzoni regmap_write(mvchip->regs,
10492233bf7aSThomas Petazzoni GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
10502233bf7aSThomas Petazzoni mvchip->level_mask_regs[i]);
1051b5b7b487SThomas Petazzoni }
1052b5b7b487SThomas Petazzoni break;
1053b5b7b487SThomas Petazzoni default:
1054b5b7b487SThomas Petazzoni BUG();
1055b5b7b487SThomas Petazzoni }
1056b5b7b487SThomas Petazzoni
10573101b1e4SUwe Kleine-König if (IS_REACHABLE(CONFIG_PWM))
1058757642f9SAndrew Lunn mvebu_pwm_resume(mvchip);
1059757642f9SAndrew Lunn
1060b5b7b487SThomas Petazzoni return 0;
1061b5b7b487SThomas Petazzoni }
1062b5b7b487SThomas Petazzoni
mvebu_gpio_probe_raw(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1063b6730b20SGregory CLEMENT static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1064b6730b20SGregory CLEMENT struct mvebu_gpio_chip *mvchip)
1065b6730b20SGregory CLEMENT {
1066b6730b20SGregory CLEMENT void __iomem *base;
1067b6730b20SGregory CLEMENT
1068dc02a0caSEnrico Weigelt, metux IT consult base = devm_platform_ioremap_resource(pdev, 0);
1069b6730b20SGregory CLEMENT if (IS_ERR(base))
1070b6730b20SGregory CLEMENT return PTR_ERR(base);
1071b6730b20SGregory CLEMENT
1072b6730b20SGregory CLEMENT mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1073b6730b20SGregory CLEMENT &mvebu_gpio_regmap_config);
1074b6730b20SGregory CLEMENT if (IS_ERR(mvchip->regs))
1075b6730b20SGregory CLEMENT return PTR_ERR(mvchip->regs);
1076b6730b20SGregory CLEMENT
1077b6730b20SGregory CLEMENT /*
1078b6730b20SGregory CLEMENT * For the legacy SoCs, the regmap directly maps to the GPIO
1079b6730b20SGregory CLEMENT * registers, so no offset is needed.
1080b6730b20SGregory CLEMENT */
1081b6730b20SGregory CLEMENT mvchip->offset = 0;
1082b6730b20SGregory CLEMENT
1083b6730b20SGregory CLEMENT /*
1084b6730b20SGregory CLEMENT * The Armada XP has a second range of registers for the
1085b6730b20SGregory CLEMENT * per-CPU registers
1086b6730b20SGregory CLEMENT */
1087b6730b20SGregory CLEMENT if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1088dc02a0caSEnrico Weigelt, metux IT consult base = devm_platform_ioremap_resource(pdev, 1);
1089b6730b20SGregory CLEMENT if (IS_ERR(base))
1090b6730b20SGregory CLEMENT return PTR_ERR(base);
1091b6730b20SGregory CLEMENT
1092b6730b20SGregory CLEMENT mvchip->percpu_regs =
1093b6730b20SGregory CLEMENT devm_regmap_init_mmio(&pdev->dev, base,
1094b6730b20SGregory CLEMENT &mvebu_gpio_regmap_config);
1095b6730b20SGregory CLEMENT if (IS_ERR(mvchip->percpu_regs))
1096b6730b20SGregory CLEMENT return PTR_ERR(mvchip->percpu_regs);
1097b6730b20SGregory CLEMENT }
1098b6730b20SGregory CLEMENT
1099b6730b20SGregory CLEMENT return 0;
1100b6730b20SGregory CLEMENT }
1101b6730b20SGregory CLEMENT
mvebu_gpio_probe_syscon(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1102b6730b20SGregory CLEMENT static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1103b6730b20SGregory CLEMENT struct mvebu_gpio_chip *mvchip)
1104b6730b20SGregory CLEMENT {
1105b6730b20SGregory CLEMENT mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1106b6730b20SGregory CLEMENT if (IS_ERR(mvchip->regs))
1107b6730b20SGregory CLEMENT return PTR_ERR(mvchip->regs);
1108b6730b20SGregory CLEMENT
1109b6730b20SGregory CLEMENT if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1110b6730b20SGregory CLEMENT return -EINVAL;
1111b6730b20SGregory CLEMENT
1112b6730b20SGregory CLEMENT return 0;
1113b6730b20SGregory CLEMENT }
1114b6730b20SGregory CLEMENT
mvebu_gpio_remove_irq_domain(void * data)1115*644ee702SBartosz Golaszewski static void mvebu_gpio_remove_irq_domain(void *data)
1116*644ee702SBartosz Golaszewski {
1117*644ee702SBartosz Golaszewski struct irq_domain *domain = data;
1118*644ee702SBartosz Golaszewski
1119*644ee702SBartosz Golaszewski irq_domain_remove(domain);
1120*644ee702SBartosz Golaszewski }
1121*644ee702SBartosz Golaszewski
mvebu_gpio_probe(struct platform_device * pdev)11223836309dSBill Pemberton static int mvebu_gpio_probe(struct platform_device *pdev)
1123fefe7b09SThomas Petazzoni {
1124fefe7b09SThomas Petazzoni struct mvebu_gpio_chip *mvchip;
1125fefe7b09SThomas Petazzoni const struct of_device_id *match;
1126fefe7b09SThomas Petazzoni struct device_node *np = pdev->dev.of_node;
1127fefe7b09SThomas Petazzoni struct irq_chip_generic *gc;
1128fefe7b09SThomas Petazzoni struct irq_chip_type *ct;
1129fefe7b09SThomas Petazzoni unsigned int ngpios;
1130812d4788SJason Gunthorpe bool have_irqs;
1131fefe7b09SThomas Petazzoni int soc_variant;
1132fefe7b09SThomas Petazzoni int i, cpu, id;
1133f1d2d081SAndrew Lunn int err;
1134fefe7b09SThomas Petazzoni
1135fefe7b09SThomas Petazzoni match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1136fefe7b09SThomas Petazzoni if (match)
1137f0d50460SRussell King soc_variant = (unsigned long) match->data;
1138fefe7b09SThomas Petazzoni else
1139fefe7b09SThomas Petazzoni soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1140fefe7b09SThomas Petazzoni
1141812d4788SJason Gunthorpe /* Some gpio controllers do not provide irq support */
11420c21639fSPeng Fan err = platform_irq_count(pdev);
11430c21639fSPeng Fan if (err < 0)
11440c21639fSPeng Fan return err;
11450c21639fSPeng Fan
11460c21639fSPeng Fan have_irqs = err != 0;
1147812d4788SJason Gunthorpe
1148a4319a61SAndrew Lunn mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1149a4319a61SAndrew Lunn GFP_KERNEL);
11506c8365f6SJingoo Han if (!mvchip)
1151fefe7b09SThomas Petazzoni return -ENOMEM;
1152fefe7b09SThomas Petazzoni
1153b5b7b487SThomas Petazzoni platform_set_drvdata(pdev, mvchip);
1154b5b7b487SThomas Petazzoni
1155fefe7b09SThomas Petazzoni if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1156fefe7b09SThomas Petazzoni dev_err(&pdev->dev, "Missing ngpios OF property\n");
1157fefe7b09SThomas Petazzoni return -ENODEV;
1158fefe7b09SThomas Petazzoni }
1159fefe7b09SThomas Petazzoni
1160fefe7b09SThomas Petazzoni id = of_alias_get_id(pdev->dev.of_node, "gpio");
1161fefe7b09SThomas Petazzoni if (id < 0) {
1162fefe7b09SThomas Petazzoni dev_err(&pdev->dev, "Couldn't get OF id\n");
1163fefe7b09SThomas Petazzoni return id;
1164fefe7b09SThomas Petazzoni }
1165fefe7b09SThomas Petazzoni
1166757642f9SAndrew Lunn mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1167de88747fSAndrew Lunn /* Not all SoCs require a clock.*/
1168757642f9SAndrew Lunn if (!IS_ERR(mvchip->clk))
1169757642f9SAndrew Lunn clk_prepare_enable(mvchip->clk);
1170de88747fSAndrew Lunn
1171fefe7b09SThomas Petazzoni mvchip->soc_variant = soc_variant;
1172fefe7b09SThomas Petazzoni mvchip->chip.label = dev_name(&pdev->dev);
117358383c78SLinus Walleij mvchip->chip.parent = &pdev->dev;
1174203f0daaSJonas Gorski mvchip->chip.request = gpiochip_generic_request;
1175203f0daaSJonas Gorski mvchip->chip.free = gpiochip_generic_free;
1176e8dacf59SBaruch Siach mvchip->chip.get_direction = mvebu_gpio_get_direction;
1177fefe7b09SThomas Petazzoni mvchip->chip.direction_input = mvebu_gpio_direction_input;
1178fefe7b09SThomas Petazzoni mvchip->chip.get = mvebu_gpio_get;
1179fefe7b09SThomas Petazzoni mvchip->chip.direction_output = mvebu_gpio_direction_output;
1180fefe7b09SThomas Petazzoni mvchip->chip.set = mvebu_gpio_set;
1181812d4788SJason Gunthorpe if (have_irqs)
1182fefe7b09SThomas Petazzoni mvchip->chip.to_irq = mvebu_gpio_to_irq;
1183fefe7b09SThomas Petazzoni mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1184fefe7b09SThomas Petazzoni mvchip->chip.ngpio = ngpios;
11859fb1f39eSLinus Walleij mvchip->chip.can_sleep = false;
1186a4ba5e1bSSimon Guinot mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1187fefe7b09SThomas Petazzoni
1188b6730b20SGregory CLEMENT if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1189b6730b20SGregory CLEMENT err = mvebu_gpio_probe_syscon(pdev, mvchip);
1190b6730b20SGregory CLEMENT else
1191b6730b20SGregory CLEMENT err = mvebu_gpio_probe_raw(pdev, mvchip);
1192fefe7b09SThomas Petazzoni
1193b6730b20SGregory CLEMENT if (err)
1194b6730b20SGregory CLEMENT return err;
1195fefe7b09SThomas Petazzoni
1196fefe7b09SThomas Petazzoni /*
1197fefe7b09SThomas Petazzoni * Mask and clear GPIO interrupts.
1198fefe7b09SThomas Petazzoni */
1199fefe7b09SThomas Petazzoni switch (soc_variant) {
1200fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ORION:
1201b6730b20SGregory CLEMENT case MVEBU_GPIO_SOC_VARIANT_A8K:
1202b6730b20SGregory CLEMENT regmap_write(mvchip->regs,
1203b6730b20SGregory CLEMENT GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1204b6730b20SGregory CLEMENT regmap_write(mvchip->regs,
1205b6730b20SGregory CLEMENT GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1206b6730b20SGregory CLEMENT regmap_write(mvchip->regs,
1207b6730b20SGregory CLEMENT GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1208fefe7b09SThomas Petazzoni break;
1209fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_MV78200:
12102233bf7aSThomas Petazzoni regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1211fefe7b09SThomas Petazzoni for (cpu = 0; cpu < 2; cpu++) {
12122233bf7aSThomas Petazzoni regmap_write(mvchip->regs,
12132233bf7aSThomas Petazzoni GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
12142233bf7aSThomas Petazzoni regmap_write(mvchip->regs,
12152233bf7aSThomas Petazzoni GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1216fefe7b09SThomas Petazzoni }
1217fefe7b09SThomas Petazzoni break;
1218fefe7b09SThomas Petazzoni case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
12192233bf7aSThomas Petazzoni regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
12202233bf7aSThomas Petazzoni regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
12212233bf7aSThomas Petazzoni regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1222fefe7b09SThomas Petazzoni for (cpu = 0; cpu < 4; cpu++) {
12232233bf7aSThomas Petazzoni regmap_write(mvchip->percpu_regs,
12242233bf7aSThomas Petazzoni GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
12252233bf7aSThomas Petazzoni regmap_write(mvchip->percpu_regs,
12262233bf7aSThomas Petazzoni GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
12272233bf7aSThomas Petazzoni regmap_write(mvchip->percpu_regs,
12282233bf7aSThomas Petazzoni GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1229fefe7b09SThomas Petazzoni }
1230fefe7b09SThomas Petazzoni break;
1231fefe7b09SThomas Petazzoni default:
1232fefe7b09SThomas Petazzoni BUG();
1233fefe7b09SThomas Petazzoni }
1234fefe7b09SThomas Petazzoni
123500b9ab4aSLaxman Dewangan devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1236fefe7b09SThomas Petazzoni
12377ee1a01eSBaruch Siach /* Some MVEBU SoCs have simple PWM support for GPIO lines */
12383101b1e4SUwe Kleine-König if (IS_REACHABLE(CONFIG_PWM)) {
12397ee1a01eSBaruch Siach err = mvebu_pwm_probe(pdev, mvchip, id);
12407ee1a01eSBaruch Siach if (err)
12417ee1a01eSBaruch Siach return err;
12427ee1a01eSBaruch Siach }
12437ee1a01eSBaruch Siach
1244fefe7b09SThomas Petazzoni /* Some gpio controllers do not provide irq support */
1245812d4788SJason Gunthorpe if (!have_irqs)
1246fefe7b09SThomas Petazzoni return 0;
1247fefe7b09SThomas Petazzoni
1248812d4788SJason Gunthorpe mvchip->domain =
1249812d4788SJason Gunthorpe irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1250812d4788SJason Gunthorpe if (!mvchip->domain) {
1251812d4788SJason Gunthorpe dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1252812d4788SJason Gunthorpe mvchip->chip.label);
12531945063eSUwe Kleine-König return -ENODEV;
1254fefe7b09SThomas Petazzoni }
1255fefe7b09SThomas Petazzoni
1256*644ee702SBartosz Golaszewski err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain,
1257*644ee702SBartosz Golaszewski mvchip->domain);
1258*644ee702SBartosz Golaszewski if (err)
1259*644ee702SBartosz Golaszewski return err;
1260*644ee702SBartosz Golaszewski
1261812d4788SJason Gunthorpe err = irq_alloc_domain_generic_chips(
1262812d4788SJason Gunthorpe mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1263812d4788SJason Gunthorpe IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1264812d4788SJason Gunthorpe if (err) {
1265812d4788SJason Gunthorpe dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1266812d4788SJason Gunthorpe mvchip->chip.label);
1267*644ee702SBartosz Golaszewski return err;
1268fefe7b09SThomas Petazzoni }
1269fefe7b09SThomas Petazzoni
1270899c37edSRalph Sennhauser /*
1271899c37edSRalph Sennhauser * NOTE: The common accessors cannot be used because of the percpu
1272812d4788SJason Gunthorpe * access to the mask registers
1273812d4788SJason Gunthorpe */
1274812d4788SJason Gunthorpe gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1275fefe7b09SThomas Petazzoni gc->private = mvchip;
1276fefe7b09SThomas Petazzoni ct = &gc->chip_types[0];
1277fefe7b09SThomas Petazzoni ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1278fefe7b09SThomas Petazzoni ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1279fefe7b09SThomas Petazzoni ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1280fefe7b09SThomas Petazzoni ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1281fefe7b09SThomas Petazzoni ct->chip.name = mvchip->chip.label;
1282fefe7b09SThomas Petazzoni
1283fefe7b09SThomas Petazzoni ct = &gc->chip_types[1];
1284fefe7b09SThomas Petazzoni ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1285fefe7b09SThomas Petazzoni ct->chip.irq_ack = mvebu_gpio_irq_ack;
1286fefe7b09SThomas Petazzoni ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1287fefe7b09SThomas Petazzoni ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1288fefe7b09SThomas Petazzoni ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1289fefe7b09SThomas Petazzoni ct->handler = handle_edge_irq;
1290fefe7b09SThomas Petazzoni ct->chip.name = mvchip->chip.label;
1291fefe7b09SThomas Petazzoni
1292899c37edSRalph Sennhauser /*
1293899c37edSRalph Sennhauser * Setup the interrupt handlers. Each chip can have up to 4
1294812d4788SJason Gunthorpe * interrupt handlers, with each handler dealing with 8 GPIO
1295812d4788SJason Gunthorpe * pins.
1296812d4788SJason Gunthorpe */
1297812d4788SJason Gunthorpe for (i = 0; i < 4; i++) {
1298525b0858SChris Packham int irq = platform_get_irq_optional(pdev, i);
1299fefe7b09SThomas Petazzoni
1300812d4788SJason Gunthorpe if (irq < 0)
1301812d4788SJason Gunthorpe continue;
1302812d4788SJason Gunthorpe irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1303fefe7b09SThomas Petazzoni mvchip);
1304fefe7b09SThomas Petazzoni }
1305fefe7b09SThomas Petazzoni
1306fefe7b09SThomas Petazzoni return 0;
1307fefe7b09SThomas Petazzoni }
1308fefe7b09SThomas Petazzoni
1309fefe7b09SThomas Petazzoni static struct platform_driver mvebu_gpio_driver = {
1310fefe7b09SThomas Petazzoni .driver = {
1311fefe7b09SThomas Petazzoni .name = "mvebu-gpio",
1312fefe7b09SThomas Petazzoni .of_match_table = mvebu_gpio_of_match,
1313fefe7b09SThomas Petazzoni },
1314fefe7b09SThomas Petazzoni .probe = mvebu_gpio_probe,
1315b5b7b487SThomas Petazzoni .suspend = mvebu_gpio_suspend,
1316b5b7b487SThomas Petazzoni .resume = mvebu_gpio_resume,
1317fefe7b09SThomas Petazzoni };
1318ed329f3aSPaul Gortmaker builtin_platform_driver(mvebu_gpio_driver);
1319