Lines Matching +full:cpu +full:- +full:offset
2 * Allwinner CPU Configuration Module emulation
26 #include "qemu/error-report.h"
28 #include "hw/core/cpu.h"
29 #include "target/arm/arm-powerctl.h"
30 #include "target/arm/cpu.h"
31 #include "hw/misc/allwinner-cpucfg.h"
37 REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
38 REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
39 REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
40 REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
41 REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */
42 REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */
43 REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */
44 REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */
45 REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */
46 REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */
47 REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */
48 REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */
49 REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */
50 REG_CLK_GATING = 0x0144, /* CPU Clock Gating */
55 REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */
56 REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */
57 REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */
85 trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr); in allwinner_cpucfg_cpu_reset()
95 bool target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64); in allwinner_cpucfg_cpu_reset()
97 ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0, in allwinner_cpucfg_cpu_reset()
100 error_report("%s: failed to bring up CPU %d: err %d", in allwinner_cpucfg_cpu_reset()
106 static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset, in allwinner_cpucfg_read() argument
112 switch (offset) { in allwinner_cpucfg_read()
114 case REG_CPU_SYS_RST: /* CPU System Reset */ in allwinner_cpucfg_read()
117 case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ in allwinner_cpucfg_read()
118 case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ in allwinner_cpucfg_read()
119 case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ in allwinner_cpucfg_read()
120 case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ in allwinner_cpucfg_read()
123 case REG_CPU0_CTRL: /* CPU#0 Control */ in allwinner_cpucfg_read()
124 case REG_CPU1_CTRL: /* CPU#1 Control */ in allwinner_cpucfg_read()
125 case REG_CPU2_CTRL: /* CPU#2 Control */ in allwinner_cpucfg_read()
126 case REG_CPU3_CTRL: /* CPU#3 Control */ in allwinner_cpucfg_read()
129 case REG_CPU0_STATUS: /* CPU#0 Status */ in allwinner_cpucfg_read()
130 case REG_CPU1_STATUS: /* CPU#1 Status */ in allwinner_cpucfg_read()
131 case REG_CPU2_STATUS: /* CPU#2 Status */ in allwinner_cpucfg_read()
132 case REG_CPU3_STATUS: /* CPU#3 Status */ in allwinner_cpucfg_read()
135 case REG_CLK_GATING: /* CPU Clock Gating */ in allwinner_cpucfg_read()
139 val = s->gen_ctrl; in allwinner_cpucfg_read()
142 val = s->super_standby; in allwinner_cpucfg_read()
145 val = s->entry_addr; in allwinner_cpucfg_read()
148 case REG_CNT64_CTRL: /* 64-bit Counter Control */ in allwinner_cpucfg_read()
149 case REG_CNT64_LOW: /* 64-bit Counter Low */ in allwinner_cpucfg_read()
150 case REG_CNT64_HIGH: /* 64-bit Counter High */ in allwinner_cpucfg_read()
152 __func__, (uint32_t)offset); in allwinner_cpucfg_read()
155 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", in allwinner_cpucfg_read()
156 __func__, (uint32_t)offset); in allwinner_cpucfg_read()
160 trace_allwinner_cpucfg_read(offset, val, size); in allwinner_cpucfg_read()
165 static void allwinner_cpucfg_write(void *opaque, hwaddr offset, in allwinner_cpucfg_write() argument
170 trace_allwinner_cpucfg_write(offset, val, size); in allwinner_cpucfg_write()
172 switch (offset) { in allwinner_cpucfg_write()
174 case REG_CPU_SYS_RST: /* CPU System Reset */ in allwinner_cpucfg_write()
176 case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ in allwinner_cpucfg_write()
177 case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ in allwinner_cpucfg_write()
178 case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ in allwinner_cpucfg_write()
179 case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ in allwinner_cpucfg_write()
181 allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> 6); in allwinner_cpucfg_write()
184 case REG_CPU0_CTRL: /* CPU#0 Control */ in allwinner_cpucfg_write()
185 case REG_CPU1_CTRL: /* CPU#1 Control */ in allwinner_cpucfg_write()
186 case REG_CPU2_CTRL: /* CPU#2 Control */ in allwinner_cpucfg_write()
187 case REG_CPU3_CTRL: /* CPU#3 Control */ in allwinner_cpucfg_write()
188 case REG_CPU0_STATUS: /* CPU#0 Status */ in allwinner_cpucfg_write()
189 case REG_CPU1_STATUS: /* CPU#1 Status */ in allwinner_cpucfg_write()
190 case REG_CPU2_STATUS: /* CPU#2 Status */ in allwinner_cpucfg_write()
191 case REG_CPU3_STATUS: /* CPU#3 Status */ in allwinner_cpucfg_write()
192 case REG_CLK_GATING: /* CPU Clock Gating */ in allwinner_cpucfg_write()
195 s->gen_ctrl = val; in allwinner_cpucfg_write()
198 s->super_standby = val; in allwinner_cpucfg_write()
201 s->entry_addr = val; in allwinner_cpucfg_write()
204 case REG_CNT64_CTRL: /* 64-bit Counter Control */ in allwinner_cpucfg_write()
205 case REG_CNT64_LOW: /* 64-bit Counter Low */ in allwinner_cpucfg_write()
206 case REG_CNT64_HIGH: /* 64-bit Counter High */ in allwinner_cpucfg_write()
208 __func__, (uint32_t)offset); in allwinner_cpucfg_write()
211 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", in allwinner_cpucfg_write()
212 __func__, (uint32_t)offset); in allwinner_cpucfg_write()
233 s->gen_ctrl = REG_GEN_CTRL_RST; in allwinner_cpucfg_reset()
234 s->super_standby = REG_SUPER_STANDBY_RST; in allwinner_cpucfg_reset()
235 s->entry_addr = 0; in allwinner_cpucfg_reset()
244 memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s, in allwinner_cpucfg_init()
246 sysbus_init_mmio(sbd, &s->iomem); in allwinner_cpucfg_init()
250 .name = "allwinner-cpucfg",
266 dc->vmsd = &allwinner_cpucfg_vmstate; in allwinner_cpucfg_class_init()