| /openbmc/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/ |
| H A D | irqsrcs_dcn_1_0.h | 81 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERF…
87 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON…
93 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON…
126 #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON…
375 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG…
811 #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_P…
835 #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_P…
859 #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_P…
883 #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_P…
889 #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_P…
[all …]
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| /openbmc/qemu/hw/rtc/ |
| H A D | aspeed_rtc.c | 18 #define COUNTER1 (0x00 / 4) macro
31 uint32_t reg1 = rtc->reg[COUNTER1]; in aspeed_rtc_calc_offset()
55 case COUNTER1: in aspeed_rtc_get_counter()
76 case COUNTER1: in aspeed_rtc_read()
104 case COUNTER1: in aspeed_rtc_write()
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| /openbmc/linux/drivers/media/pci/saa7164/ |
| H A D | saa7164-core.c | 174 hg->counter1[0 + i].val = i; in saa7164_histogram_reset()
178 hg->counter1[30 + i].val = 30 + (i * 10); in saa7164_histogram_reset()
182 hg->counter1[48 + i].val = 200 + (i * 200); in saa7164_histogram_reset()
185 hg->counter1[55].val = 2000; in saa7164_histogram_reset()
188 hg->counter1[56].val = 4000; in saa7164_histogram_reset()
191 hg->counter1[57].val = 8000; in saa7164_histogram_reset()
194 hg->counter1[58].val = 15000; in saa7164_histogram_reset()
197 hg->counter1[59].val = 30000; in saa7164_histogram_reset()
200 hg->counter1[60].val = 60000; in saa7164_histogram_reset()
203 hg->counter1[61].val = 300000; in saa7164_histogram_reset()
[all …]
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| H A D | saa7164.h | 197 struct saa7164_histogram_bucket counter1[64]; member
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| /openbmc/linux/arch/mips/alchemy/common/ |
| H A D | time.c | 16 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
41 .name = "alchemy-counter1",
116 /* register counter1 clocksource and event device */ in alchemy_time_init()
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| /openbmc/linux/drivers/watchdog/ |
| H A D | ni903x_wdt.c | 82 u8 control, counter0, counter1, counter2; in ni903x_wdd_get_timeleft() local
90 counter1 = inb(wdt->io_base + NIWD_COUNTER1); in ni903x_wdd_get_timeleft()
93 counter = (counter2 << 16) | (counter1 << 8) | counter0; in ni903x_wdd_get_timeleft()
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| /openbmc/linux/drivers/comedi/drivers/ |
| H A D | comedi_8254.c | 298 * @counter1: the counter number for the first divisor
303 unsigned int counter1, in comedi_8254_pacer_enable() argument
309 if (counter1 > 2 || counter2 > 2 || counter1 == counter2) in comedi_8254_pacer_enable()
317 comedi_8254_set_mode(i8254, counter1, mode); in comedi_8254_pacer_enable()
327 comedi_8254_write(i8254, counter1, i8254->divisor1); in comedi_8254_pacer_enable()
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| /openbmc/qemu/tests/tcg/hexagon/ |
| H A D | v68_hvx.c | 34 int counter1 = 17; in init_v6mpy_buffers() local
38 v6mpy_buffer1[i].w[j] = counter1++; in init_v6mpy_buffers()
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| H A D | hvx_misc.h | 72 int counter1 = 17; in init_buffers() local
76 buffer1[i].b[j] = counter1++; in init_buffers()
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| /openbmc/linux/arch/arm/mm/ |
| H A D | cache-l2x0-pmu.c | 30 * The L220/PL310 PMU has two equivalent counters, Counter1 and Counter0.
32 * the register for Counter1 comes first, followed by the register for
34 * We ensure that idx 0 -> Counter0, and idx1 -> Counter1.
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| /openbmc/linux/include/linux/comedi/ |
| H A D | comedi_8254.h | 111 unsigned int counter1, unsigned int counter2,
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,cci-400.yaml | 86 followed by counter0 overflow interrupt, counter1 overflow
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| /openbmc/linux/arch/parisc/kernel/ |
| H A D | perf.c | 571 /* Counter1 is bits 1431 to 1462 */ in perf_stop_counters()
573 /* OR sticky1 (bit 1463) to counter1 bit 32 */ in perf_stop_counters()
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| /openbmc/linux/arch/arm/kernel/ |
| H A D | perf_event_v6.c | 401 * counter0 and counter1. in armv6pmu_get_event_idx()
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| /openbmc/linux/drivers/perf/ |
| H A D | fsl_imx9_ddr_perf.c | 161 /* counter1 specific events */
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| /openbmc/qemu/hw/audio/ |
| H A D | gusemu_hal.c | 437 case 0x46: /* Counter1 */ in gus_write()
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| /openbmc/u-boot/include/fsl-mc/ |
| H A D | fsl_dpni.h | 264 MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->counter1); \
1290 uint64_t counter1; member
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| /openbmc/linux/arch/arm/boot/dts/nxp/ls/ |
| H A D | ls1021a.dtsi | 402 counter1: counter@29e0000 { label
|