15527cd06SHawking Zhang /* 25527cd06SHawking Zhang * Copyright 2017 Advanced Micro Devices, Inc. 35527cd06SHawking Zhang * 45527cd06SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 55527cd06SHawking Zhang * copy of this software and associated documentation files (the "Software"), 65527cd06SHawking Zhang * to deal in the Software without restriction, including without limitation 75527cd06SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 85527cd06SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 95527cd06SHawking Zhang * Software is furnished to do so, subject to the following conditions: 105527cd06SHawking Zhang * 115527cd06SHawking Zhang * The above copyright notice and this permission notice shall be included in 125527cd06SHawking Zhang * all copies or substantial portions of the Software. 135527cd06SHawking Zhang * 145527cd06SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 155527cd06SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 165527cd06SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 175527cd06SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 185527cd06SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 195527cd06SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 205527cd06SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 215527cd06SHawking Zhang * 225527cd06SHawking Zhang * Authors: AMD 235527cd06SHawking Zhang * 245527cd06SHawking Zhang */ 255527cd06SHawking Zhang 265527cd06SHawking Zhang #ifndef __IRQSRCS_DCN_1_0_H__ 275527cd06SHawking Zhang #define __IRQSRCS_DCN_1_0_H__ 285527cd06SHawking Zhang 295527cd06SHawking Zhang 305527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 315527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_SW_DONE 0 325527cd06SHawking Zhang 335527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 345527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1 355527cd06SHawking Zhang 365527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 375527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2 385527cd06SHawking Zhang 395527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 405527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3 415527cd06SHawking Zhang 425527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 435527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 445527cd06SHawking Zhang 455527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 465527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5 475527cd06SHawking Zhang 485527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 495527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6 505527cd06SHawking Zhang 515527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 525527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7 535527cd06SHawking Zhang 545527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 555527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8 565527cd06SHawking Zhang 575527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 585527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9 595527cd06SHawking Zhang 605527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 615527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10 625527cd06SHawking Zhang 635527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 645527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11 655527cd06SHawking Zhang 665527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 675527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12 685527cd06SHawking Zhang 695527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 705527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13 715527cd06SHawking Zhang 725527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 735527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14 745527cd06SHawking Zhang 755527cd06SHawking Zhang #define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 765527cd06SHawking Zhang #define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15 775527cd06SHawking Zhang 785527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 795527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7 805527cd06SHawking Zhang 815527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 825527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8 835527cd06SHawking Zhang 845527cd06SHawking Zhang #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 855527cd06SHawking Zhang #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7 865527cd06SHawking Zhang 875527cd06SHawking Zhang #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 885527cd06SHawking Zhang #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8 895527cd06SHawking Zhang 905527cd06SHawking Zhang #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 915527cd06SHawking Zhang #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7 925527cd06SHawking Zhang 935527cd06SHawking Zhang #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 945527cd06SHawking Zhang #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8 955527cd06SHawking Zhang 965527cd06SHawking Zhang #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level 975527cd06SHawking Zhang #define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12 985527cd06SHawking Zhang 995527cd06SHawking Zhang #define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level 1005527cd06SHawking Zhang #define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13 1015527cd06SHawking Zhang 1025527cd06SHawking Zhang #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level 1035527cd06SHawking Zhang #define DCN_1_0__CTXID__DMCU_SCP_INT 14 1045527cd06SHawking Zhang 1055527cd06SHawking Zhang #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1065527cd06SHawking Zhang #define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0 1075527cd06SHawking Zhang 1085527cd06SHawking Zhang #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1095527cd06SHawking Zhang #define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1 1105527cd06SHawking Zhang 1115527cd06SHawking Zhang #define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1125527cd06SHawking Zhang #define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2 1135527cd06SHawking Zhang 1145527cd06SHawking Zhang #define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level 1155527cd06SHawking Zhang #define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3 1165527cd06SHawking Zhang 1175527cd06SHawking Zhang #define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level 1185527cd06SHawking Zhang #define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4 1195527cd06SHawking Zhang 1205527cd06SHawking Zhang #define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level 1215527cd06SHawking Zhang #define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5 1225527cd06SHawking Zhang 1235527cd06SHawking Zhang #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 1245527cd06SHawking Zhang #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6 1255527cd06SHawking Zhang 1265527cd06SHawking Zhang #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 1275527cd06SHawking Zhang #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7 1285527cd06SHawking Zhang 1295527cd06SHawking Zhang #define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 1305527cd06SHawking Zhang #define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1 1315527cd06SHawking Zhang 1325527cd06SHawking Zhang #define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1335527cd06SHawking Zhang #define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0 1345527cd06SHawking Zhang 1355527cd06SHawking Zhang #define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1365527cd06SHawking Zhang #define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1 1375527cd06SHawking Zhang 1385527cd06SHawking Zhang #define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1395527cd06SHawking Zhang #define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2 1405527cd06SHawking Zhang 1415527cd06SHawking Zhang #define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1425527cd06SHawking Zhang #define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3 1435527cd06SHawking Zhang 1445527cd06SHawking Zhang #define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1455527cd06SHawking Zhang #define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4 1465527cd06SHawking Zhang 1475527cd06SHawking Zhang #define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1485527cd06SHawking Zhang #define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5 1495527cd06SHawking Zhang 1505527cd06SHawking Zhang #define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1515527cd06SHawking Zhang #define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6 1525527cd06SHawking Zhang 1535527cd06SHawking Zhang #define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1545527cd06SHawking Zhang #define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7 1555527cd06SHawking Zhang 1565527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level 1575527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD1_INT 0 1585527cd06SHawking Zhang 1595527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 1605527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD2_INT 1 1615527cd06SHawking Zhang 1625527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 1635527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD3_INT 2 1645527cd06SHawking Zhang 1655527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 1665527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD4_INT 3 1675527cd06SHawking Zhang 1685527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 1695527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD5_INT 4 1705527cd06SHawking Zhang 1715527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 1725527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD6_INT 5 1735527cd06SHawking Zhang 1745527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level 1755527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD1_RX_INT 6 1765527cd06SHawking Zhang 1775527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 1785527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD2_RX_INT 7 1795527cd06SHawking Zhang 1805527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 1815527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD3_RX_INT 8 1825527cd06SHawking Zhang 1835527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 1845527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD4_RX_INT 9 1855527cd06SHawking Zhang 1865527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 1875527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD5_RX_INT 10 1885527cd06SHawking Zhang 1895527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 1905527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_HPD6_RX_INT 11 1915527cd06SHawking Zhang 1925527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level 1935527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0 1945527cd06SHawking Zhang 1955527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 1965527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2 1975527cd06SHawking Zhang 1985527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 1995527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3 2005527cd06SHawking Zhang 2015527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2025527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4 2035527cd06SHawking Zhang 2045527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2055527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5 2065527cd06SHawking Zhang 2075527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2085527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6 2095527cd06SHawking Zhang 2105527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2115527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7 2125527cd06SHawking Zhang 2135527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2145527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8 2155527cd06SHawking Zhang 2165527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2175527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9 2185527cd06SHawking Zhang 2195527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2205527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0 2215527cd06SHawking Zhang 2225527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2235527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1 2245527cd06SHawking Zhang 2255527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2265527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2 2275527cd06SHawking Zhang 2285527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2295527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3 2305527cd06SHawking Zhang 2315527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2325527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4 2335527cd06SHawking Zhang 2345527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2355527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5 2365527cd06SHawking Zhang 2375527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2385527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6 2395527cd06SHawking Zhang 2405527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2415527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7 2425527cd06SHawking Zhang 2435527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2445527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0 2455527cd06SHawking Zhang 2465527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2475527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1 2485527cd06SHawking Zhang 2495527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2505527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2 2515527cd06SHawking Zhang 2525527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2535527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3 2545527cd06SHawking Zhang 2555527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2565527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4 2575527cd06SHawking Zhang 2585527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2595527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5 2605527cd06SHawking Zhang 2615527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2625527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6 2635527cd06SHawking Zhang 2645527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 2655527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7 2665527cd06SHawking Zhang 2675527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 2685527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0 2695527cd06SHawking Zhang 2705527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 2715527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1 2725527cd06SHawking Zhang 2735527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 2745527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2 2755527cd06SHawking Zhang 2765527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 2775527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3 2785527cd06SHawking Zhang 2795527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 2805527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4 2815527cd06SHawking Zhang 2825527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 2835527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5 2845527cd06SHawking Zhang 2855527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level 2865527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0 2875527cd06SHawking Zhang 2885527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 2895527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1 2905527cd06SHawking Zhang 2915527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 2925527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2 2935527cd06SHawking Zhang 2945527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 2955527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3 2965527cd06SHawking Zhang 2975527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 2985527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4 2995527cd06SHawking Zhang 3005527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 3015527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5 3025527cd06SHawking Zhang 3035527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level 3045527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6 3055527cd06SHawking Zhang 3065527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 3075527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7 3085527cd06SHawking Zhang 3095527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level 3105527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0 3115527cd06SHawking Zhang 3125527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 3135527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1 3145527cd06SHawking Zhang 3155527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 3165527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2 3175527cd06SHawking Zhang 3185527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 3195527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3 3205527cd06SHawking Zhang 3215527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 3225527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4 3235527cd06SHawking Zhang 3245527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 3255527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5 3265527cd06SHawking Zhang 3275527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level 3285527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6 3295527cd06SHawking Zhang 3305527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 3315527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7 3325527cd06SHawking Zhang 3335527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 3345527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0 3355527cd06SHawking Zhang 3365527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 3375527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1 3385527cd06SHawking Zhang 3395527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 3405527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2 3415527cd06SHawking Zhang 3425527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 3435527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3 3445527cd06SHawking Zhang 3455527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 3465527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4 3475527cd06SHawking Zhang 3485527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 3495527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5 3505527cd06SHawking Zhang 3515527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 3525527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6 3535527cd06SHawking Zhang 3545527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 3555527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7 3565527cd06SHawking Zhang 3575527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 3585527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8 3595527cd06SHawking Zhang 3605527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 3615527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9 3625527cd06SHawking Zhang 3635527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 3645527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10 3655527cd06SHawking Zhang 3665527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 3675527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11 3685527cd06SHawking Zhang 3695527cd06SHawking Zhang #define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 3705527cd06SHawking Zhang #define DCN_1_0__CTXID__VGA_CRT_INT 12 3715527cd06SHawking Zhang 3725527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 3735527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0 3745527cd06SHawking Zhang 3755527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level 3765527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1 3775527cd06SHawking Zhang 3785527cd06SHawking Zhang #define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 3795527cd06SHawking Zhang #define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0 3805527cd06SHawking Zhang 3815527cd06SHawking Zhang #define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 3825527cd06SHawking Zhang #define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1 3835527cd06SHawking Zhang 3845527cd06SHawking Zhang #define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 3855527cd06SHawking Zhang #define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2 3865527cd06SHawking Zhang 3875527cd06SHawking Zhang #define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 3885527cd06SHawking Zhang #define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3 3895527cd06SHawking Zhang 3905527cd06SHawking Zhang #define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 3915527cd06SHawking Zhang #define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4 3925527cd06SHawking Zhang 3935527cd06SHawking Zhang #define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 3945527cd06SHawking Zhang #define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5 3955527cd06SHawking Zhang 3965527cd06SHawking Zhang #define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 3975527cd06SHawking Zhang #define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6 3985527cd06SHawking Zhang 3995527cd06SHawking Zhang #define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 4005527cd06SHawking Zhang #define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7 4015527cd06SHawking Zhang 4025527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 4035527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0 4045527cd06SHawking Zhang 4055527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 4065527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1 4075527cd06SHawking Zhang 4085527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 4095527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2 4105527cd06SHawking Zhang 4115527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 4125527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3 4135527cd06SHawking Zhang 4145527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 4155527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4 4165527cd06SHawking Zhang 4175527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 4185527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5 4195527cd06SHawking Zhang 4205527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 4215527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0 4225527cd06SHawking Zhang 4235527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 4245527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1 4255527cd06SHawking Zhang 4265527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 4275527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2 4285527cd06SHawking Zhang 4295527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 4305527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3 4315527cd06SHawking Zhang 4325527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 4335527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4 4345527cd06SHawking Zhang 4355527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 4365527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5 4375527cd06SHawking Zhang 4385527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 4395527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6 4405527cd06SHawking Zhang 4415527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 4425527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7 4435527cd06SHawking Zhang 4445527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 4455527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8 4465527cd06SHawking Zhang 4475527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 4485527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9 4495527cd06SHawking Zhang 4505527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 4515527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10 4525527cd06SHawking Zhang 4535527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 4545527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11 4555527cd06SHawking Zhang 4565527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 4575527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12 4585527cd06SHawking Zhang 4595527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 4605527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13 4615527cd06SHawking Zhang 4625527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 4635527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14 4645527cd06SHawking Zhang 4655527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 4665527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15 4675527cd06SHawking Zhang 4685527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 4695527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0 4705527cd06SHawking Zhang 4715527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 4725527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1 4735527cd06SHawking Zhang 4745527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 4755527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2 4765527cd06SHawking Zhang 4775527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 4785527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3 4795527cd06SHawking Zhang 4805527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 4815527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4 4825527cd06SHawking Zhang 4835527cd06SHawking Zhang #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 4845527cd06SHawking Zhang #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5 4855527cd06SHawking Zhang 4865527cd06SHawking Zhang #define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level 4875527cd06SHawking Zhang #define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6 4885527cd06SHawking Zhang 4895527cd06SHawking Zhang #define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 4905527cd06SHawking Zhang #define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7 4915527cd06SHawking Zhang 4925527cd06SHawking Zhang #define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 4935527cd06SHawking Zhang #define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8 4945527cd06SHawking Zhang 4955527cd06SHawking Zhang #define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 4965527cd06SHawking Zhang #define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9 4975527cd06SHawking Zhang 4985527cd06SHawking Zhang #define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 4995527cd06SHawking Zhang #define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10 5005527cd06SHawking Zhang 5015527cd06SHawking Zhang #define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 5025527cd06SHawking Zhang #define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11 5035527cd06SHawking Zhang 5045527cd06SHawking Zhang #define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 5055527cd06SHawking Zhang #define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0 5065527cd06SHawking Zhang 5075527cd06SHawking Zhang #define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 5085527cd06SHawking Zhang #define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1 5095527cd06SHawking Zhang 5105527cd06SHawking Zhang #define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 5115527cd06SHawking Zhang #define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2 5125527cd06SHawking Zhang 5135527cd06SHawking Zhang #define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 5145527cd06SHawking Zhang #define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3 5155527cd06SHawking Zhang 5165527cd06SHawking Zhang #define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 5175527cd06SHawking Zhang #define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4 5185527cd06SHawking Zhang 5195527cd06SHawking Zhang #define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 5205527cd06SHawking Zhang #define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5 5215527cd06SHawking Zhang 5225527cd06SHawking Zhang #define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 5235527cd06SHawking Zhang #define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6 5245527cd06SHawking Zhang 5255527cd06SHawking Zhang #define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 5265527cd06SHawking Zhang #define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7 5275527cd06SHawking Zhang 5285527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5295527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0 5305527cd06SHawking Zhang 5315527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 5325527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1 5335527cd06SHawking Zhang 5345527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5355527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2 5365527cd06SHawking Zhang 5375527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 5385527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3 5395527cd06SHawking Zhang 5405527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5415527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4 5425527cd06SHawking Zhang 5435527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 5445527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5 5455527cd06SHawking Zhang 5465527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5475527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6 5485527cd06SHawking Zhang 5495527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 5505527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7 5515527cd06SHawking Zhang 5525527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5535527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8 5545527cd06SHawking Zhang 5555527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 5565527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9 5575527cd06SHawking Zhang 5585527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5595527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10 5605527cd06SHawking Zhang 5615527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 5625527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11 5635527cd06SHawking Zhang 5645527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5655527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE 0x19 // D2 : OTG V_update OTG2_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5665527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5675527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE 0x1B // D4 : OTG V_update OTG4_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5685527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5695527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5705527cd06SHawking Zhang 5715527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 5725527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0 5735527cd06SHawking Zhang 5745527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 5755527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1 5765527cd06SHawking Zhang 5775527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 5785527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2 5795527cd06SHawking Zhang 5805527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 5815527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3 5825527cd06SHawking Zhang 5835527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 5845527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4 5855527cd06SHawking Zhang 5865527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 5875527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5 5885527cd06SHawking Zhang 5895527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 5905527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6 5915527cd06SHawking Zhang 5925527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 5935527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7 5945527cd06SHawking Zhang 5955527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 5965527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8 5975527cd06SHawking Zhang 5985527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 5995527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 6005527cd06SHawking Zhang 6015527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 6025527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 6035527cd06SHawking Zhang 6045527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 6055527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 6065527cd06SHawking Zhang 6075527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse 6085527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12 6095527cd06SHawking Zhang 6105527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 6115527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0 6125527cd06SHawking Zhang 6135527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 6145527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1 6155527cd06SHawking Zhang 6165527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 6175527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2 6185527cd06SHawking Zhang 6195527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 6205527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3 6215527cd06SHawking Zhang 6225527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 6235527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4 6245527cd06SHawking Zhang 6255527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 6265527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5 6275527cd06SHawking Zhang 6285527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6295527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6 6305527cd06SHawking Zhang 6315527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6325527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7 6335527cd06SHawking Zhang 6345527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6355527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8 6365527cd06SHawking Zhang 6375527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6385527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 6395527cd06SHawking Zhang 6405527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6415527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 6425527cd06SHawking Zhang 6435527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6445527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 6455527cd06SHawking Zhang 6465527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 6475527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12 6485527cd06SHawking Zhang 6495527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6505527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0 6515527cd06SHawking Zhang 6525527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6535527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1 6545527cd06SHawking Zhang 6555527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6565527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2 6575527cd06SHawking Zhang 6585527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6595527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3 6605527cd06SHawking Zhang 6615527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6625527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4 6635527cd06SHawking Zhang 6645527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 6655527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5 6665527cd06SHawking Zhang 6675527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6685527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6 6695527cd06SHawking Zhang 6705527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6715527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7 6725527cd06SHawking Zhang 6735527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6745527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8 6755527cd06SHawking Zhang 6765527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6775527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 6785527cd06SHawking Zhang 6795527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6805527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 6815527cd06SHawking Zhang 6825527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6835527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 6845527cd06SHawking Zhang 6855527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 6865527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12 6875527cd06SHawking Zhang 6885527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6895527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0 6905527cd06SHawking Zhang 6915527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6925527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1 6935527cd06SHawking Zhang 6945527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6955527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2 6965527cd06SHawking Zhang 6975527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 6985527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3 6995527cd06SHawking Zhang 7005527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 7015527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4 7025527cd06SHawking Zhang 7035527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 7045527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5 7055527cd06SHawking Zhang 7065527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7075527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6 7085527cd06SHawking Zhang 7095527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7105527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7 7115527cd06SHawking Zhang 7125527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7135527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8 7145527cd06SHawking Zhang 7155527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7165527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 7175527cd06SHawking Zhang 7185527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7195527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 7205527cd06SHawking Zhang 7215527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7225527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 7235527cd06SHawking Zhang 7245527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 7255527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12 7265527cd06SHawking Zhang 7275527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7285527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0 7295527cd06SHawking Zhang 7305527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7315527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1 7325527cd06SHawking Zhang 7335527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7345527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2 7355527cd06SHawking Zhang 7365527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7375527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3 7385527cd06SHawking Zhang 7395527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7405527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4 7415527cd06SHawking Zhang 7425527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 7435527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5 7445527cd06SHawking Zhang 7455527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 7465527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6 7475527cd06SHawking Zhang 7485527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 7495527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7 7505527cd06SHawking Zhang 7515527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 7525527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8 7535527cd06SHawking Zhang 7545527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7555527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 7565527cd06SHawking Zhang 7575527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7585527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 7595527cd06SHawking Zhang 7605527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7615527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 7625527cd06SHawking Zhang 7635527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 7645527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12 7655527cd06SHawking Zhang 7665527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 7675527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D1_VBLANK 0 7685527cd06SHawking Zhang 7695527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 7705527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D1_VLINE1 1 7715527cd06SHawking Zhang 7725527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 7735527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D1_VLINE2 2 7745527cd06SHawking Zhang 7755527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 7765527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D2_VBLANK 3 7775527cd06SHawking Zhang 7785527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 7795527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D2_VLINE1 4 7805527cd06SHawking Zhang 7815527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 7825527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D2_VLINE2 5 7835527cd06SHawking Zhang 7845527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 7855527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6 7865527cd06SHawking Zhang 7875527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 7885527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7 7895527cd06SHawking Zhang 7905527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 7915527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8 7925527cd06SHawking Zhang 7935527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 7945527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9 7955527cd06SHawking Zhang 7965527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 7975527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10 7985527cd06SHawking Zhang 7995527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 8005527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11 8015527cd06SHawking Zhang 8025527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 8035527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12 8045527cd06SHawking Zhang 8055527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 8065527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13 8075527cd06SHawking Zhang 8085527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 8095527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0 8105527cd06SHawking Zhang 8115527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 8125527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1 8135527cd06SHawking Zhang 8145527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 8155527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D3_VBLANK 9 8165527cd06SHawking Zhang 8175527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 8185527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D3_VLINE1 10 8195527cd06SHawking Zhang 8205527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 8215527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D3_VLINE2 11 8225527cd06SHawking Zhang 8235527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8245527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D4_VBLANK 12 8255527cd06SHawking Zhang 8265527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8275527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D4_VLINE1 13 8285527cd06SHawking Zhang 8295527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8305527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D4_VLINE2 14 8315527cd06SHawking Zhang 8325527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 8335527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0 8345527cd06SHawking Zhang 8355527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 8365527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1 8375527cd06SHawking Zhang 8385527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8395527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D5_VBLANK 9 8405527cd06SHawking Zhang 8415527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8425527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D5_VLINE1 10 8435527cd06SHawking Zhang 8445527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8455527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D5_VLINE2 11 8465527cd06SHawking Zhang 8475527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8485527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D6_VBLANK 12 8495527cd06SHawking Zhang 8505527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8515527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D6_VLINE1 13 8525527cd06SHawking Zhang 8535527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8545527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D6_VLINE2 14 8555527cd06SHawking Zhang 8565527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 8575527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0 8585527cd06SHawking Zhang 8595527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 8605527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1 8615527cd06SHawking Zhang 8625527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8635527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D7_VBLANK 9 8645527cd06SHawking Zhang 8655527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8665527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D7_VLINE1 10 8675527cd06SHawking Zhang 8685527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8695527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D7_VLINE2 11 8705527cd06SHawking Zhang 8715527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8725527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D8_VBLANK 12 8735527cd06SHawking Zhang 8745527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8755527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D8_VLINE1 13 8765527cd06SHawking Zhang 8775527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 8785527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D8_VLINE2 14 8795527cd06SHawking Zhang 8805527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 8815527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0 8825527cd06SHawking Zhang 8835527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 8845527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1 8855527cd06SHawking Zhang 8865527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 8875527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0 8885527cd06SHawking Zhang 8895527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 8905527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1 8915527cd06SHawking Zhang 8925527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 8935527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0 8945527cd06SHawking Zhang 8955527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 8965527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1 8975527cd06SHawking Zhang 8985527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 8995527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0 9005527cd06SHawking Zhang 9015527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 9025527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1 9035527cd06SHawking Zhang 9045527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 9055527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0 9065527cd06SHawking Zhang 9075527cd06SHawking Zhang #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 9085527cd06SHawking Zhang #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1 9095527cd06SHawking Zhang 9105527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 9115527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0 9125527cd06SHawking Zhang 9135527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 9145527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1 9155527cd06SHawking Zhang 9165527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 9175527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0 9185527cd06SHawking Zhang 9195527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 9205527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1 9215527cd06SHawking Zhang 9225527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 9235527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0 9245527cd06SHawking Zhang 9255527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 9265527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1 9275527cd06SHawking Zhang 9285527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 9295527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0 9305527cd06SHawking Zhang 9315527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 9325527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1 9335527cd06SHawking Zhang 9345527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 9355527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0 9365527cd06SHawking Zhang 9375527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 9385527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1 9395527cd06SHawking Zhang 9405527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 9415527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0 9425527cd06SHawking Zhang 9435527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 9445527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1 9455527cd06SHawking Zhang 9465527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 9475527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0 9485527cd06SHawking Zhang 9495527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 9505527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1 9515527cd06SHawking Zhang 9525527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 9535527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0 9545527cd06SHawking Zhang 9555527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 9565527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1 9575527cd06SHawking Zhang 9585527cd06SHawking Zhang #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse 9595527cd06SHawking Zhang #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0 9605527cd06SHawking Zhang 9615527cd06SHawking Zhang #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 9625527cd06SHawking Zhang #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1 9635527cd06SHawking Zhang 9645527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 9655527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0 9665527cd06SHawking Zhang 9675527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 9685527cd06SHawking Zhang #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1 9695527cd06SHawking Zhang 9705527cd06SHawking Zhang #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 9715527cd06SHawking Zhang #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0 9725527cd06SHawking Zhang 9735527cd06SHawking Zhang #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 9745527cd06SHawking Zhang #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1 9755527cd06SHawking Zhang 9765527cd06SHawking Zhang #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 9775527cd06SHawking Zhang #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0 9785527cd06SHawking Zhang 9795527cd06SHawking Zhang #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 9805527cd06SHawking Zhang #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1 9815527cd06SHawking Zhang 9825527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 9835527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0 9845527cd06SHawking Zhang 9855527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 9865527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1 9875527cd06SHawking Zhang 9885527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 9895527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2 9905527cd06SHawking Zhang 9915527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 9925527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3 9935527cd06SHawking Zhang 9945527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 9955527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4 9965527cd06SHawking Zhang 9975527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 9985527cd06SHawking Zhang #define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5 9995527cd06SHawking Zhang 10005527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 10015527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6 10025527cd06SHawking Zhang 10035527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 10045527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7 10055527cd06SHawking Zhang 10065527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 10075527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8 10085527cd06SHawking Zhang 10095527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 10105527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 10115527cd06SHawking Zhang 10125527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 10135527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 10145527cd06SHawking Zhang 10155527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 10165527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 10175527cd06SHawking Zhang 10185527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 10195527cd06SHawking Zhang #define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12 10205527cd06SHawking Zhang 10215527cd06SHawking Zhang #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 10225527cd06SHawking Zhang #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0 10235527cd06SHawking Zhang 10245527cd06SHawking Zhang #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 10255527cd06SHawking Zhang #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1 10265527cd06SHawking Zhang 10275527cd06SHawking Zhang #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 10285527cd06SHawking Zhang #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0 10295527cd06SHawking Zhang 10305527cd06SHawking Zhang #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 10315527cd06SHawking Zhang #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1 10325527cd06SHawking Zhang 10335527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 10345527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0 10355527cd06SHawking Zhang 10365527cd06SHawking Zhang #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 10375527cd06SHawking Zhang #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1 10385527cd06SHawking Zhang 10395527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10405527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP 0x3D // "OTG1 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG2_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10415527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP 0x3E // "OTG2 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG3_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10425527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP 0x3F // "OTG3 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG4_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10435527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP 0x40 // "OTG4 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG5_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10445527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP 0x41 // "OTG5 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG6_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10455527cd06SHawking Zhang 10465527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D1_OTG_VREADY 0x42 // "OTG0 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG1_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10475527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D2_OTG_VREADY 0x43 // "OTG1 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG2_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10485527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D3_OTG_VREADY 0x44 // "OTG2 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG3_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10495527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D4_OTG_VREADY 0x45 // "OTG3 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG4_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10505527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D5_OTG_VREADY 0x46 // "OTG4 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG5_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10515527cd06SHawking Zhang #define DCN_1_0__SRCID__DC_D6_OTG_VREADY 0x47 // "OTG5 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG6_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 10525527cd06SHawking Zhang 10535527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG0_VSYNC_NOM 0x48 // OTG0 vsync nom interrupt OTG1_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 10545527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_VSYNC_NOM 0x49 // OTG1 vsync nom interrupt OTG2_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 10555527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_VSYNC_NOM 0x4A // OTG2 vsync nom interrupt OTG3_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 10565527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_VSYNC_NOM 0x4B // OTG3 vsync nom interrupt OTG4_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 10575527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 10585527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 10595527cd06SHawking Zhang 10605527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10615527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0 10625527cd06SHawking Zhang 10635527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10645527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1 10655527cd06SHawking Zhang 10665527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10675527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2 10685527cd06SHawking Zhang 10695527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10705527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3 10715527cd06SHawking Zhang 10725527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10735527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4 10745527cd06SHawking Zhang 10755527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10765527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5 10775527cd06SHawking Zhang 10785527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10795527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6 10805527cd06SHawking Zhang 10815527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10825527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7 10835527cd06SHawking Zhang 10845527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10855527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8 10865527cd06SHawking Zhang 10875527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10885527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9 10895527cd06SHawking Zhang 10905527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10915527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10 10925527cd06SHawking Zhang 10935527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10945527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11 10955527cd06SHawking Zhang 10965527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 10975527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12 10985527cd06SHawking Zhang 10995527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 11005527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13 11015527cd06SHawking Zhang 11025527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 11035527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14 11045527cd06SHawking Zhang 11055527cd06SHawking Zhang #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 11065527cd06SHawking Zhang #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15 11075527cd06SHawking Zhang 11085527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11095527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT 0x50 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP1_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11105527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT 0x51 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP2_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11115527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT 0x52 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP3_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11125527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT 0x53 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP4_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11135527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT 0x54 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP5_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11145527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT 0x55 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP6_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11155527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT 0x56 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP7_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11165527cd06SHawking Zhang 11175527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x57 // "OTG0 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 11185527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 11195527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x59 // "OTG2 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 11205527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 11215527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5B // "OTG4 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 11225527cd06SHawking Zhang #define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 11235527cd06SHawking Zhang 11245527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT 0x5D // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP0_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11255527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT 0x5E // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP1_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11265527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT 0x5F // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP2_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11275527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT 0x60 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP3_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11285527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT 0x61 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP4_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11295527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT 0x62 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP5_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11305527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11315527cd06SHawking Zhang #define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 11325527cd06SHawking Zhang 1133c79fe9b4SLeo (Hanghong) Ma #define DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 0x68 1134c79fe9b4SLeo (Hanghong) Ma #define DCN_1_0__CTXID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 6 1135*f066af88SJude Shih #define DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT 0x68 // DMCUB_IHC_outbox1_ready_int IHC_DMCUB_outbox1_ready_int_ack DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE24 Level/Pulse 1136*f066af88SJude Shih #define DCN_1_0__CTXID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT 8 11375527cd06SHawking Zhang 11385527cd06SHawking Zhang #endif // __IRQSRCS_DCN_1_0_H__ 1139