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/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6755.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&sysirq>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a53";
[all …]
H A Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
[all …]
/openbmc/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dsilicon-errata.txt1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
15 ---------------------------------------------------------------------
16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
55 相應的內核配置（Kconfig）選項被加在 「內核特性（Kernel Features）」->
66 +----------------+-----------------+-----------------+-------------------------+
67 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
68 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
69 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
[all …]
/openbmc/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dsilicon-errata.txt1 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
12 ---------------------------------------------------------------------
13 Documentation/arch/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dhi6220.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/hi6220-clock.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <2>;
23 #size-cells = <0>;
25 cpu-map {
57 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
H A Dfsl-imx8-ca53.dtsi17 #address-cells = <2>;
18 #size-cells = <0>;
20 idle-states {
21 entry-method = "psci";
23 CPU_SLEEP: cpu-sleep {
24 compatible = "arm,idle-state";
25 local-timer-stop;
26 arm,psci-suspend-param = <0x0000000>;
27 entry-latency-us = <700>;
28 exit-latency-us = <250>;
[all …]
H A Dbcm2837.dtsi9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 compatible = "brcm,bcm2836-l1-intc";
14 interrupt-controller;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
21 compatible = "arm,armv7-timer";
22 interrupt-parent = <&local_intc>;
27 always-on;
31 #address-cells = <1>;
32 #size-cells = <0>;
[all …]
H A Dbcm6858.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <0>;
16 u-boot,dm-pre-reloc;
19 compatible = "arm,cortex-a53", "arm,armv8";
22 next-level-cache = <&l2>;
23 u-boot,dm-pre-reloc;
27 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
H A Dbcm63158.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <0>;
16 u-boot,dm-pre-reloc;
19 compatible = "arm,cortex-a53", "arm,armv8";
22 next-level-cache = <&l2>;
23 u-boot,dm-pre-reloc;
27 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
H A Dmeson-gxm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gxl.dtsi"
10 compatible = "amlogic,meson-gxm";
13 cpu-map {
47 compatible = "arm,cortex-a53", "arm,armv8";
49 enable-method = "psci";
50 next-level-cache = <&l2>;
56 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
59 next-level-cache = <&l2>;
[all …]
/openbmc/qemu/docs/system/arm/
H A Draspi.rst8 ARM1176JZF-S core, 512 MiB of RAM
10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
19 -------------------
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
27 * Serial ports (BCM2835 AUX - 16550 based - and PL011)
41 ---------------
/openbmc/linux/arch/arm64/boot/dts/realtek/
H A Drtd1296.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2017-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
[all …]
H A Drtd1295.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
[all …]
H A Drtd1395.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
40 compatible = "arm,cortex-a53";
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Ds32g2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2017-2021 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
25 enable-method = "psci";
[all …]
H A Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-t7.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <0x2>;
15 #size-cells = <0x0>;
17 cpu-map {
51 compatible = "arm,cortex-a53";
53 enable-method = "psci";
[all …]
H A Dmeson-g12a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12.dtsi"
12 #address-cells = <0x2>;
13 #size-cells = <0x0>;
17 compatible = "arm,cortex-a53";
19 enable-method = "psci";
20 next-level-cache = <&l2>;
21 #cooling-cells = <2>;
26 compatible = "arm,cortex-a53";
28 enable-method = "psci";
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7885.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7885.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
34 interrupt-affinity = <&cpu0>,
42 arm-a73-pmu {
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a7.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62a.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
[all …]
H A Dk3-am62p5.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include "k3-am62p.dtsi"
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu-map {
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 i-cache-size = <0x8000>;
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/
H A Dmapfile.csv10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd020,v1,arm/cortex-a34,core
16 0x00000000410fd030,v1,arm/cortex-a53,core
17 0x00000000420f1000,v1,arm/cortex-a53,core
18 0x00000000410fd040,v1,arm/cortex-a35,core
19 0x00000000410fd050,v1,arm/cortex-a55,core
20 0x00000000410fd060,v1,arm/cortex-a65-e1,core
21 0x00000000410fd4a0,v1,arm/cortex-a65-e1,core
22 0x00000000410fd070,v1,arm/cortex-a57-a72,core
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8a/
H A Dtune-cortexa57-cortexa53.inc1 DEFAULTTUNE ?= "cortexa57-cortexa53"
3 TUNEVALID[cortexa57-cortexa53] = "Enable big.LITTLE Cortex-A57.Cortex-A53 specific processor optimi…
4 …GS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa57-cortexa53", " -mcpu=cortex-a57.cortex-a53"…
5 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa57-cortexa53", "cortexa57-cortex…
7 require conf/machine/include/arm/arch-armv8a.inc
10 AVAILTUNES += "cortexa57-cortexa53"
11 ARMPKGARCH:tune-cortexa57-cortexa53 = "cortexa57-cortexa53"
12 # We do not want -march since -mcpu is added above to cover for it
13 TUNE_FEATURES:tune-cortexa57-cortexa53 = "aarch64 crc cortexa57-cortexa53"
14 PACKAGE_EXTRA_ARCHS:tune-cortexa57-cortexa53 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa57-co…
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Djuno-r2.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
[all …]

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