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/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8-ca53.dtsi17 #address-cells = <2>;
18 #size-cells = <0>;
20 idle-states {
21 entry-method = "psci";
23 CPU_SLEEP: cpu-sleep {
24 compatible = "arm,idle-state";
25 local-timer-stop;
26 arm,psci-suspend-param = <0x0000000>;
27 entry-latency-us = <700>;
28 exit-latency-us = <250>;
[all …]
H A Dhi6220.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/hi6220-clock.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <2>;
23 #size-cells = <0>;
25 cpu-map {
57 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
H A Dbcm2837.dtsi9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 compatible = "brcm,bcm2836-l1-intc";
14 interrupt-controller;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
21 compatible = "arm,armv7-timer";
22 interrupt-parent = <&local_intc>;
27 always-on;
31 #address-cells = <1>;
32 #size-cells = <0>;
[all …]
H A Dbcm6858.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <0>;
16 u-boot,dm-pre-reloc;
19 compatible = "arm,cortex-a53", "arm,armv8";
22 next-level-cache = <&l2>;
23 u-boot,dm-pre-reloc;
27 compatible = "arm,cortex-a53", "arm,armv8";
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H A Dbcm63158.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <0>;
16 u-boot,dm-pre-reloc;
19 compatible = "arm,cortex-a53", "arm,armv8";
22 next-level-cache = <&l2>;
23 u-boot,dm-pre-reloc;
27 compatible = "arm,cortex-a53", "arm,armv8";
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H A Dmeson-gxm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gxl.dtsi"
10 compatible = "amlogic,meson-gxm";
13 cpu-map {
47 compatible = "arm,cortex-a53", "arm,armv8";
49 enable-method = "psci";
50 next-level-cache = <&l2>;
56 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
59 next-level-cache = <&l2>;
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H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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H A Dsun50i-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <sunxi-h3-h5.dtsi>
47 #address-cells = <1>;
48 #size-cells = <0>;
51 compatible = "arm,cortex-a53", "arm,armv8";
54 enable-method = "psci";
58 compatible = "arm,cortex-a53", "arm,armv8";
61 enable-method = "psci";
65 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
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H A Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
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H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53", "arm,armv8";
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/openbmc/qemu/docs/system/arm/
H A Draspi.rst8 ARM1176JZF-S core, 512 MiB of RAM
10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
19 -------------------
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
27 * Serial ports (BCM2835 AUX - 16550 based - and PL011)
41 ---------------
H A Dxlnx-zcu102.rst1 Xilinx ZynqMP ZCU102 (``xlnx-zcu102``)
4 The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board.
5 This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs.
7 Machine-specific options
10 The following machine-specific options are supported:
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8a/
H A Dtune-cortexa57-cortexa53.inc1 DEFAULTTUNE ?= "cortexa57-cortexa53"
3 TUNEVALID[cortexa57-cortexa53] = "Enable big.LITTLE Cortex-A57.Cortex-A53 specific processor optimi…
4 …GS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa57-cortexa53", " -mcpu=cortex-a57.cortex-a53"…
5 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa57-cortexa53", "cortexa57-cortex…
7 require conf/machine/include/arm/arch-armv8a.inc
10 AVAILTUNES += "cortexa57-cortexa53"
11 ARMPKGARCH:tune-cortexa57-cortexa53 = "cortexa57-cortexa53"
12 # We do not want -march since -mcpu is added above to cover for it
13 TUNE_FEATURES:tune-cortexa57-cortexa53 = "aarch64 crc cortexa57-cortexa53"
14 PACKAGE_EXTRA_ARCHS:tune-cortexa57-cortexa53 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa57-co…
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H A Dtune-cortexa72-cortexa53.inc1 DEFAULTTUNE ?= "cortexa72-cortexa53"
3 TUNEVALID[cortexa72-cortexa53] = "Enable big.LITTLE Cortex-A72.Cortex-A53 specific processor optimi…
4 …GS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa72-cortexa53", " -mcpu=cortex-a72.cortex-a53"…
5 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa72-cortexa53", "cortexa72-cortex…
7 require conf/machine/include/arm/arch-armv8a.inc
10 AVAILTUNES += "cortexa72-cortexa53 cortexa72-cortexa53-crypto"
11 ARMPKGARCH:tune-cortexa72-cortexa53 = "cortexa72-cortexa53"
12 ARMPKGARCH:tune-cortexa72-cortexa53-crypto = "cortexa72-cortexa53-crypto"
13 # We do not want -march since -mcpu is added above to cover for it
14 TUNE_FEATURES:tune-cortexa72-cortexa53 = "aarch64 crc cortexa72-cortexa53"
[all …]
H A Dtune-cortexa73-cortexa53.inc1 DEFAULTTUNE ?= "cortexa73-cortexa53"
3 TUNEVALID[cortexa73-cortexa53] = "Enable big.LITTLE Cortex-A73.Cortex-A53 specific processor optimi…
4 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa73-cortexa53", "cortexa73-cortex…
5 …GS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa73-cortexa53", " -mcpu=cortex-a73.cortex-a53"…
7 require conf/machine/include/arm/arch-armv8a.inc
10 AVAILTUNES += "cortexa73-cortexa53 cortexa73-cortexa53-crypto"
11 ARMPKGARCH:tune-cortexa73-cortexa53 = "cortexa73-cortexa53"
12 ARMPKGARCH:tune-cortexa73-cortexa53-crypto = "cortexa73-cortexa53-crypto"
13 # We do not want -march since -mcpu is added above to cover for it
14 TUNE_FEATURES:tune-cortexa73-cortexa53 = "aarch64 crc cortexa73-cortexa53"
[all …]
H A Dtune-cortexa53.inc3 TUNEVALID[cortexa53] = "Enable Cortex-A53 specific processor optimizations"
4 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa53', ' -mcpu=cortex-a53', '', d)}"
6 require conf/machine/include/arm/arch-armv8a.inc
9 AVAILTUNES += "cortexa53 cortexa53-crypto"
10 ARMPKGARCH:tune-cortexa53 = "cortexa53"
11 ARMPKGARCH:tune-cortexa53-crypto = "cortexa53-crypto"
12 # We do not want -march since -mcpu is added above to cover for it
13 TUNE_FEATURES:tune-cortexa53 = "aarch64 crc cortexa53"
14 TUNE_FEATURES:tune-cortexa53-crypto = "${TUNE_FEATURES:tune-cortexa53} crypto"
15 PACKAGE_EXTRA_ARCHS:tune-cortexa53 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa53"
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
[all …]
/openbmc/u-boot/doc/
H A DREADME.rmobile4 This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
5 and Cortex-A9/A53/A57 based R-Car[2] family of SoCs. Renesas's RMOBILE/R-Car SoC
6 family contains an ARM Cortex-A9/A53/A57.
12 | R8A73A0 | KMC KZM-A9-GT [3] | kzm9g_config
13 | R8A7734 | Atmark-Techno Armadillo-800-EVA [4] | armadillo-800eva_config
17 |---------------+----------------------------------------+-------------------
18 | R8A7791 M2-W | Renesas Electronics Koelsch | koelsch_defconfig
20 |---------------+----------------------------------------+-------------------
22 |---------------+----------------------------------------+-------------------
23 | R8A7793 M2-N | Renesas Electronics Gose | gose_defconfig
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A DKconfig14 Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
33 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
34 Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
44 Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
45 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
174 default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
/openbmc/qemu/hw/arm/
H A Dimx8mp-evk.c6 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "system/address-spaces.h"
12 #include "hw/arm/fsl-imx8mp.h"
14 #include "hw/qdev-properties.h"
16 #include "qemu/error-report.h"
26 "nxp,imx8mp-fspi", in imx8mp_evk_modify_dtb()
32 offset = fdt_node_offset_by_compatible(fdt, -1, dev_str); in imx8mp_evk_modify_dtb()
39 /* Remove cpu-idle-states property from CPU nodes */ in imx8mp_evk_modify_dtb()
40 offset = fdt_node_offset_by_compatible(fdt, -1, "arm,cortex-a53"); in imx8mp_evk_modify_dtb()
42 fdt_nop_property(fdt, offset, "cpu-idle-states"); in imx8mp_evk_modify_dtb()
[all …]
/openbmc/qemu/tests/functional/
H A Dtest_aarch64_tcg_plugins.py5 # These are a little more involved than the basic tests run by check-tcg.
12 # SPDX-License-Identifier: GPL-2.0-or-later
28 KERNEL_COMMON_COMMAND_LINE = 'printk.time=1 panic=-1 '
35 vm.add_args('-kernel', kernel_path,
36 '-append', kernel_command_line,
37 '-plugin', plugin,
38 '-d', 'plugin',
39 '-D', plugin_log,
40 '-net', 'none',
41 '-no-reboot')
[all …]
H A Dtest_aarch64_raspi3.py6 # Copyright (c) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
8 # SPDX-License-Identifier: GPL-2.0-or-later
26 self.vm.add_args('-cpu', 'cortex-a53',
27 '-nodefaults',
28 '-device', f'loader,file={efi_fd},force-raw=true')
H A Dtest_aarch64_reverse_debug.py3 # SPDX-License-Identifier: GPL-2.0-or-later
13 # later. See the COPYING file in the top-level directory.
29 @skipFlakyTest("https://gitlab.com/qemu-project/qemu/-/issues/2921")
32 self.cpu = 'cortex-a53'
34 self.reverse_debugging(args=('-kernel', kernel_path))
/openbmc/u-boot/board/ti/am65x/
H A DREADME2 -------------
9 1. Wake-up (WKUP) domain:
10 - Device Management and Security Controller (DMSC)
12 - Dual Core ARM Cortex-R5F processor
14 - Quad core 64-bit ARM Cortex-A53
19 ----------
27 2. U-Boot on A53 should start other remotecores for various
29 3. In production boot flow, we might not like to use full u-boot,
32 +------------------------------------------------------------------------+
33 | DMSC | R5 | A53 |
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