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/openbmc/qemu/docs/system/arm/
H A Dhighbank.rst4 ``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
5 which has four Cortex-A9 cores.
7 ``midway`` is a model of the Calxeda Midway (ECX-2000) system,
8 which has four Cortex-A15 cores.
12 - L2x0 cache controller
13 - SP804 dual timer
14 - PL011 UART
15 - PL061 GPIOs
16 - PL031 RTC
17 - PL022 synchronous serial port controller
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/openbmc/u-boot/arch/arm/dts/
H A Dtegra114.dtsi1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra114-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra114-host1x", "simple-bus";
20 reset-names = "host1x";
22 #address-cells = <1>;
23 #size-cells = <1>;
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H A Dkeystone.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 stdout-path = &uart0;
38 gic: interrupt-controller {
39 compatible = "arm,cortex-a15-gic";
40 #interrupt-cells = <3>;
41 interrupt-controller;
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H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53", "arm,armv8";
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H A Dsun8i-v3s.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
44 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/pinctrl/sun4i-a10.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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H A Dtegra124.dtsi1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
14 interrupt-parent = <&lic>;
17 pcie-controller@01003000 {
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H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
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H A Dsun8i-a23-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
50 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
53 interrupt-parent = <&gic>;
56 #address-cells = <1>;
57 #size-cells = <1>;
61 compatible = "allwinner,simple-framebuffer",
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H A Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
55 interrupt-parent = <&gic>;
56 #address-cells = <1>;
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H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
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H A Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
54 interrupt-parent = <&gic>;
61 #address-cells = <1>;
62 #size-cells = <1>;
66 compatible = "allwinner,simple-framebuffer",
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H A Dr8a7792.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a7792-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
41 clock-frequency = <0>;
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H A Dr8a7790.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/power/r8a7790-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
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H A Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/clock/sun7i-a20-ccu.h>
51 #include <dt-bindings/reset/sun4i-a10-ccu.h>
54 interrupt-parent = <&gic>;
61 #address-cells = <1>;
62 #size-cells = <1>;
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H A Ddra7.dtsi2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
20 interrupt-parent = <&crossbar_mpu>;
46 timer {
47 compatible = "arm,armv7-timer";
52 interrupt-parent = <&gic>;
55 gic: interrupt-controller@48211000 {
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H A Dr8a7793.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7793-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
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H A Dr8a7791.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/power/r8a7791-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
45 compatible = "fixed-clock";
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/openbmc/qemu/hw/cpu/
H A Da15mpcore.c2 * Cortex-A15MPCore internal peripheral emulation.
26 #include "hw/qdev-properties.h"
35 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in a15mp_priv_set_irq()
43 memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); in a15mp_priv_initfn()
44 sysbus_init_mmio(sbd, &s->container); in a15mp_priv_initfn()
46 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); in a15mp_priv_initfn()
47 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); in a15mp_priv_initfn()
61 if (s->num_irq < 32 || s->num_irq > 256) { in a15mp_priv_realize()
62 error_setg(errp, "Property 'num-irq' must be between 32 and 256"); in a15mp_priv_realize()
66 gicdev = DEVICE(&s->gic); in a15mp_priv_realize()
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/openbmc/qemu/hw/arm/
H A Drealview.c4 * Copyright (c) 2006-2007 CodeSourcery.
16 #include "hw/core/split-irq.h"
20 #include "hw/qdev-core.h"
25 #include "qemu/error-report.h"
33 #include "target/arm/cpu-qom.h"
38 #define GIC_EXT_IRQS 64 /* Realview PBX-A9 development board */
66 qdev_prop_set_uint32(splitter, "num-lines", 2); in split_irq_from_named()
93 unsigned int smp_cpus = machine->smp.cpus; in realview_init()
100 ram_addr_t ram_size = machine->ram_size; in realview_init()
121 Object *cpuobj = object_new(machine->cpu_type); in realview_init()
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H A Dvirt.c2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
57 #include "qemu/error-report.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/pci-bridge/pci_expander_bridge.h"
61 #include "hw/virtio/virtio-pci.h"
62 #include "hw/core/sysbus-fdt.h"
63 #include "hw/platform-bus.h"
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/openbmc/
Dopengrok1.0.log1 2025-12-16 03:01:16.893-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-12-16 03:01:16.967-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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