| /openbmc/qemu/tests/unit/ |
| H A D | test-smp-parse.c | 30 * -sockets/cores/threads
36 .has_cores = hc, .cores = c, \
45 .cores = c, \
52 * -sockets/dies/modules/cores/threads
61 .has_cores = he, .cores = e, \
68 * -sockets/clusters/cores/threads
75 .has_cores = hd, .cores = d, \
82 * -drawers/books/sockets/cores/threads
91 .has_cores = he, .cores = e, \
99 * -drawers/books/sockets/dies/clusters/modules/cores/threads
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | mp.c | 77 u32 cores, cpu_up_mask = 1; in fsl_layerscape_wake_seconday_cores() local
82 /* update for secondary cores */ in fsl_layerscape_wake_seconday_cores()
88 cores = cpu_mask(); in fsl_layerscape_wake_seconday_cores()
97 printf("Waking secondary cores to start from %lx\n", gd->relocaddr); in fsl_layerscape_wake_seconday_cores()
108 rst->brrl = cores; in fsl_layerscape_wake_seconday_cores()
112 * Release the cores out of reset one-at-a-time to avoid in fsl_layerscape_wake_seconday_cores()
140 gur_out32(&gur->brrl, cores); in fsl_layerscape_wake_seconday_cores()
143 /* Bootup online cores */ in fsl_layerscape_wake_seconday_cores()
144 scfg_out32(&scfg->corebcr, cores); in fsl_layerscape_wake_seconday_cores()
148 * cores then the pre-bootloader code will trap them in a "wfe" unless in fsl_layerscape_wake_seconday_cores()
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| /openbmc/qemu/hw/core/ |
| H A D | machine-smp.c | 58 g_string_append_printf(s, " * cores (%u)", ms->smp.cores); in cpu_hierarchy_to_string()
68 * Any missing parameter in "cpus/maxcpus/sockets/cores/threads" will be
71 * In the calculation of omitted sockets/cores/threads: we prefer sockets
72 * over cores over threads before 6.2, while preferring cores over sockets
96 unsigned cores = config->has_cores ? config->cores : 0; in machine_parse_smp_config() local
112 (config->has_cores && config->cores == 0) || in machine_parse_smp_config()
167 cores = cores > 0 ? cores : 1; in machine_parse_smp_config()
173 /* prefer sockets over cores before 6.2 */ in machine_parse_smp_config()
175 cores = cores > 0 ? cores : 1; in machine_parse_smp_config()
179 modules * cores * threads); in machine_parse_smp_config()
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| /openbmc/qemu/tests/qtest/ |
| H A D | cpu-plug-test.c | 21 unsigned cores; member
38 "-smp 1,sockets=%u,cores=%u,threads=%u,maxcpus=%u", in test_plug_with_device_add()
40 td->sockets, td->cores, td->threads, td->maxcpus); in test_plug_with_device_add()
95 data->cores = 3; in add_pc_test_case()
97 data->maxcpus = data->sockets * data->cores * data->threads; in add_pc_test_case()
100 mname, data->sockets, data->cores, in add_pc_test_case()
121 data->cores = 3; in add_pseries_test_case()
123 data->maxcpus = data->sockets * data->cores * data->threads; in add_pseries_test_case()
126 mname, data->sockets, data->cores, in add_pseries_test_case()
147 data->cores = 3; in add_s390x_test_case()
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/ |
| H A D | OperatingConfig.v1_0_4.json | 36 "description": "The clock speed for a set of cores.",
37 "longDescription": "This type shall specify the clock speed for a set of cores.",
54 "description": "The clock speed to configure the set of cores in MHz.",
55 …gDescription": "This property shall contain the clock speed to configure the set of cores in MHz.",
65 "description": "The number of cores to configure with a specified speed.",
66 …"longDescription": "This property shall contain the number of cores to configure with the speed sp…
75 … "description": "The identifier of the cores to configure with the specified speed.",
82 …"longDescription": "This property shall contain an array identifying the cores to configure with t…
158 … "description": "The clock speed for sets of cores when the configuration is operational.",
169 …hall contain an array of objects that specify the clock speed for sets of cores when the configura…
[all …]
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/ |
| H A D | OperatingConfig.v1_0_4.json | 36 "description": "The clock speed for a set of cores.",
37 "longDescription": "This type shall specify the clock speed for a set of cores.",
54 "description": "The clock speed to configure the set of cores in MHz.",
55 …gDescription": "This property shall contain the clock speed to configure the set of cores in MHz.",
65 "description": "The number of cores to configure with a specified speed.",
66 …"longDescription": "This property shall contain the number of cores to configure with the speed sp…
75 … "description": "The identifier of the cores to configure with the specified speed.",
82 …"longDescription": "This property shall contain an array identifying the cores to configure with t…
158 … "description": "The clock speed for sets of cores when the configuration is operational.",
169 …hall contain an array of objects that specify the clock speed for sets of cores when the configura…
[all …]
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| /openbmc/bmcweb/redfish-core/schema/dmtf/csdl/ |
| H A D | OperatingConfig_v1.xml | 72 …<Annotation Term="OData.Description" String="The number of cores in the processor that can be conf…
73 …"OData.LongDescription" String="This property shall contain the number of cores in the processor t…
104 …<Annotation Term="OData.Description" String="The clock speed for sets of cores when the configurat…
105 …hall contain an array of objects that specify the clock speed for sets of cores when the configura…
108 …. A turbo profile is the maximum turbo clock speed as a function of the number of active cores."/>
109 …erty shall contain an array of objects that specify the turbo profile for a set of active cores."/>
119 <Annotation Term="OData.Description" String="The turbo profile for a set of active cores."/>
120 …ta.LongDescription" String="This type shall specify the turbo profile for a set of active cores."/>
123 …<Annotation Term="OData.Description" String="The number of active cores to be configured with the …
124 …"OData.LongDescription" String="This property shall contain the number of cores to be configured w…
[all …]
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| /openbmc/bmcweb/redfish-core/schema/dmtf/installed/ |
| H A D | OperatingConfig_v1.xml | 72 …<Annotation Term="OData.Description" String="The number of cores in the processor that can be conf…
73 …"OData.LongDescription" String="This property shall contain the number of cores in the processor t…
104 …<Annotation Term="OData.Description" String="The clock speed for sets of cores when the configurat…
105 …hall contain an array of objects that specify the clock speed for sets of cores when the configura…
108 …. A turbo profile is the maximum turbo clock speed as a function of the number of active cores."/>
109 …erty shall contain an array of objects that specify the turbo profile for a set of active cores."/>
119 <Annotation Term="OData.Description" String="The turbo profile for a set of active cores."/>
120 …ta.LongDescription" String="This type shall specify the turbo profile for a set of active cores."/>
123 …<Annotation Term="OData.Description" String="The number of active cores to be configured with the …
124 …"OData.LongDescription" String="This property shall contain the number of cores to be configured w…
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| /openbmc/u-boot/doc/ |
| H A D | README.mpc85xx-spin-table | 6 __secondary_start_page. For other cores to use the spin table, the booting
12 page translation for secondary cores to use this page of memory. Then 4KB
17 that secondary cores can see it.
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
|
| H A D | README.Heterogeneous-SoCs | 5 configuration and frequencies of all PowerPC cores and devices
7 SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc.
19 Code added in this file to print the DSP cores and other device's(CPRI,
25 required cores and devices from RCW and System frequency
29 Added API to get the number of SC cores in running system and Their BIT
44 Global structure updated for dsp cores and other components
73 DSP cores and other device's components have been added in this structure.
|
| H A D | README.srio-pcie-boot-corenet | 22 the boot location to SRIO or PCIE, and holdoff all the cores.
37 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
44 2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
70 h) Since all cores of slave in holdoff, slave should be powered on before
85 1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
|
| /openbmc/u-boot/drivers/cpu/ |
| H A D | mpc83xx_cpu.h | 11 * enum e300_type - Identifiers for e300 cores
12 * @E300C1: Identifier for e300c1 cores
13 * @E300C2: Identifier for e300c2 cores
14 * @E300C3: Identifier for e300c3 cores
15 * @E300C4: Identifier for e300c4 cores
16 * @E300_UNKNOWN: Identifier for unknown e300 cores
|
| H A D | Kconfig | 15 Support CPU cores for SoCs of the MPC83xx series.
21 Support CPU cores for RISC-V architecture.
|
| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/Cpu/ |
| H A D | OperatingConfig.interface.yaml | 14 cores when the configuration is operational. Each entry contains two
39 The number of cores in the processor that can be used in this
47 cores. Each entry contains two members, first is the maximum turbo
48 clock speed in MHz, and second is number of cores which can run at
|
| /openbmc/qemu/docs/system/arm/ |
| H A D | raspi.rst | 10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
|
| H A D | nuvoton.rst | 7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
31 The NPCM8xx SoC is the successor of the NPCM7xx SoC. It has 4 Cortex-A35 cores.
|
| H A D | highbank.rst | 5 which has four Cortex-A9 cores.
8 which has four Cortex-A15 cores.
|
| /openbmc/u-boot/drivers/axi/ |
| H A D | Kconfig | 7 communication with IP cores in Xilinx FPGAs).
23 IP cores in the FPGA (e.g. video transmitter cores).
|
| /openbmc/qemu/target/ppc/ |
| H A D | cpu-models.h | 44 /* PowerPC 405 cores */
69 /* Xilinx cores */
75 /* PowerPC 440 cores */
93 /* Freescale embedded PowerPC cores */
94 /* PowerPC MPC 5xx cores (aka RCPU) */
96 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
98 /* G2 cores (aka PowerQUICC-II) */
120 /* e200 cores */
124 /* e300 cores */
133 /* e500 cores */
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| /openbmc/qemu/include/hw/s390x/ |
| H A D | cpu-topology.h | 68 return (n / smp->cores) % smp->sockets; in s390_std_socket()
73 return (n / (smp->cores * smp->sockets)) % smp->books; in s390_std_book()
78 return (n / (smp->cores * smp->sockets * smp->books)) % smp->drawers; in s390_std_drawer()
|
| /openbmc/qemu/docs/system/s390x/ |
| H A D | cpu-topology.rst | 67 -smp cpus=5,drawer=1,books=1,sockets=8,cores=4,maxcpus=32
73 -smp cpus=5,sockets=8,cores=4,maxcpus=32
133 In the following machine we define 8 sockets with 4 cores each.
139 -smp cpus=5,sockets=8,cores=4,maxcpus=32 \
155 As we have 4 cores in a socket, we have 4 CPUs provided
223 For example, here we set the position of the cores 1,2,3 to
224 drawer 1, book 1, socket 2 and cores 0,9 and 14 to drawer 0,
234 -smp cpus=1,sockets=8,cores=4,maxcpus=32 \
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| /openbmc/qemu/docs/system/ppc/ |
| H A D | powernv.rst | 77 $ qemu-system-ppc64 -m 2G -machine powernv9 -smp 2,cores=2,threads=1 \
114 $ qemu-system-ppc64 -m 2G -machine powernv9 -smp 2,cores=2,threads=1 -accel tcg,thread=single \
149 number of cores. ``-smp 2,cores=1`` will define a machine with 2
150 sockets of 1 core, whereas ``-smp 2,cores=2`` will define a machine
151 with 1 socket of 2 cores. ``-smp 8,cores=2``, 4 sockets of 2 cores.
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| /openbmc/qemu/contrib/plugins/ |
| H A D | cache.c | 98 static int cores; variable
294 caches = g_new(Cache *, cores); in caches_init()
296 for (i = 0; i < cores; i++) { in caches_init()
403 cache_idx = vcpu_index % cores; in vcpu_mem_access()
439 cache_idx = vcpu_index % cores; in vcpu_insn_exec()
527 for (i = 0; i < cores; i++) { in caches_free()
565 g_assert(cores > 1); in sum_stats()
566 for (i = 0; i < cores; i++) { in sum_stats()
618 for (i = 0; i < cores; i++) { in log_stats()
629 if (cores > 1) { in log_stats()
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| /openbmc/u-boot/board/synopsys/axs10x/ |
| H A D | axs10x.c | 72 /* All cores have reset vector pointing to 0 */ in smp_set_core_boot_addr()
75 /* Make sure other cores see written value in memory */ in smp_set_core_boot_addr()
90 * We used to have a generic START bit for all cores selected by CORE_SEL mask. in smp_kick_all_cpus()
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| /openbmc/u-boot/arch/arm/cpu/armv8/ |
| H A D | Kconfig | 18 bool "Enable data coherency with other cores in cluster"
23 For A53, it enables data coherency with other cores in the
26 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
145 of CPU cores, platforms with asymmetric clusters don't apply here.
|