183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
265fcba12SAlexey Brodkin /*
365fcba12SAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
465fcba12SAlexey Brodkin */
565fcba12SAlexey Brodkin
665fcba12SAlexey Brodkin #include <common.h>
765fcba12SAlexey Brodkin #include <dwmmc.h>
865fcba12SAlexey Brodkin #include <malloc.h>
92a5062caSAlexey Brodkin #include <asm/arcregs.h>
1065fcba12SAlexey Brodkin #include "axs10x.h"
1165fcba12SAlexey Brodkin
1265fcba12SAlexey Brodkin DECLARE_GLOBAL_DATA_PTR;
1365fcba12SAlexey Brodkin
board_mmc_init(bd_t * bis)1465fcba12SAlexey Brodkin int board_mmc_init(bd_t *bis)
1565fcba12SAlexey Brodkin {
1665fcba12SAlexey Brodkin struct dwmci_host *host = NULL;
1765fcba12SAlexey Brodkin
1865fcba12SAlexey Brodkin host = malloc(sizeof(struct dwmci_host));
1965fcba12SAlexey Brodkin if (!host) {
2065fcba12SAlexey Brodkin printf("dwmci_host malloc fail!\n");
2165fcba12SAlexey Brodkin return 1;
2265fcba12SAlexey Brodkin }
2365fcba12SAlexey Brodkin
2465fcba12SAlexey Brodkin memset(host, 0, sizeof(struct dwmci_host));
2565fcba12SAlexey Brodkin host->name = "Synopsys Mobile storage";
2665fcba12SAlexey Brodkin host->ioaddr = (void *)ARC_DWMMC_BASE;
2765fcba12SAlexey Brodkin host->buswidth = 4;
2865fcba12SAlexey Brodkin host->dev_index = 0;
2965fcba12SAlexey Brodkin host->bus_hz = 50000000;
3065fcba12SAlexey Brodkin
3165fcba12SAlexey Brodkin add_dwmci(host, host->bus_hz / 2, 400000);
3265fcba12SAlexey Brodkin
3365fcba12SAlexey Brodkin return 0;
3465fcba12SAlexey Brodkin }
3565fcba12SAlexey Brodkin
board_mmc_getcd(struct mmc * mmc)369f87d470SAlexey Brodkin int board_mmc_getcd(struct mmc *mmc)
379f87d470SAlexey Brodkin {
389f87d470SAlexey Brodkin struct dwmci_host *host = mmc->priv;
399f87d470SAlexey Brodkin
409f87d470SAlexey Brodkin return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
419f87d470SAlexey Brodkin }
429f87d470SAlexey Brodkin
4365fcba12SAlexey Brodkin #define AXS_MB_CREG 0xE0011000
4465fcba12SAlexey Brodkin
board_early_init_f(void)4565fcba12SAlexey Brodkin int board_early_init_f(void)
4665fcba12SAlexey Brodkin {
4765fcba12SAlexey Brodkin if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
4865fcba12SAlexey Brodkin gd->board_type = AXS_MB_V3;
4965fcba12SAlexey Brodkin else
5065fcba12SAlexey Brodkin gd->board_type = AXS_MB_V2;
5165fcba12SAlexey Brodkin
5265fcba12SAlexey Brodkin return 0;
5365fcba12SAlexey Brodkin }
5465fcba12SAlexey Brodkin
5565fcba12SAlexey Brodkin #ifdef CONFIG_ISA_ARCV2
56f665c14fSEugeniy Paltsev
board_jump_and_run(ulong entry,int zero,int arch,uint params)57f665c14fSEugeniy Paltsev void board_jump_and_run(ulong entry, int zero, int arch, uint params)
58f665c14fSEugeniy Paltsev {
59f665c14fSEugeniy Paltsev void (*kernel_entry)(int zero, int arch, uint params);
60f665c14fSEugeniy Paltsev
61f665c14fSEugeniy Paltsev kernel_entry = (void (*)(int, int, uint))entry;
62f665c14fSEugeniy Paltsev
63f665c14fSEugeniy Paltsev smp_set_core_boot_addr(entry, -1);
64f665c14fSEugeniy Paltsev smp_kick_all_cpus();
65f665c14fSEugeniy Paltsev kernel_entry(zero, arch, params);
66f665c14fSEugeniy Paltsev }
67f665c14fSEugeniy Paltsev
6865fcba12SAlexey Brodkin #define RESET_VECTOR_ADDR 0x0
6965fcba12SAlexey Brodkin
smp_set_core_boot_addr(unsigned long addr,int corenr)7065fcba12SAlexey Brodkin void smp_set_core_boot_addr(unsigned long addr, int corenr)
7165fcba12SAlexey Brodkin {
7265fcba12SAlexey Brodkin /* All cores have reset vector pointing to 0 */
7365fcba12SAlexey Brodkin writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
7465fcba12SAlexey Brodkin
7565fcba12SAlexey Brodkin /* Make sure other cores see written value in memory */
7665fcba12SAlexey Brodkin flush_dcache_all();
7765fcba12SAlexey Brodkin }
7865fcba12SAlexey Brodkin
smp_kick_all_cpus(void)7965fcba12SAlexey Brodkin void smp_kick_all_cpus(void)
8065fcba12SAlexey Brodkin {
8165fcba12SAlexey Brodkin /* CPU start CREG */
8265fcba12SAlexey Brodkin #define AXC003_CREG_CPU_START 0xF0001400
8365fcba12SAlexey Brodkin /* Bits positions in CPU start CREG */
8465fcba12SAlexey Brodkin #define BITS_START 0
850b0db98bSAlexey Brodkin #define BITS_START_MODE 4
8665fcba12SAlexey Brodkin #define BITS_CORE_SEL 9
8765fcba12SAlexey Brodkin
882a5062caSAlexey Brodkin /*
892a5062caSAlexey Brodkin * In axs103 v1.1 START bits semantics has changed quite a bit.
902a5062caSAlexey Brodkin * We used to have a generic START bit for all cores selected by CORE_SEL mask.
912a5062caSAlexey Brodkin * But now we don't touch CORE_SEL at all because we have a dedicated START bit
922a5062caSAlexey Brodkin * for each core:
932a5062caSAlexey Brodkin * bit 0: Core 0 (master)
942a5062caSAlexey Brodkin * bit 1: Core 1 (slave)
952a5062caSAlexey Brodkin */
962a5062caSAlexey Brodkin #define BITS_START_CORE1 1
972a5062caSAlexey Brodkin
982a5062caSAlexey Brodkin #define ARCVER_HS38_3_0 0x53
992a5062caSAlexey Brodkin
1002a5062caSAlexey Brodkin int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
1010b0db98bSAlexey Brodkin int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
1022a5062caSAlexey Brodkin
1032a5062caSAlexey Brodkin if (core_family < ARCVER_HS38_3_0) {
1040b0db98bSAlexey Brodkin cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
1050b0db98bSAlexey Brodkin cmd &= ~(1 << BITS_START_MODE);
1062a5062caSAlexey Brodkin } else {
1072a5062caSAlexey Brodkin cmd |= (1 << BITS_START_CORE1);
1082a5062caSAlexey Brodkin }
1090b0db98bSAlexey Brodkin writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
11065fcba12SAlexey Brodkin }
11165fcba12SAlexey Brodkin #endif
112*6ef705b1SAlexey Brodkin
checkboard(void)113*6ef705b1SAlexey Brodkin int checkboard(void)
114*6ef705b1SAlexey Brodkin {
115*6ef705b1SAlexey Brodkin printf("Board: ARC Software Development Platform AXS%s\n",
116*6ef705b1SAlexey Brodkin is_isa_arcv2() ? "103" : "101");
117*6ef705b1SAlexey Brodkin
118*6ef705b1SAlexey Brodkin return 0;
119*6ef705b1SAlexey Brodkin };
120