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/openbmc/linux/drivers/greybus/
H A Dcontrol.c3 * Greybus CPort control protocol.
14 /* Highest control-protocol version supported */
18 static int gb_control_get_version(struct gb_control *control) in gb_control_get_version() argument
20 struct gb_interface *intf = control->connection->intf; in gb_control_get_version()
28 ret = gb_operation_sync(control->connection, in gb_control_get_version()
34 "failed to get control-protocol version: %d\n", in gb_control_get_version()
41 "unsupported major control-protocol version (%u > %u)\n", in gb_control_get_version()
46 control->protocol_major = response.major; in gb_control_get_version()
47 control->protocol_minor = response.minor; in gb_control_get_version()
55 static int gb_control_get_bundle_version(struct gb_control *control, in gb_control_get_bundle_version() argument
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/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dhighlander.h13 #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
14 #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
19 #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
20 #define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
21 #define PA_PCICD (PA_BCR+0x0010) /* PCI Connector detect control */
22 #define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
23 #define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
24 #define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
25 #define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
26 #define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
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/openbmc/linux/drivers/pinctrl/renesas/
H A DKconfig9 bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
57 This enables pin control drivers for Renesas SuperH and ARM platforms
65 This enables common pin control functionality for EMMA Mobile, R-Car,
73 This enables pin control and GPIO drivers for SH/SH Mobile platforms
82 bool "pin control support for Emma Mobile EV2" if COMPILE_TEST
86 bool "pin control support for R-Car D3" if COMPILE_TEST
90 bool "pin control support for R-Car E2" if COMPILE_TEST
94 bool "pin control support for R-Car E3" if COMPILE_TEST
98 bool "pin control support for R-Car H1" if COMPILE_TEST
102 bool "pin control support for R-Car H2" if COMPILE_TEST
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/openbmc/linux/include/media/
H A Dv4l2-ctrls.h29 * union v4l2_ctrl_ptr - A pointer to a control value.
109 * struct v4l2_ctrl_ops - The control operations that the driver has to provide.
111 * @g_volatile_ctrl: Get a new value for this control. Generally only relevant
112 * for volatile (and usually read-only) controls such as a control
116 * @try_ctrl: Test whether the control's value is valid. Only relevant when
118 * @s_ctrl: Actually set the new control value. s_ctrl is compulsory. The
129 * struct v4l2_ctrl_type_ops - The control type operations that the driver
149 * that should be called when a control value has changed.
152 * @priv: control private data
160 * struct v4l2_ctrl - The control structure.
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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun50i_h6.h13 u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
15 u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
17 u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
19 u32 pll_periph1_cfg; /* 0x028 pll periph1 control */
21 u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
23 u32 pll3_cfg; /* 0x040 pll3 (video0) control */
25 u32 pll_video1_cfg; /* 0x048 pll video1 control */
27 u32 pll4_cfg; /* 0x058 pll4 (ve) control */
29 u32 pll10_cfg; /* 0x060 pll10 (de) control */
31 u32 pll9_cfg; /* 0x070 pll9 (hsic) control */
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/openbmc/linux/include/sound/
H A Dseq_midi_emul.h35 unsigned char control[128]; /* Current value of all controls */ member
73 void (*control)(void *private_data, int type, struct snd_midi_channel *chan); member
94 #define gm_bank_select control[0]
95 #define gm_modulation control[1]
96 #define gm_breath control[2]
97 #define gm_foot_pedal control[4]
98 #define gm_portamento_time control[5]
99 #define gm_data_entry control[6]
100 #define gm_volume control[7]
101 #define gm_balance control[8]
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ras_eeprom.c128 * add to control->i2c_address, and then tell I2C layer to read
171 struct amdgpu_ras_eeprom_control *control) in __get_eeprom_i2c_addr() argument
176 if (!control) in __get_eeprom_i2c_addr()
189 control->i2c_address = ((u32) i2c_addr) << 16; in __get_eeprom_i2c_addr()
198 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
202 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
204 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
207 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
212 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
214 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
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/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DControl.v1_5_2.json2 "$id": "http://redfish.dmtf.org/schemas/v1/Control.v1_5_2.json",
3 "$ref": "#/definitions/Control",
26 "#Control.ResetToDefaults": {
37 "Control": { object
39 "description": "The `Control` schema describes a control point and its properties.",
40 … "longDescription": "This resource shall represent a control point for a Redfish implementation.",
86 "description": "The maximum possible setting for this control.",
87 "excerpt": "Control",
88 …mum possible value of the `SetPoint` or `SettingMax` properties for this control. Services shall …
96 "description": "The minimum possible setting for this control.",
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/openbmc/u-boot/drivers/pinctrl/renesas/
H A DKconfig4 bool "Renesas pin control drivers"
10 bool "Renesas RCar Gen2 R8A7790 pin control driver"
13 Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs.
16 the GPIO definitions and pin control functions for each available
20 bool "Renesas RCar Gen2 R8A7791 pin control driver"
23 Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs.
26 the GPIO definitions and pin control functions for each available
30 bool "Renesas RCar Gen2 R8A7792 pin control driver"
33 Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs.
36 the GPIO definitions and pin control functions for each available
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/openbmc/linux/Documentation/userspace-api/media/drivers/
H A Duvcvideo.rst28 control enumeration.
37 Control mappings
41 control mappings at runtime. These allow for individual XU controls or byte
45 triggers a read or write of the associated XU control.
47 The ioctl used to create these control mappings is called UVCIOC_CTRL_MAP.
49 beforehand (UVCIOC_CTRL_ADD) to pass XU control information to the UVC driver.
57 3. Driver specific XU control interface
65 directly map to the low-level UVC control requests.
67 In order to make such a request the UVC unit ID of the control's extension unit
68 and the control selector need to be known. This information either needs to be
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/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DControl_v1.xml4 <!--# Redfish Schema: Control v1.5.2 -->
40 <Schema xmlns="http://docs.oasis-open.org/odata/ns/edm" Namespace="Control">
44 <EntityType Name="Control" BaseType="Resource.v1_0_0.Resource" Abstract="true">
45 …<Annotation Term="OData.Description" String="The `Control` schema describes a control point and it…
46 …<Annotation Term="OData.LongDescription" String="This resource shall represent a control point for…
73 <Parameter Name="Control" Type="Control.v1_0_0.Actions"/>
85 <Schema xmlns="http://docs.oasis-open.org/odata/ns/edm" Namespace="Control.v1_0_0">
89 <EntityType Name="Control" BaseType="Control.Control">
90 <Property Name="ControlType" Type="Control.v1_0_0.ControlType">
92 <Annotation Term="OData.Description" String="The type of control."/>
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/openbmc/linux/include/linux/mfd/
H A Dmotorola-cpcap.h47 #define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */
48 #define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */
54 #define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */
55 #define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */
60 #define CPCAP_REG_PGC 0x0228 /* Power Gate and Control */
66 #define CPCAP_REG_SCC 0x0400 /* System Clock Control */
80 #define CPCAP_REG_SI2CC1 0x0604 /* Switcher I2C Control 1 */
81 #define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */
82 #define CPCAP_REG_S1C1 0x060c /* Switcher 1 Control 1 */
83 #define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */
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/openbmc/linux/drivers/tty/vt/
H A Ddefkeymap.map7 # altgr control keycode 83 = Boot
8 # altgr control keycode 111 = Boot
20 control keycode 3 = nul
21 shift control keycode 3 = nul
24 control keycode 4 = Escape
27 control keycode 5 = Control_backslash
30 control keycode 6 = Control_bracketright
33 control keycode 7 = Control_asciicircum
36 control keycode 8 = Control_underscore
39 control keycode 9 = Delete
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/openbmc/linux/include/linux/greybus/
H A Dcontrol.h3 * Greybus CPort control protocol
33 int gb_control_enable(struct gb_control *control);
34 void gb_control_disable(struct gb_control *control);
35 int gb_control_suspend(struct gb_control *control);
36 int gb_control_resume(struct gb_control *control);
37 int gb_control_add(struct gb_control *control);
38 void gb_control_del(struct gb_control *control);
39 struct gb_control *gb_control_get(struct gb_control *control);
40 void gb_control_put(struct gb_control *control);
42 int gb_control_get_bundle_versions(struct gb_control *control);
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/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.h36 #define B43_LPPHY_TSSI_CTL B43_PHY_CCK(0x28) /* TSSI Control */
80 #define B43_LPPHY_FINEDIGIGAIN_CTL B43_PHY_CCK(0x67) /* FineDigiGain Control */
106 #define B43_LPPHY_CRSGAIN_CTL B43_PHY_OFDM(0x10) /* crsgain Control */
117 #define B43_LPPHY_LTRN_CTL B43_PHY_OFDM(0x1B) /* LTRN Control */
123 #define B43_LPPHY_OFDMSYNCTIMER_CTL B43_PHY_OFDM(0x21) /* ofdmSyncTimer Control */
141 #define B43_LPPHY_PHASE_SHIFT_CTL B43_PHY_OFDM(0x33) /* phase shift Control */
143 #define B43_LPPHY_OFDM_SYNC_CTL B43_PHY_OFDM(0x35) /* ofdm sync Control */
144 #define B43_LPPHY_AFE_ADC_CTL_0 B43_PHY_OFDM(0x36) /* Afe ADC Control 0 */
145 #define B43_LPPHY_AFE_ADC_CTL_1 B43_PHY_OFDM(0x37) /* Afe ADC Control 1 */
146 #define B43_LPPHY_AFE_ADC_CTL_2 B43_PHY_OFDM(0x38) /* Afe ADC Control 2 */
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/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dclk.h14 /* Clocking and Power Control Registers */
17 u32 boot_map; /* Boot Map Control Register */
30 /* Clock Control Registers */
31 u32 hclkdiv_ctrl; /* HCLK Divider Control Register */
32 u32 pwr_ctrl; /* Power Control Register */
33 u32 pll397_ctrl; /* PLL397 Control Register */
34 u32 osc_ctrl; /* Main Oscillator Control Register */
35 u32 sysclk_ctrl; /* SYSCLK Control Register */
36 u32 lcdclk_ctrl; /* LCD Clock Control Register */
37 u32 hclkpll_ctrl; /* HCLK PLL Control Register */
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/openbmc/linux/drivers/pinctrl/mediatek/
H A DKconfig51 bool "MediaTek MT7620 pin control"
58 bool "MediaTek MT7621 pin control"
65 bool "MediaTek MT76X8 pin control"
72 bool "Ralink RT2880 pin control"
79 bool "Ralink RT305X pin control"
86 bool "Ralink RT3883 pin control"
94 bool "MediaTek MT2701 pin control"
101 bool "MediaTek MT7623 pin control with generic binding"
108 bool "MediaTek MT7629 pin control"
115 bool "MediaTek MT8135 pin control"
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/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dextended-controls.rst13 The control mechanism as originally designed was meant to be used for
19 implementing this extended control mechanism: the MPEG standard is quite
27 Unfortunately, the original control API lacked some features needed for
29 named) extended control API.
32 Extended Control API, nowadays there are also other classes of Extended
38 The Extended Control API
48 control). This is needed since it is often required to atomically change
53 contains a pointer to the control array, a count of the number of
54 controls in that array and a control class. Control classes are used to
55 group similar controls into a single class. For example, control class
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H A Dvidioc-queryctrl.rst13 VIDIOC_QUERYCTRL - VIDIOC_QUERY_EXT_CTRL - VIDIOC_QUERYMENU - Enumerate controls and menu control i…
41 To query the attributes of a control applications set the ``id`` field
49 exclusive ``V4L2_CID_LASTP1``. Drivers may return ``EINVAL`` if a control in
56 in the ``flags`` field this control is permanently disabled and should
60 driver returns the next supported non-compound control, or ``EINVAL`` if
63 type ≥ ``V4L2_CTRL_COMPOUND_TYPES`` and/or array control, in other words
71 control information that cannot be returned in struct
95 See also the examples in :ref:`control`.
110 - Identifies the control, set by the application. See
111 :ref:`control-id` for predefined IDs. When the ID is ORed with
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H A Dvidioc-g-ext-ctrls.rst13 …C_S_EXT_CTRLS - VIDIOC_TRY_EXT_CTRLS - Get or set the value of several controls, try control values
43 atomically. Control IDs are grouped into control classes (see
44 :ref:`ctrl-class`) and all controls in the control array must belong
45 to the same control class.
60 If the ``size`` is too small to receive the control result (only
79 control values are valid.
93 :c:type:`v4l2_ext_control`. If the new control value
95 control), then this will also result in an ``EINVAL`` error code error.
116 The driver will only set/get these controls if all control values are
138 - Identifies the control, set by the application.
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/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmc_me_regs.h112 /* DEC200 Peripheral Control Register */
114 /* 2D-ACE Peripheral Control Register */
116 /* ENET Peripheral Control Register */
118 /* DMACHMUX0 Peripheral Control Register */
120 /* CSI0 Peripheral Control Register */
122 /* MMDC0 Peripheral Control Register */
124 /* FRAY Peripheral Control Register */
126 /* PIT0 Peripheral Control Register */
128 /* FlexTIMER0 Peripheral Control Register */
130 /* SARADC0 Peripheral Control Register */
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/openbmc/linux/drivers/media/i2c/
H A Dadv7183_regs.h11 #define ADV7183_IN_CTRL 0x00 /* Input control */
13 #define ADV7183_OUT_CTRL 0x03 /* Output control */
14 #define ADV7183_EXT_OUT_CTRL 0x04 /* Extended output control */
21 #define ADV7183_ADI_CTRL 0x0E /* ADI control */
27 #define ADV7183_ANAL_CLAMP_CTRL 0x14 /* Analog clamp control */
28 #define ADV7183_DIGI_CLAMP_CTRL_1 0x15 /* Digital clamp control 1 */
29 #define ADV7183_SHAP_FILT_CTRL 0x17 /* Shaping filter control */
30 #define ADV7183_SHAP_FILT_CTRL_2 0x18 /* Shaping filter control 2 */
31 #define ADV7183_COMB_FILT_CTRL 0x19 /* Comb filter control */
32 #define ADV7183_ADI_CTRL_2 0x1D /* ADI control 2 */
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/openbmc/phosphor-dbus-interfaces/gen/xyz/openbmc_project/Control/
H A Dmeson.build5 'xyz/openbmc_project/Control/CFMLimit__markdown'.underscorify(),
6 input: [ '../../../../yaml/xyz/openbmc_project/Control/CFMLimit.interface.yaml', ],
14 'xyz/openbmc_project/Control/CFMLimit',
20 'xyz/openbmc_project/Control/ChassisCapabilities__markdown'.underscorify(),
21 input: [ '../../../../yaml/xyz/openbmc_project/Control/ChassisCapabilities.interface.yaml', ],
29 'xyz/openbmc_project/Control/ChassisCapabilities',
35 'xyz/openbmc_project/Control/Device__markdown'.underscorify(),
36 input: [ '../../../../yaml/xyz/openbmc_project/Control/Device.errors.yaml', ],
44 'xyz/openbmc_project/Control/Device',
50 'xyz/openbmc_project/Control/FanPwm__markdown'.underscorify(),
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/openbmc/openbmc/meta-ampere/meta-mitchell/recipes-phosphor/fans/phosphor-fan/
H A Dmonitor.json14 "target_interface": "xyz.openbmc_project.Control.FanPwm",
15 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM7",
22 "target_interface": "xyz.openbmc_project.Control.FanPwm",
23 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM7",
40 "target_interface": "xyz.openbmc_project.Control.FanPwm",
41 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM5",
48 "target_interface": "xyz.openbmc_project.Control.FanPwm",
49 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM5",
66 "target_interface": "xyz.openbmc_project.Control.FanPwm",
67 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM4",
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/openbmc/openbmc/meta-ampere/meta-jade/recipes-phosphor/fans/phosphor-fan/mtjade/
H A Dmonitor.json14 "target_interface": "xyz.openbmc_project.Control.FanPwm",
15 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM3",
22 "target_interface": "xyz.openbmc_project.Control.FanPwm",
23 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM3",
40 "target_interface": "xyz.openbmc_project.Control.FanPwm",
41 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM4",
48 "target_interface": "xyz.openbmc_project.Control.FanPwm",
49 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM4",
66 "target_interface": "xyz.openbmc_project.Control.FanPwm",
67 "target_path": "/xyz/openbmc_project/control/fanpwm/PWM5",
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